From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 825912D6E4D for ; Tue, 12 Aug 2025 05:02:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974933; cv=none; b=c4PS3y5j7tHn3qLFlVqmcW1p7n7vH8qSo0hZuqTOb3T4sw7wRoCCwWKtKTsHLsNYG6G816nRJDchBb4FGBAN4djWY4RTKC7dHNNVoeKkqz6JXEhTIos0lbcCLFBlGh1EjPv2LurQl1dUpFDzhM3d4NsYg4TUL9p3laSHnVPH+/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754974933; c=relaxed/simple; bh=wjjg7SJLEPBbQK2Tv7ARwQeoj+DFGdvzSzjAKKngXOY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=rBSg0yG7f6AVpzu4sF3JYga0zNRt5bLQxz71glyXNv38TdANp5hIelLKTXt3oa3GaC5+Uqbn7zYMkFMs4nRdHX46RK929DJxSp0hU4do9JAr7FCwNLfHPJJV7hxQrU7t+dkdimsYJc+y7UYgPlwYOSagngWQkIkVAV9NYuY6WU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=UNYFGLHS; arc=none smtp.client-ip=203.254.224.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="UNYFGLHS" Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20250812050203epoutp02476516565186ddaf313d58697700f69b~a7GUNY7Ln0945609456epoutp02z for ; Tue, 12 Aug 2025 05:02:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250812050203epoutp02476516565186ddaf313d58697700f69b~a7GUNY7Ln0945609456epoutp02z DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1754974923; bh=2IA86F4zckPMij9e7yGYro0kXu5bh8Py7lV8n/0sesc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UNYFGLHSBeDvYC1mRmZqxpKZrLEDeqMMD2zqXQqSTdgS6alssz6eAyb7tJxgh/hkM bd/vYlTl5Wwx93crmmvfrAK4JAjJuhTgeK3NYgQOhRGq+RSiFIuhQWobJ3FuYgXZxF d1qp3Ee0TRl25xSYTCT2hrmxvVwL0G/M5bvchOa8= Received: from epsnrtp01.localdomain (unknown [182.195.42.153]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPS id 20250812050202epcas5p31f271fb43f33f8ab6f0f022b0231d2eb~a7GTkYNaO3131631316epcas5p3r; Tue, 12 Aug 2025 05:02:02 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.95]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c1K9j5t1yz6B9mF; Tue, 12 Aug 2025 05:02:01 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250811154655epcas5p211bd14152fa48635fc5c1daceb963e71~awQERWW4V0377703777epcas5p2f; Mon, 11 Aug 2025 15:46:55 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154652epsmtip112e87d107f6556973ea2463d4c2cb28a~awQBic9oH2101521015epsmtip1C; Mon, 11 Aug 2025 15:46:52 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi , Hrishikesh Dileep Subject: [PATCH v3 01/12] PCI: exynos: Remove unused MACROs in exynos PCIe file Date: Mon, 11 Aug 2025 21:16:27 +0530 Message-ID: <20250811154638.95732-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154655epcas5p211bd14152fa48635fc5c1daceb963e71 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154655epcas5p211bd14152fa48635fc5c1daceb963e71 References: <20250811154638.95732-1-shradha.t@samsung.com> Some MACROs are defined in the exynos PCIe file but are not used anywhere within the file. Remove such unused MACROs. Suggested-by: Hrishikesh Dileep Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 1f0e98d07109..f9140d1f1d19 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -31,8 +31,6 @@ #define IRQ_INTB_ASSERT BIT(2) #define IRQ_INTC_ASSERT BIT(4) #define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_LEVEL 0x004 -#define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 #define PCIE_IRQ_EN_SPECIAL 0x014 --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACA511991D4 for ; Tue, 12 Aug 2025 05:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 12 Aug 2025 05:02:05 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.94]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c1K9m5Y4Dz2SSKd; Tue, 12 Aug 2025 05:02:04 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51~awQIcaq_x2692426924epcas5p10; Mon, 11 Aug 2025 15:46:59 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154656epsmtip1d9d756f77820130ac933dbc336675fc2~awQF0WLN42450724507epsmtip1v; Mon, 11 Aug 2025 15:46:56 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 02/12] PCI: exynos: Change macro names to exynos specific Date: Mon, 11 Aug 2025 21:16:28 +0530 Message-ID: <20250811154638.95732-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51 References: <20250811154638.95732-1-shradha.t@samsung.com> Prefix macro names in exynos file with the term "EXYNOS" as the current macro names seem to be generic to PCIe. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 112 ++++++++++++------------ 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index f9140d1f1d19..30d12ff9b0c6 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -26,28 +26,28 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) =20 /* PCIe ELBI registers */ -#define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT BIT(0) -#define IRQ_INTB_ASSERT BIT(2) -#define IRQ_INTC_ASSERT BIT(4) -#define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_EN_PULSE 0x00c -#define PCIE_IRQ_EN_LEVEL 0x010 -#define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_SW_WAKE 0x018 -#define PCIE_BUS_EN BIT(1) -#define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE BIT(0) -#define PCIE_STICKY_RESET 0x020 -#define PCIE_NONSTICKY_RESET 0x024 -#define PCIE_APP_INIT_RESET 0x028 -#define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x074 -#define PCIE_ELBI_XMLH_LINKUP BIT(4) -#define PCIE_ELBI_LTSSM_ENABLE 0x1 -#define PCIE_ELBI_SLV_AWMISC 0x11c -#define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 +#define EXYNOS_PCIE_SW_WAKE 0x018 +#define EXYNOS_PCIE_BUS_EN BIT(1) +#define EXYNOS_PCIE_CORE_RESET 0x01c +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) +#define EXYNOS_PCIE_STICKY_RESET 0x020 +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 struct exynos_pcie { struct dw_pcie pci; @@ -71,49 +71,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exyn= os_pcie *ep, bool on) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); } =20 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool o= n) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); if (on) - val |=3D PCIE_ELBI_SLV_DBI_ENABLE; + val |=3D EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &=3D ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + val &=3D ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); } =20 static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val &=3D ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val &=3D ~EXYNOS_PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } =20 static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val |=3D PCIE_CORE_RESET_ENABLE; + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val |=3D EXYNOS_PCIE_CORE_RESET_ENABLE; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } =20 static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -121,21 +121,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep =3D to_exynos_pcie(pci); u32 val; =20 - val =3D exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &=3D ~PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val &=3D ~EXYNOS_PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); =20 /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } =20 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); } =20 static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -148,12 +148,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, v= oid *arg) =20 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - u32 val =3D IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + u32 val =3D EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; =20 - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } =20 static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -210,9 +210,9 @@ static struct pci_ops exynos_pci_ops =3D { static bool exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep =3D to_exynos_pcie(pci); - u32 val =3D exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + u32 val =3D exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP= ); =20 - return val & PCIE_ELBI_XMLH_LINKUP; + return val & EXYNOS_PCIE_ELBI_XMLH_LINKUP; } =20 static int exynos_pcie_host_init(struct dw_pcie_rp *pp) --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A3C229BD8D for ; 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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154707epcas5p20e96a10de3fffcaaf95861358811446c References: <20250811154638.95732-1-shradha.t@samsung.com> Exynos PCI file follows MACRO definition order where register offset is defined in ascending order and each bit field within the offset is defined right after offset definition. Some MACROs are out of order and so reorder those MACROs to maintain consistency. Suggested-by: Hrishikesh Dileep Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 30d12ff9b0c6..b4ec167b0583 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -27,11 +27,11 @@ =20 /* PCIe ELBI registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_IRQ_INTA_ASSERT BIT(0) #define EXYNOS_IRQ_INTB_ASSERT BIT(2) #define EXYNOS_IRQ_INTC_ASSERT BIT(4) #define EXYNOS_IRQ_INTD_ASSERT BIT(6) -#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c #define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 #define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 #define EXYNOS_PCIE_SW_WAKE 0x018 @@ -42,9 +42,9 @@ #define EXYNOS_PCIE_NONSTICKY_RESET 0x024 #define EXYNOS_PCIE_APP_INIT_RESET 0x028 #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 #define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 #define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 310F42E4241 for ; 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Tue, 12 Aug 2025 05:02:12 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.95]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c1K9v5rK9z3hhTC; Tue, 12 Aug 2025 05:02:11 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250811154711epcas5p1847566b0216447ad0976472dddf096dd~awQTokfzx2229822298epcas5p1J; Mon, 11 Aug 2025 15:47:11 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154708epsmtip1f8ce936834e2899393b7b76e1e7f6c93~awQRA13uZ2560925609epsmtip1L; Mon, 11 Aug 2025 15:47:08 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 04/12] PCI: exynos: Add platform device private data Date: Mon, 11 Aug 2025 21:16:30 +0530 Message-ID: <20250811154638.95732-5-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154711epcas5p1847566b0216447ad0976472dddf096dd X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154711epcas5p1847566b0216447ad0976472dddf096dd References: <20250811154638.95732-1-shradha.t@samsung.com> In order to extend this driver to all Samsung manufactured SoCs having DWC PCIe controller, add private data structure which will hold platform device specific information. It holds function ops like DWC host ops, DWC generic ops, and PCI read/write ops which will be used as driver data for different compatibles. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 32 ++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index b4ec167b0583..c830b20d54f0 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -49,9 +49,16 @@ #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 +struct samsung_pcie_pdata { + struct pci_ops *pci_ops; + const struct dw_pcie_ops *dwc_ops; + const struct dw_pcie_host_ops *host_ops; +}; + struct exynos_pcie { struct dw_pcie pci; void __iomem *elbi_base; + const struct samsung_pcie_pdata *pdata; struct clk_bulk_data *clks; struct phy *phy; struct regulator_bulk_data supplies[2]; @@ -220,7 +227,7 @@ static int exynos_pcie_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct exynos_pcie *ep =3D to_exynos_pcie(pci); =20 - pp->bridge->ops =3D &exynos_pci_ops; + pp->bridge->ops =3D ep->pdata->pci_ops; =20 exynos_pcie_assert_core_reset(ep); =20 @@ -268,7 +275,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, return 0; } =20 -static const struct dw_pcie_ops dw_pcie_ops =3D { +static const struct dw_pcie_ops exynos_dw_pcie_ops =3D { .read_dbi =3D exynos_pcie_read_dbi, .write_dbi =3D exynos_pcie_write_dbi, .link_up =3D exynos_pcie_link_up, @@ -279,6 +286,7 @@ static int exynos_pcie_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct exynos_pcie *ep; + const struct samsung_pcie_pdata *pdata; struct device_node *np =3D dev->of_node; int ret; =20 @@ -286,8 +294,11 @@ static int exynos_pcie_probe(struct platform_device *p= dev) if (!ep) return -ENOMEM; =20 + pdata =3D of_device_get_match_data(dev); + + ep->pdata =3D pdata; ep->pci.dev =3D dev; - ep->pci.ops =3D &dw_pcie_ops; + ep->pci.ops =3D pdata->dwc_ops; =20 ep->phy =3D devm_of_phy_get(dev, np, NULL); if (IS_ERR(ep->phy)) @@ -363,9 +374,9 @@ static int exynos_pcie_resume_noirq(struct device *dev) return ret; =20 /* exynos_pcie_host_init controls ep->phy */ - exynos_pcie_host_init(pp); + ep->pdata->host_ops->init(pp); dw_pcie_setup_rc(pp); - exynos_pcie_start_link(pci); + ep->pdata->dwc_ops->start_link(pci); return dw_pcie_wait_for_link(pci); } =20 @@ -374,8 +385,17 @@ static const struct dev_pm_ops exynos_pcie_pm_ops =3D { exynos_pcie_resume_noirq) }; =20 +static const struct samsung_pcie_pdata exynos_5433_pcie_rc_pdata =3D { + .dwc_ops =3D &exynos_dw_pcie_ops, + .pci_ops =3D &exynos_pci_ops, + .host_ops =3D &exynos_pcie_host_ops, +}; + static const struct of_device_id exynos_pcie_of_match[] =3D { - { .compatible =3D "samsung,exynos5433-pcie", }, + { + .compatible =3D "samsung,exynos5433-pcie", + .data =3D (void *) &exynos_5433_pcie_rc_pdata, + }, { }, }; =20 --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D53B42E4277 for ; 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Tue, 12 Aug 2025 05:02:16 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.87]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c1K9z19SBz3hhTD; Tue, 12 Aug 2025 05:02:15 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250811154716epcas5p44980091d5273073b9bf2031572c38376~awQXzzDDb1821518215epcas5p45; Mon, 11 Aug 2025 15:47:16 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154713epsmtip1541fb87e24feb81701b892c5299371e0~awQVL4KJ72560925609epsmtip1M; Mon, 11 Aug 2025 15:47:13 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 05/12] PCI: exynos: Add resource ops, soc variant and device mode Date: Mon, 11 Aug 2025 21:16:31 +0530 Message-ID: <20250811154638.95732-6-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154716epcas5p44980091d5273073b9bf2031572c38376 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154716epcas5p44980091d5273073b9bf2031572c38376 References: <20250811154638.95732-1-shradha.t@samsung.com> Some resources might differ based on platforms and we need platform specific functions to initialize or alter them. For better code re-usability, making a separate res_ops which will hold all such function pointers or other resource specific data. Include ops like - init_regulator (initialize the regulator data) - pcie_irq_handler (interrupt handler for PCIe) - set_device_mode (set device mode to EP or RC) Some operations maybe specific to certain SoCs and not applicable to others. For such use cases, adding an SoC variant data field which can be used to distinguish between the variants. Some SoCs may have dual-role PCIe controller which can work as RC or EP. Add device_mode to store the role and take decisions accordingly. Make enable/disable of regulator and initialization of IRQ as common functions to be used by all Samsung SoCs. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 143 +++++++++++++++++++----- 1 file changed, 116 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index c830b20d54f0..ef1f42236575 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -49,10 +49,18 @@ #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 +/* to store different SoC variants of Samsung */ +enum samsung_pcie_variants { + EXYNOS_5433, +}; + struct samsung_pcie_pdata { struct pci_ops *pci_ops; const struct dw_pcie_ops *dwc_ops; const struct dw_pcie_host_ops *host_ops; + const struct samsung_res_ops *res_ops; + unsigned int soc_variant; + enum dw_pcie_device_mode device_mode; }; =20 struct exynos_pcie { @@ -61,7 +69,14 @@ struct exynos_pcie { const struct samsung_pcie_pdata *pdata; struct clk_bulk_data *clks; struct phy *phy; - struct regulator_bulk_data supplies[2]; + struct regulator_bulk_data *supplies; + int supplies_cnt; +}; + +struct samsung_res_ops { + int (*init_regulator)(struct exynos_pcie *ep); + irqreturn_t (*pcie_irq_handler)(int irq, void *arg); + void (*set_device_mode)(struct exynos_pcie *ep); }; =20 static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -74,6 +89,31 @@ static u32 exynos_pcie_readl(void __iomem *base, u32 reg) return readl(base + reg); } =20 +static int samsung_regulator_enable(struct exynos_pcie *ep) +{ + int ret; + + if (ep->supplies_cnt =3D=3D 0) + return 0; + + ret =3D regulator_bulk_enable(ep->supplies_cnt, ep->supplies); + + return ret; +} + +static void samsung_regulator_disable(struct exynos_pcie *ep) +{ + struct device *dev =3D ep->pci.dev; + int ret; + + if (ep->supplies_cnt =3D=3D 0) + return; + + ret =3D regulator_bulk_disable(ep->supplies_cnt, ep->supplies); + if (ret) + dev_warn(dev, "failed to disable regulators: %d\n", ret); +} + static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool o= n) { u32 val; @@ -244,7 +284,26 @@ static const struct dw_pcie_host_ops exynos_pcie_host_= ops =3D { .init =3D exynos_pcie_host_init, }; =20 -static int exynos_add_pcie_port(struct exynos_pcie *ep, +static int exynos_init_regulator(struct exynos_pcie *ep) +{ + struct device *dev =3D ep->pci.dev; + int ret =3D 0; + + ep->supplies_cnt =3D 2; + + ep->supplies =3D devm_kcalloc(dev, ep->supplies_cnt, sizeof(*ep->supplies= ), GFP_KERNEL); + if (!ep->supplies) + return -ENOMEM; + + ep->supplies[0].supply =3D "vdd18"; + ep->supplies[1].supply =3D "vdd10"; + + ret =3D devm_regulator_bulk_get(dev, ep->supplies_cnt, ep->supplies); + + return ret; +} + +static int samsung_irq_init(struct exynos_pcie *ep, struct platform_device *pdev) { struct dw_pcie *pci =3D &ep->pci; @@ -256,22 +315,15 @@ static int exynos_add_pcie_port(struct exynos_pcie *e= p, if (pp->irq < 0) return pp->irq; =20 - ret =3D devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, + ret =3D devm_request_irq(dev, pp->irq, ep->pdata->res_ops->pcie_irq_handl= er, IRQF_SHARED, "exynos-pcie", ep); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; } =20 - pp->ops =3D &exynos_pcie_host_ops; pp->msi_irq[0] =3D -ENODEV; =20 - ret =3D dw_pcie_host_init(pp); - if (ret) { - dev_err(dev, "failed to initialize host\n"); - return ret; - } - return 0; } =20 @@ -282,6 +334,11 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops =3D= { .start_link =3D exynos_pcie_start_link, }; =20 +static const struct samsung_res_ops exynos_res_ops_data =3D { + .init_regulator =3D exynos_init_regulator, + .pcie_irq_handler =3D exynos_pcie_irq_handler, +}; + static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -313,28 +370,46 @@ static int exynos_pcie_probe(struct platform_device *= pdev) if (ret < 0) return ret; =20 - ep->supplies[0].supply =3D "vdd18"; - ep->supplies[1].supply =3D "vdd10"; - ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), - ep->supplies); - if (ret) - return ret; + if (pdata->res_ops && pdata->res_ops->init_regulator) { + ret =3D ep->pdata->res_ops->init_regulator(ep); + if (ret) + return ret; + } =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + ret =3D samsung_regulator_enable(ep); if (ret) return ret; =20 platform_set_drvdata(pdev, ep); =20 - ret =3D exynos_add_pcie_port(ep, pdev); - if (ret < 0) - goto fail_probe; + if (pdata->res_ops && pdata->res_ops->set_device_mode) + pdata->res_ops->set_device_mode(ep); + + switch (ep->pdata->device_mode) { + case DW_PCIE_RC_TYPE: + ret =3D samsung_irq_init(ep, pdev); + if (ret) + goto fail_regulator; + + ep->pci.pp.ops =3D pdata->host_ops; + + ret =3D dw_pcie_host_init(&ep->pci.pp); + if (ret < 0) + goto fail_phy_init; + + break; + default: + dev_err(dev, "invalid device type\n"); + ret =3D -EINVAL; + goto fail_regulator; + } =20 return 0; =20 -fail_probe: +fail_phy_init: phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); +fail_regulator: + samsung_regulator_disable(ep); =20 return ret; } @@ -343,21 +418,29 @@ static void exynos_pcie_remove(struct platform_device= *pdev) { struct exynos_pcie *ep =3D platform_get_drvdata(pdev); =20 + if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) + return; dw_pcie_host_deinit(&ep->pci.pp); - exynos_pcie_assert_core_reset(ep); + if (ep->pdata->soc_variant =3D=3D EXYNOS_5433) + exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + samsung_regulator_disable(ep); } =20 static int exynos_pcie_suspend_noirq(struct device *dev) { struct exynos_pcie *ep =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &ep->pci; =20 - exynos_pcie_assert_core_reset(ep); + if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) + return 0; + + if (ep->pdata->soc_variant =3D=3D EXYNOS_5433) + exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + samsung_regulator_disable(ep); =20 return 0; } @@ -369,7 +452,10 @@ static int exynos_pcie_resume_noirq(struct device *dev) struct dw_pcie_rp *pp =3D &pci->pp; int ret; =20 - ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); 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Tue, 12 Aug 2025 05:02:20 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.92]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c1KB32bsCz6B9mB; Tue, 12 Aug 2025 05:02:19 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250811154721epcas5p26c9e2880ca55a470f595d914b4030745~awQca5BY13269132691epcas5p2H; Mon, 11 Aug 2025 15:47:21 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154718epsmtip1dc1faa6a78e80137e6ed5ed1b4e63636~awQZyl8dc2596225962epsmtip1B; Mon, 11 Aug 2025 15:47:18 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 06/12] dt-bindings: PCI: Split exynos host into two files Date: Mon, 11 Aug 2025 21:16:32 +0530 Message-ID: <20250811154638.95732-7-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154721epcas5p26c9e2880ca55a470f595d914b4030745 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154721epcas5p26c9e2880ca55a470f595d914b4030745 References: <20250811154638.95732-1-shradha.t@samsung.com> The current Exynos PCIe yaml binding file is hard to reuse by other Samsung SoCs. Refactoring it by: - Moving common Samsung PCIe properties into samsung,exynos-pcie.yaml - Creating a dedicated samsung,exynos5433-pcie.yaml file for properties and constraints specific to the Exynos5433 SoC Signed-off-by: Shradha Todi --- .../bindings/pci/samsung,exynos-pcie.yaml | 70 +-------------- .../bindings/pci/samsung,exynos5433-pcie.yaml | 89 +++++++++++++++++++ 2 files changed, 91 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos543= 3-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml= b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index f20ed7e709f7..fd0b97b30821 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -11,7 +11,7 @@ maintainers: - Jaehoon Chung =20 description: |+ - Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + Samsung SoCs PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. =20 @@ -19,9 +19,6 @@ allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# =20 properties: - compatible: - const: samsung,exynos5433-pcie - reg: items: - description: Data Bus Interface (DBI) registers. @@ -37,83 +34,20 @@ properties: interrupts: maxItems: 1 =20 - clocks: - items: - - description: PCIe bridge clock - - description: PCIe bus clock - - clock-names: - items: - - const: pcie - - const: pcie_bus - phys: maxItems: 1 =20 - vdd10-supply: - description: - Phandle to a regulator that provides 1.0V power to the PCIe block. - - vdd18-supply: - description: - Phandle to a regulator that provides 1.8V power to the PCIe block. - - num-lanes: - const: 1 - - num-viewport: - const: 3 - required: - reg - reg-names - interrupts - "#address-cells" - "#size-cells" - - "#interrupt-cells" - - interrupt-map - - interrupt-map-mask - ranges - - bus-range - device_type - num-lanes - - num-viewport - clocks - clock-names - phys - - vdd10-supply - - vdd18-supply - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include =20 - pcie: pcie@15700000 { - compatible =3D "samsung,exynos5433-pcie"; - reg =3D <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x10= 00>; - reg-names =3D "dbi", "elbi", "config"; - #address-cells =3D <3>; - #size-cells =3D <2>; - #interrupt-cells =3D <1>; - device_type =3D "pci"; - interrupts =3D ; - clocks =3D <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; - clock-names =3D "pcie", "pcie_bus"; - phys =3D <&pcie_phy>; - pinctrl-0 =3D <&pcie_bus &pcie_wlanen>; - pinctrl-names =3D "default"; - num-lanes =3D <1>; - num-viewport =3D <3>; - bus-range =3D <0x00 0xff>; - ranges =3D <0x81000000 0 0 0x0c001000 0 0x00010000>, - <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; - vdd10-supply =3D <&ldo6_reg>; - vdd18-supply =3D <&ldo7_reg>; - interrupt-map-mask =3D <0 0 0 0>; - interrupt-map =3D <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; - }; -... +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.= yaml b/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml new file mode 100644 index 000000000000..1fb2c32899c4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5433-pcie.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos5433-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos5433 SoC PCIe Host Controller + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +description: + Exynos5433 SoCs PCIe host controller inherits all the + common properties defined in samsung,exynos-pcie.yaml + +allOf: + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + num-lanes: + const: 1 + + num-viewport: + const: 3 + + vdd10-supply: + description: + phandle to a regulator that provides 1.0v power to the pcie block + + vdd18-supply: + description: + phandle to a regulator that provides 1.8v power to the pcie block + +required: + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - bus-range + - num-viewport + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible =3D "samsung,exynos5433-pcie"; + reg =3D <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x10= 00>; + reg-names =3D "dbi", "elbi", "config"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + interrupts =3D ; + clocks =3D <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names =3D "pcie", "pcie_bus"; + phys =3D <&pcie_phy>; + pinctrl-0 =3D <&pcie_bus &pcie_wlanen>; + pinctrl-names =3D "default"; + num-lanes =3D <1>; + num-viewport =3D <3>; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply =3D <&ldo6_reg>; + vdd18-supply =3D <&ldo7_reg>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; +... --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90A262DFA2A for ; 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Tue, 12 Aug 2025 05:02:24 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.95]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c1KB72z6Rz2SSKp; Tue, 12 Aug 2025 05:02:23 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097~awQg8dEdu2612226122epcas5p4y; Mon, 11 Aug 2025 15:47:25 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154723epsmtip1209187009cea317303c81d1a099486b6~awQeURXHq2560925609epsmtip1Q; Mon, 11 Aug 2025 15:47:22 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 07/12] dt-bindings: PCI: Add support for Tesla FSD SoC Date: Mon, 11 Aug 2025 21:16:33 +0530 Message-ID: <20250811154638.95732-8-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097 References: <20250811154638.95732-1-shradha.t@samsung.com> Add Tesla FSD SoC support for both RC and EP. Signed-off-by: Shradha Todi --- .../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++ .../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep= .yaml create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.ya= ml diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml b= /Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml new file mode 100644 index 000000000000..8dfe0720e6ab --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC series PCIe Endpoint Controller + +maintainers: + - Shradha Todi + +description: + Tesla FSD SoCs PCIe endpoint controller is based on the Synopsys DesignW= are + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: tesla,fsd-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: elbi + - const: dbi + - const: dbi2 + - const: addr_space + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: dbi + - const: mstr + - const: slv + + num-lanes: + maximum: 4 + + phys: + maxItems: 1 + + samsung,syscon-pcie: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandle for system control registers, used to + control signals at system level + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - samsung,syscon-pcie + +unevaluatedProperties: false + +examples: + - | + #include + #include + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcieep0: pcie-ep@16a00000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x16a01000 0x0 0x80>, + <0x0 0x17000000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml new file mode 100644 index 000000000000..533870ab1d73 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC series PCIe Host Controller + +maintainers: + - Shradha Todi + +description: + Tesla FSD SoCs PCIe host controller inherits all the common + properties defined in samsung,exynos-pcie.yaml + +allOf: + - $ref: /schemas/pci/samsung,exynos-pcie.yaml# + +properties: + compatible: + const: tesla,fsd-pcie + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: dbi + - const: mstr + - const: slv + + num-lanes: + maximum: 4 + + samsung,syscon-pcie: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandle for system control registers, used to + control signals at system level + +required: + - samsung,syscon-pcie + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcierc1: pcie@16b00000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xff= efff>; + clocks =3D <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x510>; + }; + }; +... --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4C102E5B05 for ; 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Tue, 12 Aug 2025 05:02:27 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.92]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c1KBB2ZBpz2SSKY; Tue, 12 Aug 2025 05:02:26 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401~awQktGyX_2612226122epcas5p44; Mon, 11 Aug 2025 15:47:29 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154727epsmtip10f1370b9b4a42104a2120af22d683fe8~awQiFM6iH2596225962epsmtip1G; Mon, 11 Aug 2025 15:47:27 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 08/12] dt-bindings: phy: Add PCIe PHY support for FSD SoC Date: Mon, 11 Aug 2025 21:16:34 +0530 Message-ID: <20250811154638.95732-9-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401 References: <20250811154638.95732-1-shradha.t@samsung.com> Since Tesla FSD SoC uses Samsung PCIe PHY, add support in exynos PCIe PHY bindings. In Tesla FSD SoC, the two PHY instances, although having identical hardware design and register maps, are placed in different locations (Placement and routing) inside the SoC and have distinct PHY-to-Controller topologies. (One instance is connected to two PCIe controllers, while the other is connected to only one). As a result, they experience different analog environments, including varying channel losses and noise profiles. Since these PHYs lack internal adaptation mechanisms and f/w based tuning, manual register programming is required for analog tuning. To ensure optimal signal integrity, it is essential to use different register values for each PHY instance, despite their identical hardware design. This is because the same register values may not be suitable for both instances due to their differing environments and topologies. Due to this, we are using two PHY compatibles for different PHY instances. Signed-off-by: Shradha Todi Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/samsung,exynos-pcie-phy.yaml | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml index 41df8bb08ff7..6295472696db 100644 --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -15,10 +15,14 @@ properties: const: 0 =20 compatible: - const: samsung,exynos5433-pcie-phy + enum: + - samsung,exynos5433-pcie-phy + - tesla,fsd-pcie-phy0 + - tesla,fsd-pcie-phy1 =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 samsung,pmu-syscon: $ref: /schemas/types.yaml#/definitions/phandle @@ -30,6 +34,25 @@ properties: description: phandle for FSYS sysreg interface, used to control sysreg registers bits for PCIe PHY =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-pcie-phy0 + - tesla,fsd-pcie-phy1 + then: + properties: + reg: + items: + - description: PHY + - description: PCS + else: + properties: + reg: + maxItems: 1 + required: - "#phy-cells" - compatible --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B2E22E6104 for ; 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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154734epcas5p1ed075fa71285a5c34c2d319bb01c98ac References: <20250811154638.95732-1-shradha.t@samsung.com> Currently, the exynos PCIe PHY driver supports only single phy ops making it unusable for other platforms. Add the phy_ops as platform specific device data so as to extend this driver to support all platforms using Samsung PHY. Signed-off-by: Shradha Todi --- drivers/phy/samsung/phy-exynos-pcie.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/ph= y-exynos-pcie.c index 53c9230c2907..022222a0212a 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -136,6 +136,7 @@ static const struct phy_ops exynos5433_phy_ops =3D { static const struct of_device_id exynos_pcie_phy_match[] =3D { { .compatible =3D "samsung,exynos5433-pcie-phy", + .data =3D &exynos5433_phy_ops, }, {}, }; @@ -146,6 +147,11 @@ static int exynos_pcie_phy_probe(struct platform_devic= e *pdev) struct exynos_pcie_phy *exynos_phy; struct phy *generic_phy; struct phy_provider *phy_provider; + const struct phy_ops *drv_data; + + drv_data =3D of_device_get_match_data(dev); + if (!drv_data) + return -ENODEV; =20 exynos_phy =3D devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL); if (!exynos_phy) @@ -169,7 +175,7 @@ static int exynos_pcie_phy_probe(struct platform_device= *pdev) return PTR_ERR(exynos_phy->fsysreg); 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Mon, 11 Aug 2025 15:47:38 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154735epsmtip17c2186ff99f7d4ce9e9fd71d457a69e3~awQpjLYCi2560925609epsmtip1Y; Mon, 11 Aug 2025 15:47:35 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 10/12] phy: exynos: Add PCIe PHY support for FSD SoC Date: Mon, 11 Aug 2025 21:16:36 +0530 Message-ID: <20250811154638.95732-11-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154738epcas5p1d1202f799c4d950c5d5e7f45e39a51e7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154738epcas5p1d1202f799c4d950c5d5e7f45e39a51e7 References: <20250811154638.95732-1-shradha.t@samsung.com> Add PCIe PHY support for Tesla FSD SoC. Signed-off-by: Shradha Todi --- drivers/phy/samsung/phy-exynos-pcie.c | 287 ++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/ph= y-exynos-pcie.c index 022222a0212a..5a55a22f9661 100644 --- a/drivers/phy/samsung/phy-exynos-pcie.c +++ b/drivers/phy/samsung/phy-exynos-pcie.c @@ -34,9 +34,105 @@ /* PMU PCIE PHY isolation control */ #define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730 =20 +/* FSD: PCIe PHY common registers */ +#define FSD_PCIE_PHY_TRSV_CMN_REG03 0x000c +#define FSD_PCIE_PHY_TRSV_CMN_REG01E 0x0078 +#define FSD_PCIE_PHY_TRSV_CMN_REG02D 0x00b4 +#define FSD_PCIE_PHY_TRSV_CMN_REG031 0x00c4 +#define FSD_PCIE_PHY_TRSV_CMN_REG036 0x00d8 +#define FSD_PCIE_PHY_TRSV_CMN_REG05F 0x017c +#define FSD_PCIE_PHY_TRSV_CMN_REG060 0x0180 +#define FSD_PCIE_PHY_TRSV_CMN_REG062 0x0188 +#define FSD_PCIE_PHY_TRSV_CMN_REG061 0x0184 +#define FSD_PCIE_PHY_AGG_BIF_RESET 0x0200 +#define FSD_PCIE_PHY_AGG_BIF_CLOCK 0x0208 +#define FSD_PCIE_PHY_CMN_RESET 0x0228 + +/* FSD: PCIe PHY lane registers */ +#define FSD_PCIE_LANE_OFFSET 0x0400 +#define FSD_PCIE_NUM_LANES 0x4 + +#define FSD_PCIE_PHY_TRSV_REG001_LN_N 0x0404 +#define FSD_PCIE_PHY_TRSV_REG002_LN_N 0x0408 +#define FSD_PCIE_PHY_TRSV_REG005_LN_N 0x0414 +#define FSD_PCIE_PHY_TRSV_REG006_LN_N 0x0418 +#define FSD_PCIE_PHY_TRSV_REG007_LN_N 0x041c +#define FSD_PCIE_PHY_TRSV_REG009_LN_N 0x0424 +#define FSD_PCIE_PHY_TRSV_REG00A_LN_N 0x0428 +#define FSD_PCIE_PHY_TRSV_REG00C_LN_N 0x0430 +#define FSD_PCIE_PHY_TRSV_REG012_LN_N 0x0448 +#define FSD_PCIE_PHY_TRSV_REG013_LN_N 0x044c +#define FSD_PCIE_PHY_TRSV_REG014_LN_N 0x0450 +#define FSD_PCIE_PHY_TRSV_REG015_LN_N 0x0454 +#define FSD_PCIE_PHY_TRSV_REG016_LN_N 0x0458 +#define FSD_PCIE_PHY_TRSV_REG018_LN_N 0x0460 +#define FSD_PCIE_PHY_TRSV_REG020_LN_N 0x0480 +#define FSD_PCIE_PHY_TRSV_REG026_LN_N 0x0498 +#define FSD_PCIE_PHY_TRSV_REG029_LN_N 0x04a4 +#define FSD_PCIE_PHY_TRSV_REG031_LN_N 0x04c4 +#define FSD_PCIE_PHY_TRSV_REG036_LN_N 0x04d8 +#define FSD_PCIE_PHY_TRSV_REG039_LN_N 0x04e4 +#define FSD_PCIE_PHY_TRSV_REG03B_LN_N 0x04ec +#define FSD_PCIE_PHY_TRSV_REG03C_LN_N 0x04f0 +#define FSD_PCIE_PHY_TRSV_REG03E_LN_N 0x04f8 +#define FSD_PCIE_PHY_TRSV_REG03F_LN_N 0x04fc +#define FSD_PCIE_PHY_TRSV_REG043_LN_N 0x050c +#define FSD_PCIE_PHY_TRSV_REG044_LN_N 0x0510 +#define FSD_PCIE_PHY_TRSV_REG046_LN_N 0x0518 +#define FSD_PCIE_PHY_TRSV_REG048_LN_N 0x0520 +#define FSD_PCIE_PHY_TRSV_REG049_LN_N 0x0524 +#define FSD_PCIE_PHY_TRSV_REG04E_LN_N 0x0538 +#define FSD_PCIE_PHY_TRSV_REG052_LN_N 0x0548 +#define FSD_PCIE_PHY_TRSV_REG068_LN_N 0x05a0 +#define FSD_PCIE_PHY_TRSV_REG069_LN_N 0x05a4 +#define FSD_PCIE_PHY_TRSV_REG06A_LN_N 0x05a8 +#define FSD_PCIE_PHY_TRSV_REG06B_LN_N 0x05ac +#define FSD_PCIE_PHY_TRSV_REG07B_LN_N 0x05ec +#define FSD_PCIE_PHY_TRSV_REG083_LN_N 0x060c +#define FSD_PCIE_PHY_TRSV_REG084_LN_N 0x0610 +#define FSD_PCIE_PHY_TRSV_REG086_LN_N 0x0618 +#define FSD_PCIE_PHY_TRSV_REG087_LN_N 0x061c +#define FSD_PCIE_PHY_TRSV_REG08B_LN_N 0x062c +#define FSD_PCIE_PHY_TRSV_REG09C_LN_N 0x0670 +#define FSD_PCIE_PHY_TRSV_REG09D_LN_N 0x0674 +#define FSD_PCIE_PHY_TRSV_REG09E_LN_N 0x0678 +#define FSD_PCIE_PHY_TRSV_REG09F_LN_N 0x067c +#define FSD_PCIE_PHY_TRSV_REG0A2_LN_N 0x0688 +#define FSD_PCIE_PHY_TRSV_REG0A4_LN_N 0x0690 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_N 0x0738 +#define FSD_PCIE_PHY_TRSV_REG0FC_LN_N 0x07f0 +#define FSD_PCIE_PHY_TRSV_REG0FD_LN_N 0x07f4 +#define FSD_PCIE_PHY_TRSV_REG0FE_LN_N 0x07f8 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_1 0x0b38 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_2 0x0f38 +#define FSD_PCIE_PHY_TRSV_REG0CE_LN_3 0x1338 + +/* FSD: PCIe PCS registers */ +#define FSD_PCIE_PCS_BRF_0 0x0004 +#define FSD_PCIE_PCS_BRF_1 0x0804 +#define FSD_PCIE_PCS_CLK 0x0180 + +/* FSD: PCIe SYSREG registers */ +#define FSD_PCIE_SYSREG_PHY_0_CON 0x042c +#define FSD_PCIE_SYSREG_PHY_0_CON_MASK 0x03ff +#define FSD_PCIE_SYSREG_PHY_0_REF_SEL (0x2 << 0) +#define FSD_PCIE_SYSREG_PHY_0_REF_SEL_MASK 0x3 +#define FSD_PCIE_SYSREG_PHY_0_AUX_EN BIT(4) +#define FSD_PCIE_SYSREG_PHY_0_CMN_RSTN BIT(8) +#define FSD_PCIE_SYSREG_PHY_0_INIT_RSTN BIT(9) + +#define FSD_PCIE_SYSREG_PHY_1_CON 0x0500 +#define FSD_PCIE_SYSREG_PHY_1_CON_MASK 0x01ff +#define FSD_PCIE_SYSREG_PHY_1_REF_SEL (0x2 << 4) +#define FSD_PCIE_SYSREG_PHY_1_REF_SEL_MASK 0x30 +#define FSD_PCIE_SYSREG_PHY_1_AUX_EN BIT(0) +#define FSD_PCIE_SYSREG_PHY_1_CMN_RSTN BIT(1) +#define FSD_PCIE_SYSREG_PHY_1_INIT_RSTN BIT(3) + /* For Exynos pcie phy */ struct exynos_pcie_phy { void __iomem *base; + void __iomem *pcs_base; struct regmap *pmureg; struct regmap *fsysreg; }; @@ -133,11 +229,200 @@ static const struct phy_ops exynos5433_phy_ops =3D { .owner =3D THIS_MODULE, }; =20 +static void fsd_pcie_phy_writel(struct exynos_pcie_phy *phy_ctrl, u32 offs= et, u32 val) +{ + void __iomem *phy_base =3D phy_ctrl->base; + u32 i; + + for (i =3D 0; i < FSD_PCIE_NUM_LANES; i++) + writel(val, phy_base + (offset + i * FSD_PCIE_LANE_OFFSET)); +} + +static int fsd_pcie_phy0_reset(struct phy *phy) +{ + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + + writel(0x1, phy_ctrl->pcs_base + FSD_PCIE_PCS_CLK); + + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_0_CON, + FSD_PCIE_SYSREG_PHY_0_CON_MASK, 0x0); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_0_CON, + FSD_PCIE_SYSREG_PHY_0_AUX_EN, FSD_PCIE_SYSREG_PHY_0_AUX_EN); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_0_CON, + FSD_PCIE_SYSREG_PHY_0_REF_SEL_MASK, FSD_PCIE_SYSREG_PHY_0_REF_SEL); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_0_CON, + FSD_PCIE_SYSREG_PHY_0_INIT_RSTN, FSD_PCIE_SYSREG_PHY_0_INIT_RSTN); + + return 0; +} + +static int fsd_pcie_phy1_reset(struct phy *phy) +{ + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + + writel(0x1, phy_ctrl->pcs_base + FSD_PCIE_PCS_CLK); + + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_1_CON, + FSD_PCIE_SYSREG_PHY_1_CON_MASK, 0x0); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_1_CON, + FSD_PCIE_SYSREG_PHY_1_AUX_EN, FSD_PCIE_SYSREG_PHY_1_AUX_EN); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_1_CON, + FSD_PCIE_SYSREG_PHY_1_REF_SEL_MASK, FSD_PCIE_SYSREG_PHY_1_REF_SEL); + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_1_CON, + FSD_PCIE_SYSREG_PHY_1_INIT_RSTN, FSD_PCIE_SYSREG_PHY_1_INIT_RSTN); + + return 0; +} + +static int fsd_pcie_phy0_init(struct phy *phy) +{ + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + void __iomem *pbase =3D phy_ctrl->base; + + fsd_pcie_phy0_reset(phy); + + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_0); + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_1); + writel(0x00, pbase + FSD_PCIE_PHY_AGG_BIF_RESET); + writel(0x00, pbase + FSD_PCIE_PHY_AGG_BIF_CLOCK); + + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG07B_LN_N, 0x20); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG052_LN_N, 0x00); + writel(0x11, pbase + FSD_PCIE_PHY_TRSV_CMN_REG05F); + writel(0x23, pbase + FSD_PCIE_PHY_TRSV_CMN_REG060); + writel(0x0, pbase + FSD_PCIE_PHY_TRSV_CMN_REG062); + writel(0x15, pbase + FSD_PCIE_PHY_TRSV_CMN_REG03); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0CE_LN_N, 0x8); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG039_LN_N, 0xf); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03B_LN_N, 0x13); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03C_LN_N, 0xf6); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG044_LN_N, 0x57); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03E_LN_N, 0x10); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03F_LN_N, 0x04); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG043_LN_N, 0x11); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG049_LN_N, 0x6f); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG04E_LN_N, 0x18); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG068_LN_N, 0x1f); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG069_LN_N, 0xc); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG06B_LN_N, 0x78); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG083_LN_N, 0xa); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG084_LN_N, 0x80); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG086_LN_N, 0xff); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG087_LN_N, 0x3c); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG09D_LN_N, 0x7c); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG09E_LN_N, 0x33); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG09F_LN_N, 0x33); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG001_LN_N, 0x3f); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG002_LN_N, 0x1c); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG005_LN_N, 0x2b); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG006_LN_N, 0x3); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG007_LN_N, 0x0c); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG009_LN_N, 0x10); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG00A_LN_N, 0x1); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG00C_LN_N, 0x93); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG012_LN_N, 0x1); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG013_LN_N, 0x0); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG014_LN_N, 0x70); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG015_LN_N, 0x0); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG016_LN_N, 0x70); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0FC_LN_N, 0x80); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0FD_LN_N, 0x0); + + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_0_CON, + FSD_PCIE_SYSREG_PHY_0_CMN_RSTN, FSD_PCIE_SYSREG_PHY_0_CMN_RSTN); + + return 0; +} + +static int fsd_pcie_phy1_init(struct phy *phy) +{ + struct exynos_pcie_phy *phy_ctrl =3D phy_get_drvdata(phy); + void __iomem *pbase =3D phy_ctrl->base; + + fsd_pcie_phy1_reset(phy); + + writel(0x2, pbase + FSD_PCIE_PHY_CMN_RESET); + + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_0); + writel(0x00, phy_ctrl->pcs_base + FSD_PCIE_PCS_BRF_1); + writel(0x00, pbase + FSD_PCIE_PHY_AGG_BIF_RESET); + writel(0x00, pbase + FSD_PCIE_PHY_AGG_BIF_CLOCK); + + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG07B_LN_N, 0x20); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG052_LN_N, 0x00); + writel(0xaa, pbase + FSD_PCIE_PHY_TRSV_CMN_REG01E); + writel(0x28, pbase + FSD_PCIE_PHY_TRSV_CMN_REG02D); + writel(0x28, pbase + FSD_PCIE_PHY_TRSV_CMN_REG031); + writel(0x21, pbase + FSD_PCIE_PHY_TRSV_CMN_REG036); + writel(0x12, pbase + FSD_PCIE_PHY_TRSV_CMN_REG05F); + writel(0x23, pbase + FSD_PCIE_PHY_TRSV_CMN_REG060); + writel(0x0, pbase + FSD_PCIE_PHY_TRSV_CMN_REG061); + writel(0x0, pbase + FSD_PCIE_PHY_TRSV_CMN_REG062); + writel(0x15, pbase + FSD_PCIE_PHY_TRSV_CMN_REG03); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG039_LN_N, 0xf); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03B_LN_N, 0x13); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03C_LN_N, 0x66); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG044_LN_N, 0x57); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03E_LN_N, 0x10); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG03F_LN_N, 0x44); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG043_LN_N, 0x11); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG046_LN_N, 0xef); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG048_LN_N, 0x06); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG049_LN_N, 0xaf); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG04E_LN_N, 0x28); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG068_LN_N, 0x1f); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG069_LN_N, 0xc); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG06A_LN_N, 0x8); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG06B_LN_N, 0x78); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG083_LN_N, 0xa); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG084_LN_N, 0x80); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG087_LN_N, 0x30); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG08B_LN_N, 0xa0); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG09C_LN_N, 0xf7); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG09E_LN_N, 0x33); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0A2_LN_N, 0xfa); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0A4_LN_N, 0xf2); + writel(0x8, pbase + FSD_PCIE_PHY_TRSV_REG0CE_LN_N); + writel(0x9, pbase + FSD_PCIE_PHY_TRSV_REG0CE_LN_1); + writel(0x9, pbase + FSD_PCIE_PHY_TRSV_REG0CE_LN_2); + writel(0x9, pbase + FSD_PCIE_PHY_TRSV_REG0CE_LN_3); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG0FE_LN_N, 0x33); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG001_LN_N, 0x3f); + fsd_pcie_phy_writel(phy_ctrl, FSD_PCIE_PHY_TRSV_REG005_LN_N, 0x2b); + + writel(0x3, pbase + FSD_PCIE_PHY_CMN_RESET); + + regmap_update_bits(phy_ctrl->fsysreg, FSD_PCIE_SYSREG_PHY_1_CON, + FSD_PCIE_SYSREG_PHY_1_CMN_RSTN, FSD_PCIE_SYSREG_PHY_1_CMN_RSTN); + + return 0; +} + +static const struct phy_ops fsd_phy0_ops =3D { + .init =3D fsd_pcie_phy0_init, + .reset =3D fsd_pcie_phy0_reset, + .owner =3D THIS_MODULE, +}; + +static const struct phy_ops fsd_phy1_ops =3D { + .init =3D fsd_pcie_phy1_init, + .reset =3D fsd_pcie_phy1_reset, + .owner =3D THIS_MODULE, +}; + static const struct of_device_id exynos_pcie_phy_match[] =3D { { .compatible =3D "samsung,exynos5433-pcie-phy", .data =3D &exynos5433_phy_ops, }, + { + .compatible =3D "tesla,fsd-pcie-phy0", + .data =3D &fsd_phy0_ops, + }, + { + .compatible =3D "tesla,fsd-pcie-phy1", + .data =3D &fsd_phy1_ops, + }, {}, }; =20 @@ -181,6 +466,8 @@ static int exynos_pcie_phy_probe(struct platform_device= *pdev) return PTR_ERR(generic_phy); } =20 + exynos_phy->pcs_base =3D devm_platform_ioremap_resource(pdev, 1); + phy_set_drvdata(generic_phy, exynos_phy); phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); =20 --=20 2.49.0 From nobody Sun Oct 5 00:17:44 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB88A2E62A5 for ; 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Tue, 12 Aug 2025 05:02:36 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.86]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4c1KBM39mLz6B9m6; Tue, 12 Aug 2025 05:02:35 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250811154742epcas5p3276c7c053bedc526d9ce370dda83e195~awQv9dmns2815828158epcas5p3S; Mon, 11 Aug 2025 15:47:42 +0000 (GMT) Received: from cheetah.samsungds.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250811154739epsmtip19674dea8703440bc1f7b4a0340d60e0c~awQtVjeu32101521015epsmtip1X; Mon, 11 Aug 2025 15:47:39 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 11/12] PCI: exynos: Add support for Tesla FSD SoC Date: Mon, 11 Aug 2025 21:16:37 +0530 Message-ID: <20250811154638.95732-12-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154742epcas5p3276c7c053bedc526d9ce370dda83e195 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154742epcas5p3276c7c053bedc526d9ce370dda83e195 References: <20250811154638.95732-1-shradha.t@samsung.com> Add host and endpoint controller driver support for FSD SoC. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-exynos.c | 278 ++++++++++++++++++++++++ 1 file changed, 278 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index ef1f42236575..9aabfecdc147 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include =20 @@ -49,15 +51,35 @@ #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) =20 +#define FSD_IRQ2_STS 0x008 +#define FSD_IRQ_MSI_ENABLE BIT(17) +#define FSD_IRQ2_EN 0x018 +#define FSD_PCIE_APP_LTSSM_ENABLE 0x054 +#define FSD_PCIE_LTSSM_ENABLE 0x1 +#define FSD_PCIE_DEVICE_TYPE 0x080 +#define FSD_DEVICE_TYPE_RC 0x4 +#define FSD_DEVICE_TYPE_EP 0x0 +#define FSD_PCIE_CXPL_DEBUG_00_31 0x2c8 + /* to store different SoC variants of Samsung */ enum samsung_pcie_variants { + FSD, EXYNOS_5433, }; =20 +/* Values to be written to SYSREG to view DBI space as CDM/DBI2/IATU/DMA */ +enum fsd_pcie_addr_type { + ADDR_TYPE_DBI =3D 0x0, + ADDR_TYPE_DBI2 =3D 0x12, + ADDR_TYPE_ATU =3D 0x36, + ADDR_TYPE_DMA =3D 0x3f, +}; + struct samsung_pcie_pdata { struct pci_ops *pci_ops; const struct dw_pcie_ops *dwc_ops; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; const struct samsung_res_ops *res_ops; unsigned int soc_variant; enum dw_pcie_device_mode device_mode; @@ -67,6 +89,8 @@ struct exynos_pcie { struct dw_pcie pci; void __iomem *elbi_base; const struct samsung_pcie_pdata *pdata; + struct regmap *sysreg; + unsigned int sysreg_offset; struct clk_bulk_data *clks; struct phy *phy; struct regulator_bulk_data *supplies; @@ -334,11 +358,201 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops = =3D { .start_link =3D exynos_pcie_start_link, }; =20 +static void fsd_pcie_stop_link(struct dw_pcie *pci) +{ + u32 val; + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + val =3D readl(ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); + val &=3D ~FSD_PCIE_LTSSM_ENABLE; + writel(val, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); +} + +static int fsd_pcie_start_link(struct dw_pcie *pci) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + struct dw_pcie_ep *dw_ep =3D &pci->ep; + + if (dw_pcie_link_up(pci)) + return 0; + + writel(FSD_PCIE_LTSSM_ENABLE, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE); + + /* no need to wait for link in case of host as core files take care */ + if (ep->pdata->device_mode =3D=3D DW_PCIE_RC_TYPE) + return 0; + + /* check if the link is up or not in case of EP */ + if (!dw_pcie_wait_for_link(pci)) { + dw_pcie_ep_linkup(dw_ep); + return 0; + } + + return -ETIMEDOUT; +} + +static irqreturn_t fsd_pcie_irq_handler(int irq, void *arg) +{ + u32 val; + struct exynos_pcie *ep =3D arg; + struct dw_pcie *pci =3D &ep->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + + val =3D readl(ep->elbi_base + FSD_IRQ2_STS); + if ((val & FSD_IRQ_MSI_ENABLE) =3D=3D FSD_IRQ_MSI_ENABLE) { + val &=3D FSD_IRQ_MSI_ENABLE; + writel(val, ep->elbi_base + FSD_IRQ2_STS); + dw_handle_msi_irq(pp); + } + + return IRQ_HANDLED; +} + +static void fsd_pcie_msi_init(struct exynos_pcie *ep) +{ + int val; + + val =3D readl(ep->elbi_base + FSD_IRQ2_EN); + val |=3D FSD_IRQ_MSI_ENABLE; + writel(val, ep->elbi_base + FSD_IRQ2_EN); +} + +static void __iomem *fsd_atu_setting(struct dw_pcie *pci, void __iomem *ba= se) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + if (base >=3D pci->atu_base) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_ATU); + return (base - DEFAULT_DBI_ATU_OFFSET); + } else if (base =3D=3D pci->dbi_base) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI); + } else if (base =3D=3D pci->dbi_base2) { + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI2); + } + + return base; +} + +static u32 fsd_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + void __iomem *addr; + u32 val; + + addr =3D fsd_atu_setting(pci, base); + dw_pcie_read(addr + reg, size, &val); + + return val; +} + +static void fsd_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + void __iomem *addr; + + addr =3D fsd_atu_setting(pci, base); + dw_pcie_write(addr + reg, size, val); +} + +static void fsd_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + fsd_atu_setting(pci, base); + dw_pcie_write(pci->dbi_base + reg, size, val); + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI); +} + +static bool fsd_pcie_link_up(struct dw_pcie *pci) +{ + u32 val; + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + val =3D readl(ep->elbi_base + FSD_PCIE_CXPL_DEBUG_00_31); + val &=3D PORT_LOGIC_LTSSM_STATE_MASK; + + return (val =3D=3D PORT_LOGIC_LTSSM_STATE_L0); +} + +static int fsd_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct exynos_pcie *ep =3D to_exynos_pcie(pci); + + phy_init(ep->phy); + fsd_pcie_msi_init(ep); + + return 0; +} + +static const struct dw_pcie_host_ops fsd_pcie_host_ops =3D { + .init =3D fsd_pcie_host_init, +}; + +static int fsd_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + return dw_pcie_ep_raise_intx_irq(ep, func_no); + case PCI_IRQ_MSIX: + dev_err(pci->dev, "EP does not support MSI-X\n"); + return -EINVAL; + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static const struct pci_epc_features fsd_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, +}; + +static const struct pci_epc_features *fsd_pcie_get_features(struct dw_pcie= _ep *ep) +{ + return &fsd_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops fsd_ep_ops =3D { + .raise_irq =3D fsd_pcie_raise_irq, + .get_features =3D fsd_pcie_get_features, +}; + +static void fsd_set_device_mode(struct exynos_pcie *ep) +{ + if (ep->pdata->device_mode =3D=3D DW_PCIE_RC_TYPE) + writel(FSD_DEVICE_TYPE_RC, ep->elbi_base + FSD_PCIE_DEVICE_TYPE); + else + writel(FSD_DEVICE_TYPE_EP, ep->elbi_base + FSD_PCIE_DEVICE_TYPE); +} + +static const struct dw_pcie_ops fsd_dw_pcie_ops =3D { + .read_dbi =3D fsd_pcie_read_dbi, + .write_dbi =3D fsd_pcie_write_dbi, + .write_dbi2 =3D fsd_pcie_write_dbi2, + .start_link =3D fsd_pcie_start_link, + .stop_link =3D fsd_pcie_stop_link, + .link_up =3D fsd_pcie_link_up, +}; + static const struct samsung_res_ops exynos_res_ops_data =3D { .init_regulator =3D exynos_init_regulator, .pcie_irq_handler =3D exynos_pcie_irq_handler, }; =20 +static const struct samsung_res_ops fsd_res_ops_data =3D { + .pcie_irq_handler =3D fsd_pcie_irq_handler, + .set_device_mode =3D fsd_set_device_mode, +}; + static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -361,6 +575,26 @@ static int exynos_pcie_probe(struct platform_device *p= dev) if (IS_ERR(ep->phy)) return PTR_ERR(ep->phy); =20 + if (ep->pdata->soc_variant =3D=3D FSD) { + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); + if (ret) + return ret; + + ep->sysreg =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,syscon-pcie"); + if (IS_ERR(ep->sysreg)) { + dev_err(dev, "sysreg regmap lookup failed.\n"); + return PTR_ERR(ep->sysreg); + } + + ret =3D of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", = 1, + &ep->sysreg_offset); + if (ret) { + dev_err(dev, "couldn't get the register offset for syscon!\n"); + return ret; + } + } + /* External Local Bus interface (ELBI) registers */ ep->elbi_base =3D devm_platform_ioremap_resource_byname(pdev, "elbi"); if (IS_ERR(ep->elbi_base)) @@ -397,6 +631,22 @@ static int exynos_pcie_probe(struct platform_device *p= dev) if (ret < 0) goto fail_phy_init; =20 + break; + case DW_PCIE_EP_TYPE: + phy_init(ep->phy); + + ep->pci.ep.ops =3D pdata->ep_ops; + + ret =3D dw_pcie_ep_init(&ep->pci.ep); + if (ret < 0) + goto fail_phy_init; + + ret =3D dw_pcie_ep_init_registers(&ep->pci.ep); + if (ret) + goto fail_phy_init; + + pci_epc_init_notify(ep->pci.ep.epc); + break; default: dev_err(dev, "invalid device type\n"); @@ -436,6 +686,9 @@ static int exynos_pcie_suspend_noirq(struct device *dev) if (ep->pdata->device_mode =3D=3D DW_PCIE_EP_TYPE) return 0; =20 + if (ep->pdata->dwc_ops->stop_link) + ep->pdata->dwc_ops->stop_link(pci); + if (ep->pdata->soc_variant =3D=3D EXYNOS_5433) exynos_pcie_assert_core_reset(ep); phy_power_off(ep->phy); @@ -471,6 +724,23 @@ static const struct dev_pm_ops exynos_pcie_pm_ops =3D { exynos_pcie_resume_noirq) }; =20 + +static const struct samsung_pcie_pdata fsd_hw3_pcie_rc_pdata =3D { + .dwc_ops =3D &fsd_dw_pcie_ops, + .host_ops =3D &fsd_pcie_host_ops, + .res_ops =3D &fsd_res_ops_data, + .soc_variant =3D FSD, + .device_mode =3D DW_PCIE_RC_TYPE, +}; + +static const struct samsung_pcie_pdata fsd_hw3_pcie_ep_pdata =3D { + .dwc_ops =3D &fsd_dw_pcie_ops, + .ep_ops =3D &fsd_ep_ops, + .res_ops =3D &fsd_res_ops_data, + .soc_variant =3D FSD, + .device_mode =3D DW_PCIE_EP_TYPE, +}; + static const struct samsung_pcie_pdata exynos_5433_pcie_rc_pdata =3D { .dwc_ops =3D &exynos_dw_pcie_ops, .pci_ops =3D &exynos_pci_ops, @@ -485,6 +755,14 @@ static const struct of_device_id exynos_pcie_of_match[= ] =3D { .compatible =3D "samsung,exynos5433-pcie", .data =3D (void *) &exynos_5433_pcie_rc_pdata, }, + { + .compatible =3D "tesla,fsd-pcie", + .data =3D (void *) &fsd_hw3_pcie_rc_pdata, + }, + { + .compatible =3D "tesla,fsd-pcie-ep", + .data =3D (void *) &fsd_hw3_pcie_ep_pdata, + }, { }, }; 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Mon, 11 Aug 2025 15:47:43 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org, kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, jh80.chung@samsung.com, pankaj.dubey@samsung.com, Shradha Todi Subject: [PATCH v3 12/12] arm64: dts: fsd: Add PCIe support for Tesla FSD SoC Date: Mon, 11 Aug 2025 21:16:38 +0530 Message-ID: <20250811154638.95732-13-shradha.t@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250811154638.95732-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525 References: <20250811154638.95732-1-shradha.t@samsung.com> Add the support for PCIe controller driver and phy driver for Tesla FSD. It includes support for both RC and EP. Signed-off-by: Pankaj Dubey Signed-off-by: Shradha Todi --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 34 +++++ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 65 +++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 147 +++++++++++++++++++++ 3 files changed, 246 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/te= sla/fsd-evb.dts index 9ff22e1c8723..1b63c5d72d19 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -130,3 +130,37 @@ &serial_0 { &ufs { status =3D "okay"; }; + +&pcierc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>, + <&pcie0_slot1>; +}; + +&pcieep2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>, + <&pcie0_slot1>; +}; + +&pcierc0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, + <&pcie0_slot0>; +}; + +&pcieep0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, + <&pcie0_slot0>; +}; + +&pcierc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; +}; + +&pcieep1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/d= ts/tesla/fsd-pinctrl.dtsi index 6f4658f57453..fa99aa4b9906 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -120,6 +120,27 @@ eth0_mdio: eth0-mdio-pins { samsung,pin-pud =3D ; samsung,pin-drv =3D ; }; + + pcie1_clkreq: pcie1-clkreq-pins { + samsung,pins =3D "gpf6-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie1_wake: pcie1-wake-pins { + samsung,pins =3D "gpf6-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie1_preset: pcie1-preset-pins { + samsung,pins =3D "gpf6-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; }; =20 &pinctrl_peric { @@ -493,6 +514,50 @@ eth1_mdio: eth1-mdio-pins { samsung,pin-pud =3D ; samsung,pin-drv =3D ; }; + + pcie0_clkreq: pcie0-clkreq-pins { + samsung,pins =3D "gpc8-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie0_wake0: pcie0-wake0-pins { + samsung,pins =3D "gpc8-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie0_preset0: pcie0-preset0-pins { + samsung,pins =3D "gpc8-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie0_wake1: pcie0-wake1-pins { + samsung,pins =3D "gpc8-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pcie0_slot0: pcie0-gpio22-pins { + samsung,pins =3D "gpg2-6"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + samsung,pin-val =3D <1>; + }; + + pcie0_slot1: pcie0-gpio23-pins { + samsung,pins =3D "gpg2-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + samsung,pin-val =3D <1>; + }; }; =20 &pinctrl_pmu { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla= /fsd.dtsi index a5ebb3f9b18f..8ed8d2131855 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -1009,6 +1009,16 @@ ethernet1: ethernet@14300000 { status =3D "disabled"; }; =20 + pciephy0: pcie-phy@15080000 { + compatible =3D "tesla,fsd-pcie-phy0"; + reg =3D <0x0 0x15080000 0x0 0x2000>, + <0x0 0x150a0000 0x0 0x1000>; + #phy-cells =3D <0>; + samsung,pmu-syscon =3D <&pmu_system_controller>; + samsung,fsys-sysreg =3D <&sysreg_fsys0>; + status =3D "disabled"; + }; + ufs: ufs@15120000 { compatible =3D "tesla,fsd-ufs"; reg =3D <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ @@ -1057,6 +1067,143 @@ ethernet0: ethernet@15300000 { iommus =3D <&smmu_fsys0 0x0 0x1>; status =3D "disabled"; }; + + pcierc2: pcie@15400000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x15400000 0x0 0x2000>, + <0x0 0x15090000 0x0 0x1000>, + <0x0 0x15800000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0 0x15801000 0 0x15801000 0 0xffefff>; + clocks =3D <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + phys =3D <&pciephy0>; + iommu-map =3D <0x0 &smmu_fsys0 0x4 0x10000>; + iommu-map-mask =3D <0x0>; + samsung,syscon-pcie =3D <&sysreg_fsys0 0x434>; + status =3D "disabled"; + }; + + pcieep2: pcie-ep@15400000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x15090000 0x0 0x1000>, + <0x0 0x15400000 0x0 0x2000>, + <0x0 0x15402000 0x0 0x80>, + <0x0 0x15800000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>, + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + phys =3D <&pciephy0>; + samsung,syscon-pcie =3D <&sysreg_fsys0 0x434>; + status =3D "disabled"; + }; + + pciephy1: pcie-phy@16880000 { + compatible =3D "tesla,fsd-pcie-phy1"; + reg =3D <0x0 0x16880000 0x0 0x2000>, + <0x0 0x16860000 0x0 0x1000>; + #phy-cells =3D <0>; + samsung,pmu-syscon =3D <&pmu_system_controller>; + samsung,fsys-sysreg =3D <&sysreg_fsys1>; + status =3D "disabled"; + }; + + pcierc0: pcie@16a00000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x17000000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0 0x17001000 0 0x17001000 0 0xffefff>; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + iommu-map =3D <0x0 &smmu_imem 0x0 0x10000>; + iommu-map-mask =3D <0x0>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + status =3D "disabled"; + }; + + pcieep0: pcie-ep@16a00000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x168b0000 0x0 0x1000>, + <0x0 0x16a00000 0x0 0x2000>, + <0x0 0x16a02000 0x0 0x80>, + <0x0 0x17000000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x50c>; + status =3D "disabled"; + }; + + pcierc1: pcie@16b00000 { + compatible =3D "tesla,fsd-pcie"; + reg =3D <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x1000>; + reg-names =3D "dbi", "elbi", "config"; + ranges =3D <0x82000000 0 0x18001000 0 0x18001000 0 0xffefff>; + clocks =3D <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + device_type =3D "pci"; + interrupts =3D ; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x510>; + status =3D "disabled"; + }; + + pcieep1: pcie-ep@16b00000 { + compatible =3D "tesla,fsd-pcie-ep"; + reg =3D <0x0 0x168c0000 0x0 0x1000>, + <0x0 0x16b00000 0x0 0x2000>, + <0x0 0x16b02000 0x0 0x80>, + <0x0 0x18000000 0x0 0xff0000>; + reg-names =3D "elbi", "dbi", "dbi2", "addr_space"; + clocks =3D <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>, + <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>; + clock-names =3D "aux", "dbi", "mstr", "slv"; + num-lanes =3D <4>; + phys =3D <&pciephy1>; + samsung,syscon-pcie =3D <&sysreg_fsys1 0x510>; + status =3D "disabled"; + }; }; }; =20 --=20 2.49.0