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charset="utf-8" Document Multi-Circular Queue (MCQ) register space for Qualcomm UFS controllers. Signed-off-by: Ram Kumar Dwivedi --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 6c6043d9809e..daf681b0e23b 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -89,9 +89,13 @@ properties: maxItems: 2 =20 reg-names: - items: - - const: std - - const: ice + oneOf: + - items: + - const: std + - const: ice + - items: + - const: ufs_mem + - const: mcq =20 required-opps: maxItems: 1 @@ -177,9 +181,9 @@ allOf: - const: rx_lane1_sync_clk reg: minItems: 1 - maxItems: 1 + maxItems: 2 reg-names: - maxItems: 1 + maxItems: 2 =20 - if: properties: @@ -280,7 +284,7 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 2 clocks: minItems: 7 maxItems: 8 --=20 2.50.1 From nobody Sun Oct 5 00:14:11 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0B312561B9; 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charset="utf-8" Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8650 platform by updating the device tree node. This includes adding new register region for MCQ and specifying the MSI parent required for MCQ operation. Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index e14d3d778b71..1885d88abc3a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3982,7 +3982,10 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0 0x01d84000 0 0x3000>, + <0 0x1da0000 0 0x15000>; + reg-names =3D "ufs_mem", + "mcq"; =20 interrupts =3D ; =20 @@ -4020,6 +4023,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 iommus =3D <&apps_smmu 0x60 0>; =20 + msi-parent =3D <&gic_its 0x60>; + lanes-per-direction =3D <2>; qcom,ice =3D <&ice>; =20 --=20 2.50.1 From nobody Sun Oct 5 00:14:11 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA2D5253B64; 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charset="utf-8" From: Palash Kambar Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8750 platform by updating the device tree node. This includes adding new register region for MCQ and specifying the MSI parent required for MCQ operation. Signed-off-by: Palash Kambar Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 4643705021c6..3cd701ca4020 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3329,7 +3329,10 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufs@1d84000 { compatible =3D "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0x0 0x01d84000 0x0 0x3000>; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x1da0000 0x0 0x2000>; + reg-names =3D "ufs_mem", + "mcq"; =20 interrupts =3D ; =20 @@ -3363,11 +3366,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "cpu-ufs"; =20 power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; =20 iommus =3D <&apps_smmu 0x60 0>; dma-coherent; - + msi-parent =3D <&gic_its 0x60>; lanes-per-direction =3D <2>; =20 phys =3D <&ufs_mem_phy>; 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charset="utf-8" From: Nitin Rawat The current MCQ resource configuration involves multiple resource mappings and dynamic resource allocation. Simplify the resource mapping by directly mapping the single "mcq" resource from device tree to hba->mcq_base instead of mapping multiple separate resources (RES_UFS, RES_MCQ, RES_MCQ_SQD, RES_MCQ_VS). It also uses predefined offsets for MCQ doorbell registers (SQD, CQD, SQIS, CQIS) relative to the MCQ base,providing clearer memory layout clarity. Additionally update vendor-specific register offset UFS_MEM_CQIS_VS offset from 0x8 to 0x4008 to align with the hardware programming guide. The new approach assumes the device tree provides a single "mcq" resource that encompasses the entire MCQ configuration space, making the driver more maintainable and less prone to resource mapping errors. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 146 +++++++++++++----------------------- drivers/ufs/host/ufs-qcom.h | 21 +++++- 2 files changed, 72 insertions(+), 95 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 76fc70503a62..984d16b4075a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1910,116 +1910,73 @@ static void ufs_qcom_config_scaling_param(struct u= fs_hba *hba, hba->clk_scaling.suspend_on_no_request =3D true; } =20 -/* Resources */ -static const struct ufshcd_res_info ufs_res_info[RES_MAX] =3D { - {.name =3D "ufs_mem",}, - {.name =3D "mcq",}, - /* Submission Queue DAO */ - {.name =3D "mcq_sqd",}, - /* Submission Queue Interrupt Status */ - {.name =3D "mcq_sqis",}, - /* Completion Queue DAO */ - {.name =3D "mcq_cqd",}, - /* Completion Queue Interrupt Status */ - {.name =3D "mcq_cqis",}, - /* MCQ vendor specific */ - {.name =3D "mcq_vs",}, -}; - static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) { struct platform_device *pdev =3D to_platform_device(hba->dev); - struct ufshcd_res_info *res; - struct resource *res_mem, *res_mcq; - int i, ret; - - memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); - - for (i =3D 0; i < RES_MAX; i++) { - res =3D &hba->res[i]; - res->resource =3D platform_get_resource_byname(pdev, - IORESOURCE_MEM, - res->name); - if (!res->resource) { - dev_info(hba->dev, "Resource %s not provided\n", res->name); - if (i =3D=3D RES_UFS) - return -ENODEV; - continue; - } else if (i =3D=3D RES_UFS) { - res_mem =3D res->resource; - res->base =3D hba->mmio_base; - continue; - } + struct resource *res; =20 - res->base =3D devm_ioremap_resource(hba->dev, res->resource); - if (IS_ERR(res->base)) { - dev_err(hba->dev, "Failed to map res %s, err=3D%d\n", - res->name, (int)PTR_ERR(res->base)); - ret =3D PTR_ERR(res->base); - res->base =3D NULL; - return ret; - } + /* Map the MCQ configuration region */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq"); + if (!res) { + dev_err(hba->dev, "MCQ resource not found in device tree\n"); + return -ENODEV; } =20 - /* MCQ resource provided in DT */ - res =3D &hba->res[RES_MCQ]; - /* Bail if MCQ resource is provided */ - if (res->base) - goto out; - - /* Explicitly allocate MCQ resource from ufs_mem */ - res_mcq =3D devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); - if (!res_mcq) - return -ENOMEM; - - res_mcq->start =3D res_mem->start + - MCQ_SQATTR_OFFSET(hba->mcq_capabilities); - res_mcq->end =3D res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; - res_mcq->flags =3D res_mem->flags; - res_mcq->name =3D "mcq"; - - ret =3D insert_resource(&iomem_resource, res_mcq); - if (ret) { - dev_err(hba->dev, "Failed to insert MCQ resource, err=3D%d\n", - ret); - return ret; + hba->mcq_base =3D devm_ioremap_resource(hba->dev, res); + if (IS_ERR(hba->mcq_base)) { + dev_err(hba->dev, "Failed to map MCQ region: %ld\n", + PTR_ERR(hba->mcq_base)); + return PTR_ERR(hba->mcq_base); } =20 - res->base =3D devm_ioremap_resource(hba->dev, res_mcq); - if (IS_ERR(res->base)) { - dev_err(hba->dev, "MCQ registers mapping failed, err=3D%d\n", - (int)PTR_ERR(res->base)); - ret =3D PTR_ERR(res->base); - goto ioremap_err; - } - -out: - hba->mcq_base =3D res->base; return 0; -ioremap_err: - res->base =3D NULL; - remove_resource(res_mcq); - return ret; } =20 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) { - struct ufshcd_res_info *mem_res, *sqdao_res; struct ufshcd_mcq_opr_info_t *opr; int i; + u32 doorbell_offsets[OPR_MAX]; =20 - mem_res =3D &hba->res[RES_UFS]; - sqdao_res =3D &hba->res[RES_MCQ_SQD]; - - if (!mem_res->base || !sqdao_res->base) + if (!hba->mcq_base) { + dev_err(hba->dev, "MCQ base not mapped\n"); return -EINVAL; + } + + /* + * Configure doorbell address offsets in MCQ configuration registers. + * These values are offsets relative to mmio_base (UFS_HCI_BASE). + * + * Memory Layout: + * - mmio_base =3D UFS_HCI_BASE + * - mcq_base =3D MCQ_CONFIG_BASE =3D mmio_base + (UFS_QCOM_MCQCAP_QCFGP= TR * 0x200) + * - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x= 200) + + * - UFS_QCOM_MCQ_SQD_OFFSET + * - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET + */ + + doorbell_offsets[OPR_SQD] =3D UFS_QCOM_SQD_ADDR_OFFSET; + doorbell_offsets[OPR_SQIS] =3D UFS_QCOM_SQIS_ADDR_OFFSET; + doorbell_offsets[OPR_CQD] =3D UFS_QCOM_CQD_ADDR_OFFSET; + doorbell_offsets[OPR_CQIS] =3D UFS_QCOM_CQIS_ADDR_OFFSET; =20 + /* + * Configure MCQ operation registers. + * + * The doorbell registers are physically located within the MCQ region: + * - doorbell_physical_addr =3D mmio_base + doorbell_offset + * - doorbell_physical_addr =3D mcq_base + (doorbell_offset - MCQ_CONFIG_= OFFSET) + */ for (i =3D 0; i < OPR_MAX; i++) { opr =3D &hba->mcq_opr[i]; - opr->offset =3D sqdao_res->resource->start - - mem_res->resource->start + 0x40 * i; - opr->stride =3D 0x100; - opr->base =3D sqdao_res->base + 0x40 * i; + opr->offset =3D doorbell_offsets[i]; /* Offset relative to mmio_base */ + opr->stride =3D UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */ + + /* + * Calculate the actual doorbell base address within MCQ region: + * base =3D mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) + */ + opr->base =3D hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET); } =20 return 0; @@ -2034,12 +1991,13 @@ static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, unsigned long *ocqs) { - struct ufshcd_res_info *mcq_vs_res =3D &hba->res[RES_MCQ_VS]; - - if (!mcq_vs_res->base) + if (!hba->mcq_base) { + dev_err(hba->dev, "MCQ base not mapped\n"); return -EINVAL; + } =20 - *ocqs =3D readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); + /* Read from MCQ vendor-specific register in MCQ region */ + *ocqs =3D readl(hba->mcq_base + UFS_MEM_CQIS_VS); =20 return 0; } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index e0e129af7c16..533e3297045f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,6 +33,25 @@ #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) =20 +/* Qualcomm MCQ Configuration */ +#define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ +#define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* = 0x1C000 */ + +/* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */ +#define UFS_QCOM_MCQ_SQD_OFFSET 0x5000 +#define UFS_QCOM_MCQ_CQD_OFFSET 0x5080 +#define UFS_QCOM_MCQ_SQIS_OFFSET 0x5040 +#define UFS_QCOM_MCQ_CQIS_OFFSET 0x50C0 +#define UFS_QCOM_MCQ_STRIDE 0x100 + +/* Calculated doorbell address offsets (relative to mmio_base) */ +#define UFS_QCOM_SQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_SQD_OFFSET) +#define UFS_QCOM_CQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_CQD_OFFSET) +#define UFS_QCOM_SQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_SQIS_OFFSET) +#define UFS_QCOM_CQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_CQIS_OFFSET) + +#define REG_UFS_MCQ_STRIDE UFS_QCOM_MCQ_STRIDE + /* QCOM UFS host controller vendor specific registers */ enum { REG_UFS_SYS1CLK_1US =3D 0xC0, @@ -96,7 +115,7 @@ enum { }; =20 enum { - UFS_MEM_CQIS_VS =3D 0x8, + UFS_MEM_CQIS_VS =3D 0x4008, }; =20 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) --=20 2.50.1