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charset="utf-8" From: Sricharan Ramabadhran CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. Add support for the APSS PLL, RCG and clock enable for ipq5424. The PLL, RCG register space are clubbed. Hence adding new APSS driver for both PLL and RCG/CBC control. Also the L3 cache has a separate pll and needs to be scaled along with the CPU and is modeled as an ICC clock. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Removed clock notifier, moved L3 pll to icc-clk, used existing alpha pll structure ] Signed-off-by: Varadarajan Narayanan Reviewed-by: Konrad Dybcio --- v7: Use index instead of clock-names in l3 pll Select IPQ_APSS_5424 if IPQ_GCC_5424 is enabled v6: Drop all clock-names and use index instead Fix coding style issues v5: Use enums instead of clock names in clock struct Add 'sync_state =3D icc_sync_state' v4: s/gpll0/clk_ref/g v3: Use the qcom_cc_driver_data framework to trim down apss_ipq5424_probe Rearrange structures to use in other structures v2: Model L3 pll as ICC clock and add relevant structures Use CLK_ALPHA_PLL_TYPE_HUAYRA_2290 register offsets instead of duplicate ipq5424_pll_offsets definition. Inline clock rates. Fix MODULE_LICENSE --- drivers/clk/qcom/Kconfig | 9 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq5424.c | 265 ++++++++++++++++++++++++++++++++ 3 files changed, 275 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq5424.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6cb6cd3e1778..aeb6197d7c90 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -187,6 +187,15 @@ config IPQ_APSS_PLL Say Y if you want to support CPU frequency scaling on ipq based devices. =20 +config IPQ_APSS_5424 + tristate "IPQ APSS Clock Controller" + select IPQ_APSS_PLL + default y if IPQ_GCC_5424 + help + Support for APSS Clock controller on Qualcom IPQ5424 platform. + Say Y if you want to support CPU frequency scaling on ipq based + devices. + config IPQ_APSS_6018 tristate "IPQ APSS Clock Controller" select IPQ_APSS_PLL diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ddb7e06fae40..98de55eb6402 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) +=3D gpucc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o +obj-$(CONFIG_IPQ_APSS_5424) +=3D apss-ipq5424.o obj-$(CONFIG_IPQ_APSS_6018) +=3D apss-ipq6018.o obj-$(CONFIG_IPQ_CMN_PLL) +=3D ipq-cmn-pll.o obj-$(CONFIG_IPQ_GCC_4019) +=3D gcc-ipq4019.o diff --git a/drivers/clk/qcom/apss-ipq5424.c b/drivers/clk/qcom/apss-ipq542= 4.c new file mode 100644 index 000000000000..4c67f722e009 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq5424.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" + +enum { + DT_XO, + DT_CLK_REF, +}; + +enum { + P_XO, + P_GPLL0, + P_APSS_PLL_EARLY, + P_L3_PLL, +}; + +struct apss_clk { + struct notifier_block cpu_clk_notifier; + struct clk_hw *hw; + struct device *dev; + struct clk *l3_clk; +}; + +static const struct alpha_pll_config apss_pll_config =3D { + .l =3D 0x3b, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll ipq5424_apss_pll =3D { + .offset =3D 0x0, + .config =3D &apss_pll_config, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "apss_pll", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_XO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_apss_silver_clk_src[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_CLK_REF }, + { .hw =3D &ipq5424_apss_pll.clkr.hw }, +}; + +static const struct parent_map parents_apss_silver_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +static const struct freq_tbl ftbl_apss_clk_src[] =3D { + F(816000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1416000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1800000000, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +static struct clk_rcg2 apss_silver_clk_src =3D { + .cmd_rcgr =3D 0x0080, + .freq_tbl =3D ftbl_apss_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_apss_silver_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "apss_silver_clk_src", + .parent_data =3D parents_apss_silver_clk_src, + .num_parents =3D ARRAY_SIZE(parents_apss_silver_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apss_silver_core_clk =3D { + .halt_reg =3D 0x008c, + .clkr =3D { + .enable_reg =3D 0x008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "apss_silver_core_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &apss_silver_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct alpha_pll_config l3_pll_config =3D { + .l =3D 0x29, + .config_ctl_val =3D 0x08200920, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x04000000, + .user_ctl_val =3D 0xf, +}; + +static struct clk_alpha_pll ipq5424_l3_pll =3D { + .offset =3D 0x10000, + .config =3D &l3_pll_config, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], + .flags =3D SUPPORTS_DYNAMIC_UPDATE, + .clkr =3D { + .enable_reg =3D 0x0, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "l3_pll", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_XO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static const struct clk_parent_data parents_l3_clk_src[] =3D { + { .index =3D DT_XO }, + { .index =3D DT_CLK_REF }, + { .hw =3D &ipq5424_l3_pll.clkr.hw }, +}; + +static const struct parent_map parents_l3_clk_src_map[] =3D { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_L3_PLL, 5 }, +}; + +static const struct freq_tbl ftbl_l3_clk_src[] =3D { + F(816000000, P_L3_PLL, 1, 0, 0), + F(984000000, P_L3_PLL, 1, 0, 0), + F(1272000000, P_L3_PLL, 1, 0, 0), + { } +}; + +static struct clk_rcg2 l3_clk_src =3D { + .cmd_rcgr =3D 0x10080, + .freq_tbl =3D ftbl_l3_clk_src, + .hid_width =3D 5, + .parent_map =3D parents_l3_clk_src_map, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "l3_clk_src", + .parent_data =3D parents_l3_clk_src, + .num_parents =3D ARRAY_SIZE(parents_l3_clk_src), + .ops =3D &clk_rcg2_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch l3_core_clk =3D { + .halt_reg =3D 0x1008c, + .clkr =3D { + .enable_reg =3D 0x1008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "l3_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &l3_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static const struct regmap_config apss_ipq5424_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x20000, + .fast_io =3D true, +}; + +static struct clk_regmap *apss_ipq5424_clks[] =3D { + [APSS_PLL_EARLY] =3D &ipq5424_apss_pll.clkr, + [APSS_SILVER_CLK_SRC] =3D &apss_silver_clk_src.clkr, + [APSS_SILVER_CORE_CLK] =3D &apss_silver_core_clk.clkr, + [L3_PLL] =3D &ipq5424_l3_pll.clkr, + [L3_CLK_SRC] =3D &l3_clk_src.clkr, + [L3_CORE_CLK] =3D &l3_core_clk.clkr, +}; + +static struct clk_alpha_pll *ipa5424_apss_plls[] =3D { + &ipq5424_l3_pll, + &ipq5424_apss_pll, +}; + +static struct qcom_cc_driver_data ipa5424_apss_driver_data =3D { + .alpha_plls =3D ipa5424_apss_plls, + .num_alpha_plls =3D ARRAY_SIZE(ipa5424_apss_plls), +}; + +#define IPQ_APPS_PLL_ID (5424 * 3) /* some unique value */ + +static const struct qcom_icc_hws_data icc_ipq5424_cpu_l3[] =3D { + { MASTER_CPU, SLAVE_L3, L3_CORE_CLK }, +}; + +static const struct qcom_cc_desc apss_ipq5424_desc =3D { + .config =3D &apss_ipq5424_regmap_config, + .clks =3D apss_ipq5424_clks, + .num_clks =3D ARRAY_SIZE(apss_ipq5424_clks), + .icc_hws =3D icc_ipq5424_cpu_l3, + .num_icc_hws =3D ARRAY_SIZE(icc_ipq5424_cpu_l3), + .icc_first_node_id =3D IPQ_APPS_PLL_ID, + .driver_data =3D &ipa5424_apss_driver_data, +}; + +static int apss_ipq5424_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &apss_ipq5424_desc); +} + +static const struct of_device_id apss_ipq5424_match_table[] =3D { + { .compatible =3D "qcom,ipq5424-apss-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, apss_ipq5424_match_table); + +static struct platform_driver apss_ipq5424_driver =3D { + .probe =3D apss_ipq5424_probe, + .driver =3D { + .name =3D "apss-ipq5424-clk", + .of_match_table =3D apss_ipq5424_match_table, + .sync_state =3D icc_sync_state, + }, +}; + +module_platform_driver(apss_ipq5424_driver); + +MODULE_DESCRIPTION("QCOM APSS IPQ5424 CLK Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1