From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 881D12DCF4C; Mon, 11 Aug 2025 09:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902892; cv=none; b=Jc9JNMCUDkld3xxI+M0pocHRwWn4YHvyUmN8S1t9idKbPNDfklU59XKXZFL5voXLEzXzTTcweoUV5WcCf+pgAicIwY4nq66MfE40djWIV3ml1ZoRMyjEqufHMaQqrSxCcFQRdCfIGNGk2MHDqCZGz/OhoNHptmvg+SOMQqPNF24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902892; c=relaxed/simple; bh=AIVkug2vJfK1kkjVROGHj3pbwPQGLM2oRGiF3Almj/Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T2cScH3nkTAoBIrBjiSBoGS6JhGHwSXFWUHZCyatljn6Vt/IvfNlqWe/4qbezs3OaCVLvEDrEdWbtxEeC5UYnFTpV+N8jGx+AMBX0Uzs2queKt/5wYxcq3EqEqGZoY9yDXXIuHYJ5mgROrACe/D1FB38JL19/+LG+pVf5Rv4tPE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=njdxcJmU; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="njdxcJmU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902891; x=1786438891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AIVkug2vJfK1kkjVROGHj3pbwPQGLM2oRGiF3Almj/Q=; b=njdxcJmU0TaaIhqo9JltyLHDxzzUR5rHhMPcxGNi+wCHOtjboYWtXRCc wxlySzO1PKds/EYAo2Fvqd99ZniQU3+m1HV2usvM7big3r7k06hamERtV kL3JwOEJy9KDgASWNauSI9GrVwLkKxsOSZX4ZqUUpUuWfCvDehNNCoqlC By/Z7aRRwcM6S9De4ojyQon9EMP3PQ0R5eHAjZQjt8BVzoicHK+291STh 8zl9OdDSxNA2dPaFJ9dcZACqoBOZqN3WxGgW6vbiahSAvKEJIiydWMZXg qBRxJKOqxc+ZuTfxnyj/0xNI28YyZCZDKWa+dSQPYya/GRovF9WWy6D/x A==; X-CSE-ConnectionGUID: YAobInAwRSi3U3Thfv+zAg== X-CSE-MsgGUID: n4F0ZcuYRQeD4Eblrhlgkg== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107309" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107309" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:31 -0700 X-CSE-ConnectionGUID: /Ea2sNIaRlqX7Ggk9NV8Ig== X-CSE-MsgGUID: ZhRWKeYETvWcr/ksBAgUlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219821" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:28 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi Subject: [Patch v2 1/6] perf/x86/intel: Use early_initcall() to hook bts_init() Date: Mon, 11 Aug 2025 17:00:29 +0800 Message-Id: <20250811090034.51249-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After the commit 'd971342d38bf ("perf/x86/intel: Decouple BTS initialization from PEBS initialization")' is introduced, x86_pmu.bts would initialized in bts_init() which is hooked by arch_initcall(). Whereas init_hw_perf_events() is hooked by early_initcall(). Once the core PMU is initialized, nmi watchdog initialization is called immediately before bts_init() is called. It leads to the BTS buffer is not really initialized since bts_init() is not called and x86_pmu.bts is still false at that time. Worse, BTS buffer would never be initialized then unless all core PMU events are freed and reserve_ds_buffers() is called again. Thus aligning with init_hw_perf_events(), use early_initcall() to hook bts_init() to ensure x86_pmu.bts is initialized before nmi watchdog initialization. Fixes: d971342d38bf ("perf/x86/intel: Decouple BTS initialization from PEBS= initialization") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/bts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 61da6b8a3d51..cbac54cb3a9e 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -643,4 +643,4 @@ static __init int bts_init(void) =20 return perf_pmu_register(&bts_pmu, "intel_bts", -1); } -arch_initcall(bts_init); +early_initcall(bts_init); --=20 2.34.1 From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5499F2DD608; Mon, 11 Aug 2025 09:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902896; cv=none; b=OBbiRhHIfK/OcaLN0A6+o5GrX/TsfY6KuAnTV1F+9DqRMOYuoi9e+TzlEMMzvvC1dPSrQOV9XFiKnTBdaUqyyKr/KCqtph5lz9fAc4HtuQZ/DMxG8qD17JgAz1uroXI6Pxdi/tIyNazHiPAVtpoJA8qI3Yl6s2MwhKVr5cMzbD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902896; c=relaxed/simple; bh=sZRpO4rbclFWtzr9ZWXs4UzuQzYyrXnLfzfs+08PKFk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oQBNQl6PEZCIQOOJwJbH6HNmIbBoYzBal643Gn+hucEzp+dAkhY9w5Q3R7Pdpyk/UJdZ+7tNtdA5wqPfn6jrE4327PdRc+azEdTjZrj1OUzHtCUjNgwzYmYhL6+5mEw985pvDWBj8weUZVynKaOSGh89dMAZJCDZz/KJINpl27w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PsDKzuSS; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PsDKzuSS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902895; x=1786438895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sZRpO4rbclFWtzr9ZWXs4UzuQzYyrXnLfzfs+08PKFk=; b=PsDKzuSSAWq19O6w9uZiC3MP21LOXJH4dGLWmBVWv/w35tVp85jUPgEx X7OG5R60nGUmok7yYa9z49NPnvh6P41aKmPwrv6TvW6n1TkZumKhhnN7P lCl7yl3LAXZNt5p86PntO7Ess1n8q5/an/CqGvz2mQu+ym6wcTGhqXoTB +saJbdLZLefU8dDHaUjWNJly1oyEA/js3aRER2Syx50OODE/GCvmnICl2 lFRvaJjOv1nDtg2cZcSS7e/PGB7WPhgthAyDnem8JpFYNqnlP+dEKJpgf wiW4Gjeg5YkZ3TY7fpD9fT99gKtU1aB7QTTK66jS2jivMFfOApNRFxNiN Q==; X-CSE-ConnectionGUID: ctDPmsdxRz6i+Nab1tRjCA== X-CSE-MsgGUID: heXwgtDVRsuTPnGpH6iAyQ== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107318" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107318" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:35 -0700 X-CSE-ConnectionGUID: I5rPCiDUTHamXUJc72hQ8w== X-CSE-MsgGUID: L/d0MWl3QVKyLY275t6kyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219831" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:31 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi Subject: [Patch v2 2/6] perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error Date: Mon, 11 Aug 2025 17:00:30 +0800 Message-Id: <20250811090034.51249-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When running perf_fuzzer on PTL, sometimes the below "unchecked MSR access error" is seen when accessing IA32_PMC_x_CFG_B MSRs. [ 55.611268] unchecked MSR access error: WRMSR to 0x1986 (tried to write = 0x0000000200000001) at rIP: 0xffffffffac564b28 (native_write_msr+0x8/0x30) [ 55.611280] Call Trace: [ 55.611282] [ 55.611284] ? intel_pmu_config_acr+0x87/0x160 [ 55.611289] intel_pmu_enable_acr+0x6d/0x80 [ 55.611291] intel_pmu_enable_event+0xce/0x460 [ 55.611293] x86_pmu_start+0x78/0xb0 [ 55.611297] x86_pmu_enable+0x218/0x3a0 [ 55.611300] ? x86_pmu_enable+0x121/0x3a0 [ 55.611302] perf_pmu_enable+0x40/0x50 [ 55.611307] ctx_resched+0x19d/0x220 [ 55.611309] __perf_install_in_context+0x284/0x2f0 [ 55.611311] ? __pfx_remote_function+0x10/0x10 [ 55.611314] remote_function+0x52/0x70 [ 55.611317] ? __pfx_remote_function+0x10/0x10 [ 55.611319] generic_exec_single+0x84/0x150 [ 55.611323] smp_call_function_single+0xc5/0x1a0 [ 55.611326] ? __pfx_remote_function+0x10/0x10 [ 55.611329] perf_install_in_context+0xd1/0x1e0 [ 55.611331] ? __pfx___perf_install_in_context+0x10/0x10 [ 55.611333] __do_sys_perf_event_open+0xa76/0x1040 [ 55.611336] __x64_sys_perf_event_open+0x26/0x30 [ 55.611337] x64_sys_call+0x1d8e/0x20c0 [ 55.611339] do_syscall_64+0x4f/0x120 [ 55.611343] entry_SYSCALL_64_after_hwframe+0x76/0x7e On PTL, GP counter 0 and 1 doesn't support auto counter reload feature, thus it would trigger a #GP when trying to write 1 on bit 0 of CFG_B MSR which requires to enable auto counter reload on GP counter 0. The root cause of causing this issue is the check for auto counter reload (ACR) counter mask from user space is incorrect in intel_pmu_acr_late_setup() helper. It leads to an invalid ACR counter mask from user space could be set into hw.config1 and then written into CFG_B MSRs and trigger the MSR access warning. e.g., User may create a perf event with ACR counter mask (config2=3D0xcb), and there is only 1 event created, so "cpuc->n_events" is 1. The correct check condition should be "i + idx >=3D cpuc->n_events" instead of "i + idx > cpuc->n_events" (it looks a typo). Otherwise, the counter mask would traverse twice and an invalid "cpuc->assign[1]" bit (bit 0) is set into hw.config1 and cause MSR accessing error. Besides, also check if the ACR counter mask corresponding events are ACR events. If not, filter out these counter mask. If a event is not a ACR event, it could be scheduled to an HW counter which doesn't support ACR. It's invalid to add their counter index in ACR counter mask. Furthermore, remove the WARN_ON_ONCE() since it's easily triggered as user could set any invalid ACR counter mask and the warning message could mislead users. Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi Reviewed-by: Kan Liang --- arch/x86/events/intel/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c2fb729c270e..15da60cf69f2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2997,7 +2997,8 @@ static void intel_pmu_acr_late_setup(struct cpu_hw_ev= ents *cpuc) if (event->group_leader !=3D leader->group_leader) break; for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_ID= X_MAX) { - if (WARN_ON_ONCE(i + idx > cpuc->n_events)) + if (i + idx >=3D cpuc->n_events || + !is_acr_event_group(cpuc->event_list[i + idx])) return; __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); } --=20 2.34.1 From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB1672DE6E5; Mon, 11 Aug 2025 09:01:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902901; cv=none; b=nDawK2FpZn/ILrScQ5KjMKDUNCV6lSHuSANIXbVzES7wxAEAi8ERzVR71v8qr/S9V3SUt98nY0stmN0nETUUU56bp3+16pMOCIUPk6Z+hWjZfW6pe6oIK+ZIF0Swj1BRKV5MnixqLRK1xW9vCRfSgO1BmsQr4edblR3pl93oKTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902901; c=relaxed/simple; bh=7LC99mG6CAsODrq/k96iOPGgZQeZVG2EuMixAhEZ0hA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VljdJ1++wfCtdjQCXq/fVoZgF19vQtqhWG35ESXyUez+vuYdJTIzgmiEE0Imi2CBy3YrwGKKsbUm+T7xXdvaPzAxWQ2jJq0oSeNfrFkZdnfiB6DnX44sUbexsQKDqGvawIX9Uw8NoVrfiInmkJsldjTHD2z7TBYlxr+DGvdW5kY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jBgdJDmW; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jBgdJDmW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902900; x=1786438900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7LC99mG6CAsODrq/k96iOPGgZQeZVG2EuMixAhEZ0hA=; b=jBgdJDmWpGdJY19UHmGSrMTNyvuI64Kl7oj0RB6zSpMY50yebHEcXIzx qCvOSG4CHJiE2N5Do2jPqCpBaxvEwfe67XNuiUmbMdse1jlxF/StGo+yC gnzi0lrMMIqtkQTsLYqQxtwd+1FMimXFPX1GuVB0wbXsvnX6DbJ5ZJEhZ yRbmd0wyx1qXTShaA8Fmv5qCoXFszvI1/voP/fFuutdtRvpHBWEoZDd2X LYOs02ZnmR9wP5pvIB6bi9MAUe0U+hO/eAXPKyi0ZGV144fU5y3mVPw9i XS9jUjglOEtf1FHjrPDkzgZ+A85FTYB1K+k5UO1AWQloQmUyeuPfkauAP g==; X-CSE-ConnectionGUID: Vo1Ihs12QJe4PDpAv2LQSQ== X-CSE-MsgGUID: 1DJ2qvlkRiKNhKFB5sTrjw== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107342" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107342" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:39 -0700 X-CSE-ConnectionGUID: qg0uc91NQQO8KhtZ8vOKfQ== X-CSE-MsgGUID: gzhvExp+RSWId96/H8XmMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219856" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:35 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi , kernel test robot Subject: [Patch v2 3/6] perf/x86: Check if cpuc->events[*] pointer exists before accessing it Date: Mon, 11 Aug 2025 17:00:31 +0800 Message-Id: <20250811090034.51249-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PMI handler could disable some events as the interrupt throttling and clear the corresponding items in cpuc->events[] array. perf_event_overflow() -> __perf_event_overflow() ->__perf_event_account_interrupt() -> perf_event_throttle_group() -> perf_event_throttle() -> event->pmu->stop() -> x86_pmu_stop() Moreover PMI is NMI on x86 platform and it could interrupt other perf code like setup_pebs_adaptive_sample_data(). So once PMI handling finishes and returns into setup_pebs_adaptive_sample_data() and it could find the cpuc->events[*] becomes NULL and accessing this NULL pointer triggers an invalid memory access and leads to kernel crashes eventually. Thus add NULL check before accessing cpuc->events[*] pointer. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-lkp/202507042103.a15d2923-lkp@intel.com Fixes: 9734e25fbf5a ("perf: Fix the throttle logic for a group") Signed-off-by: Dapeng Mi Tested-by: kernel test robot --- arch/x86/events/core.c | 3 +++ arch/x86/events/intel/core.c | 6 +++++- arch/x86/events/intel/ds.c | 13 ++++++------- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 7610f26dfbd9..f0a3bc57157d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1711,6 +1711,9 @@ int x86_pmu_handle_irq(struct pt_regs *regs) continue; =20 event =3D cpuc->events[idx]; + if (!event) + continue; + last_period =3D event->hw.last_period; =20 val =3D static_call(x86_pmu_update)(event); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 15da60cf69f2..386717b75a09 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2718,6 +2718,8 @@ static void update_saved_topdown_regs(struct perf_eve= nt *event, u64 slots, if (!is_topdown_idx(idx)) continue; other =3D cpuc->events[idx]; + if (!other) + continue; other->hw.saved_slots =3D slots; other->hw.saved_metric =3D metrics; } @@ -2761,6 +2763,8 @@ static u64 intel_update_topdown_event(struct perf_eve= nt *event, int metric_end, if (!is_topdown_idx(idx)) continue; other =3D cpuc->events[idx]; + if (!other) + continue; __icl_update_topdown_event(other, slots, metrics, event ? event->hw.saved_slots : 0, event ? event->hw.saved_metric : 0); @@ -3138,7 +3142,7 @@ static void x86_pmu_handle_guest_pebs(struct pt_regs = *regs, =20 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX)= { event =3D cpuc->events[bit]; - if (!event->attr.precise_ip) + if (!event || !event->attr.precise_ip) continue; =20 perf_sample_data_init(data, 0, event->hw.last_period); diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index c0b7ac1c7594..b23c49e2e06f 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2480,6 +2480,8 @@ static void intel_pmu_pebs_event_update_no_drain(stru= ct cpu_hw_events *cpuc, u64 */ for_each_set_bit(bit, (unsigned long *)&pebs_enabled, X86_PMC_IDX_MAX) { event =3D cpuc->events[bit]; + if (!event) + continue; if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) intel_pmu_save_and_restart_reload(event, 0); } @@ -2579,10 +2581,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs = *iregs, struct perf_sample_d continue; =20 event =3D cpuc->events[bit]; - if (WARN_ON_ONCE(!event)) - continue; - - if (WARN_ON_ONCE(!event->attr.precise_ip)) + if (!event || WARN_ON_ONCE(!event->attr.precise_ip)) continue; =20 /* log dropped samples number */ @@ -2645,9 +2644,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d pebs_status =3D basic->applicable_counters & cpuc->pebs_enabled & mask; for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) { event =3D cpuc->events[bit]; - - if (WARN_ON_ONCE(!event) || - WARN_ON_ONCE(!event->attr.precise_ip)) + if (!event || WARN_ON_ONCE(!event->attr.precise_ip)) continue; =20 if (counts[bit]++) { @@ -2663,6 +2660,8 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d continue; =20 event =3D cpuc->events[bit]; + if (!event) + continue; =20 __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit], counts[bit], setup_pebs_adaptive_sample_data); --=20 2.34.1 From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C2E2DCF6A; Mon, 11 Aug 2025 09:01:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902907; cv=none; b=X6Kipq0YZcWucLL2A+G0EU9Hg2ST0GSPaGaDcDjOgm0dVDYgDcIlTwRpUjQmPP8jB9QNdKmcSy5qA9gL79ruOcR3Ihs0f+VA8ak+9ziqDX0f+gS8n9WjukFBRy8JCzdC93k3+Lmmia8o4SDfyTeO64xzzQ+3Jocpuyku7BelzvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902907; c=relaxed/simple; bh=yroT7CzWxiE6A86M6FMgIQECV5NHrE/bzjF/iVz9y8Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gvoDc/+0FTu3iGIhtOKAv8ojGFFMZknWfckoPfDwiBDCKPfI0K4cAGS5i1p7iRp6VivQQyvjvyRXn+FRVM23+pshIh8Akbp4mginVOUJjZAJ97s5FsqLNVgUdWMEGXAboNWP/PNLqi6GTvWA4Bfl5wT3skoHR0wanX7SeR9tXJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A25IaUzj; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A25IaUzj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902906; x=1786438906; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yroT7CzWxiE6A86M6FMgIQECV5NHrE/bzjF/iVz9y8Y=; b=A25IaUzjPxUDwIX+rx9pNVj0uu+PIcWrnviMOeAhK1ZyGccVrtKHpk3L aqjsmPXhShWGzeIs+amZDS6B8f5QiLJkbAkfjs1JHC70g/sWYlpASe5lv JhiSQ4RWpytevss1t9u8d5i5uC4qFjVfb8iboSegYkTE6vCn7v1iNp+Cw Ekc9snfb1UwgZSdjkODPgPJpAEtDT0r7iV6vvD66SYRwwM/S/QQeiNCV0 DaOkBChRMoaBkT7w+S/RU9LexRL7ZaH4j9bMdtIiC+NOynVYsSQ7HvYm5 2U2K6LpO4US+mrHOpw+UI07Lh6Ki+Betj4wbVhVOW5VLcKNHA4u3s7F6y w==; X-CSE-ConnectionGUID: aQ3pzNC4RCqX9MGnzDyCkQ== X-CSE-MsgGUID: p0GN6dYyS3CKEXxgU3oGAg== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107384" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107384" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:44 -0700 X-CSE-ConnectionGUID: t460OEnaQSSZgVDEkdl6oQ== X-CSE-MsgGUID: E1bMGbCkSe62MtZ/+d5kVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219908" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:39 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi , Yi Lai Subject: [Patch v2 4/6] perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag Date: Mon, 11 Aug 2025 17:00:32 +0800 Message-Id: <20250811090034.51249-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to indicate whether timed PEBS is supported. Timed PEBS adds a new "retired latency" field in basic info group to show the timing info. Please find detailed information about timed PEBS in section 8.4.1 "Timed Processor Event Based Sampling" of "Intel Architecture Instruction Set Extensions and Future Features". This patch adds PERF_CAP_PEBS_TIMING_INFO flag and KVM module leverages this flag to expose timed PEBS feature to guest. Moreover, opportunistically refine the indents and make the macros share consistent indents. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- arch/x86/include/asm/msr-index.h | 14 ++++++++------ tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index b65c3ba5fa14..f627196eb796 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -315,12 +315,14 @@ #define PERF_CAP_PT_IDX 16 =20 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 -#define PERF_CAP_PEBS_TRAP BIT_ULL(6) -#define PERF_CAP_ARCH_REG BIT_ULL(7) -#define PERF_CAP_PEBS_FORMAT 0xf00 -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) +#define PERF_CAP_PEBS_TRAP BIT_ULL(6) +#define PERF_CAP_ARCH_REG BIT_ULL(7) +#define PERF_CAP_PEBS_FORMAT 0xf00 +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ + PERF_CAP_PEBS_TIMING_INFO) =20 #define MSR_IA32_RTIT_CTL 0x00000570 #define RTIT_CTL_TRACEEN BIT(0) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index 5cfb5d74dd5f..daebfd926f08 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -315,12 +315,14 @@ #define PERF_CAP_PT_IDX 16 =20 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 -#define PERF_CAP_PEBS_TRAP BIT_ULL(6) -#define PERF_CAP_ARCH_REG BIT_ULL(7) -#define PERF_CAP_PEBS_FORMAT 0xf00 -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) +#define PERF_CAP_PEBS_TRAP BIT_ULL(6) +#define PERF_CAP_ARCH_REG BIT_ULL(7) +#define PERF_CAP_PEBS_FORMAT 0xf00 +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ + PERF_CAP_PEBS_TIMING_INFO) =20 #define MSR_IA32_RTIT_CTL 0x00000570 #define RTIT_CTL_TRACEEN BIT(0) --=20 2.34.1 From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC68E2DD5EF; Mon, 11 Aug 2025 09:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902916; cv=none; b=HQ0tpmsA8D9jFkZDMB/ALQRzElqa1+/lDK8jVTkr/dQRaCWIPwDostLJbznWOBeTwkdKzbM/I3n+yeNRRMwCL04aHmivr47GzdJ1LCHrVgMdV6FbXPN+GH93tjsNNBg62fFDfSt6A4Eaw3aTmUTD6/GYeid3+G28NuL3sJFBlHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902916; c=relaxed/simple; bh=fSGEJ8LBndoHk9y2A/U407ioZmHKOGrzLCNFN60i/H0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hOai32g1B1ZuJaqbtwAgdpWGQKdjm72EuDMHS3ryILXWt+8dGWmzpmSYEHf7afJD5711tyZqEhoQW/OWQQrr+gYqezzPV0WxRwz7RG7DSqwGJ7AJ+mfoPgnzh5u9nnpWe2LmZ9si2V5h6exB3+pRW+8i/JbQSgAwQAIYjA+POTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NToKSTL/; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NToKSTL/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902915; x=1786438915; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fSGEJ8LBndoHk9y2A/U407ioZmHKOGrzLCNFN60i/H0=; b=NToKSTL/zM2xNHN+HET5bP1wwaGYePUP+lLZ44jRorS5DhRuSI2iZtq5 roiTw4/rBD45Qpv9Dro8seWYxPwag94FD+yxP9nIqEN0xmY+EFRrwhLu3 WCJ1UQxzFAmeI62aVZoiklntNqDhWDOAUjlbMehButCeMhluE8RgUbVDa Za12dmKRqogwI9DLtGGzXcqzRaVA53498QEqfPVIxK3o6xINTVT7aUPUl AGpI4hvVwqo5Tr02PxI79+rwqZcuZM6QnN4Og0MPIJDf4CeGknhI8+DXZ 6AGWZlbf70HlExAFn0lBB9QAGCma1Y8V8Io95N6yyD6pIPCk3sW6nJTFr A==; X-CSE-ConnectionGUID: f89w9kjVRe6JqcvEWM/IpQ== X-CSE-MsgGUID: FEwB4jHiSbe2iJdVG7HwjQ== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107421" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107421" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:47 -0700 X-CSE-ConnectionGUID: uWtYLQ9VSjui4m/Bu+n44w== X-CSE-MsgGUID: Oo1EFSgTQL2bJE7JZc594g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219937" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:44 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi , Yi Lai Subject: [Patch v2 5/6] perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) Date: Mon, 11 Aug 2025 17:00:33 +0800 Message-Id: <20250811090034.51249-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Macro GLOBAL_CTRL_EN_PERF_METRICS is defined to 48 instead of BIT_ULL(48), it's inconsistent with other similar macros. This leads to this macro is quite easily used wrongly since users thinks it's a bit-mask just like other similar macros. Thus change GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) and eliminate this potential misuse. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- arch/x86/events/intel/core.c | 8 ++++---- arch/x86/include/asm/perf_event.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 386717b75a09..cdd10370ed95 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5323,9 +5323,9 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hy= brid_pmu *pmu) 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); =20 if (pmu->intel_cap.perf_metrics) - pmu->intel_ctrl |=3D 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; + pmu->intel_ctrl |=3D GLOBAL_CTRL_EN_PERF_METRICS; else - pmu->intel_ctrl &=3D ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); + pmu->intel_ctrl &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; =20 intel_pmu_check_event_constraints(pmu->event_constraints, pmu->cntr_mask64, @@ -5460,7 +5460,7 @@ static void intel_pmu_cpu_starting(int cpu) rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); if (!perf_cap.perf_metrics) { x86_pmu.intel_cap.perf_metrics =3D 0; - x86_pmu.intel_ctrl &=3D ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); + x86_pmu.intel_ctrl &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; } } =20 @@ -7794,7 +7794,7 @@ __init int intel_pmu_init(void) } =20 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) - x86_pmu.intel_ctrl |=3D 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; + x86_pmu.intel_ctrl |=3D GLOBAL_CTRL_EN_PERF_METRICS; =20 if (x86_pmu.intel_cap.pebs_timing_info) x86_pmu.flags |=3D PMU_FL_RETIRE_LATENCY; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 70d1d94aca7e..f8247ac276c4 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -430,7 +430,7 @@ static inline bool is_topdown_idx(int idx) #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_B= IT) #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 =20 -#define GLOBAL_CTRL_EN_PERF_METRICS 48 +#define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) /* * We model guest LBR event tracing as another fixed-mode PMC like BTS. * --=20 2.34.1 From nobody Sun Oct 5 01:49:29 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77949263C90; Mon, 11 Aug 2025 09:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902922; cv=none; b=Gd17tGQBaTl7NkEFlc/i4yVp/CiOjQQ23PwJ5RXD4lr8yrIga0eWg7ZAsEme96b1WzpfpJn6zTNLMP+HgiDEO/2iHqCz9487EQgf8EjGmxiPFQJJV1z1rbFgw+t+g/afCUuO1y24qXJdijQlCjIB5VBmScXLfPM63W9DFyFX7rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754902922; c=relaxed/simple; bh=P8KdGfXOFljOVpITDk6jNbMaI0Tluc2AyNId32bn8X0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dboTjyoa7CjfbDKPaUnGF0UB5SI3T3xMy7iBGfKjoYMHDOFFE1jyXUE6+oS84ZNgIqejg3SZkYtZ5DN/GckMPzVq44GNynLY+8wGy1+dsJU72bwAzYwqmHKoNlNV713I4TACno7XUg2l/o8+6BbYDuXBCPnbKZklulsd8rEyJ6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nrMcwE5Y; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nrMcwE5Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754902921; x=1786438921; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P8KdGfXOFljOVpITDk6jNbMaI0Tluc2AyNId32bn8X0=; b=nrMcwE5YDSSEradkTK/sw90nPJfFLOUqs5STtw4+gU1xMe2NF9RacFFd pQ97pHM3PrZ+ldJqKppgUvoaCHM/j+b1DQkWujw5uxnr2P5MQ/aOlrR4s OzOKWmdKXh6wX5wZHrlrUIEbzlD5B6QlG3GGACirbjnyO7QaVIE2R+Sn1 61vr6yaGGo2fxysJ3kaieWLDK9lCpdZj24vbQiAyDtAH1WPXOPR8/T0IY QlkQ0nHobYSpNZoUBpPmQB1QT86dABo/DLDGvcTT5jb0TfpPxt7nB1U7h HsQYuzgR2Z5a5yBq8vpMNW5vO9U7JxPCog/bWwgC6zcYHXJjFkUGC2jNz Q==; X-CSE-ConnectionGUID: +9NS8Vw7QO2gp4kaX6cs5g== X-CSE-MsgGUID: p+tz45hAT0icjISLrcBlIw== X-IronPort-AV: E=McAfee;i="6800,10657,11518"; a="57107447" X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="57107447" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2025 02:01:51 -0700 X-CSE-ConnectionGUID: ET+7rkEkSgiiyQhbJMJq2w== X-CSE-MsgGUID: 0uSjbyJxQieZi3HUvpWINA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,278,1747724400"; d="scan'208";a="166219975" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 11 Aug 2025 02:01:48 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi , Yi Lai Subject: [Patch v2 6/6] perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into INTEL_FIXED_BITS_MASK Date: Mon, 11 Aug 2025 17:00:34 +0800 Message-Id: <20250811090034.51249-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> References: <20250811090034.51249-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ICL_FIXED_0_ADAPTIVE is missed to be added into INTEL_FIXED_BITS_MASK, add it and opportunistically refine fixed counter enabling code. Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- arch/x86/events/intel/core.c | 10 +++------- arch/x86/include/asm/perf_event.h | 6 +++++- arch/x86/kvm/pmu.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index cdd10370ed95..1a91b527d3c5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2849,8 +2849,8 @@ static void intel_pmu_enable_fixed(struct perf_event = *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; - u64 mask, bits =3D 0; int idx =3D hwc->idx; + u64 bits =3D 0; =20 if (is_topdown_idx(idx)) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); @@ -2889,14 +2889,10 @@ static void intel_pmu_enable_fixed(struct perf_even= t *event) =20 idx -=3D INTEL_PMC_IDX_FIXED; bits =3D intel_fixed_bits_by_idx(idx, bits); - mask =3D intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); - - if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { + if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) bits |=3D intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); - mask |=3D intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); - } =20 - cpuc->fixed_ctrl_val &=3D ~mask; + cpuc->fixed_ctrl_val &=3D ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_= MASK); cpuc->fixed_ctrl_val |=3D bits; } =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index f8247ac276c4..49a4d442f3fc 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -35,7 +35,6 @@ #define ARCH_PERFMON_EVENTSEL_EQ (1ULL << 36) #define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40) =20 -#define INTEL_FIXED_BITS_MASK 0xFULL #define INTEL_FIXED_BITS_STRIDE 4 #define INTEL_FIXED_0_KERNEL (1ULL << 0) #define INTEL_FIXED_0_USER (1ULL << 1) @@ -48,6 +47,11 @@ #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) #define ICL_FIXED_0_ADAPTIVE (1ULL << 32) =20 +#define INTEL_FIXED_BITS_MASK \ + (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | \ + INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI | \ + ICL_FIXED_0_ADAPTIVE) + #define intel_fixed_bits_by_idx(_idx, _bits) \ ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE)) =20 diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index ad89d0bd6005..103604c4b33b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -13,7 +13,7 @@ #define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAI= L | \ MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) =20 -/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ +/* retrieve a fixed counter bits out of IA32_FIXED_CTR_CTRL */ #define fixed_ctrl_field(ctrl_reg, idx) \ (((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MAS= K) =20 --=20 2.34.1