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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a21c081sm1956446566b.97.2025.08.11.01.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:04:49 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5 RESEND] ARM: tegra: Add SOCTHERM support on Tegra114 Date: Mon, 11 Aug 2025 11:04:22 +0300 Message-ID: <20250811080422.12300-6-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250811080422.12300-1-clamor95@gmail.com> References: <20250811080422.12300-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SOCTHERM and thermal zones nodes into common Tegra 4 device tree. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 197 +++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 3ee51d7f3935..cb30a7948e19 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include =20 / { @@ -694,6 +695,46 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells =3D <1>; }; =20 + soctherm: thermal-sensor@700e2000 { + compatible =3D "nvidia,tegra114-soctherm"; + reg =3D <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x60006000 0x400>; /* CAR reg_base */ + reg-names =3D "soctherm-reg", "car-reg"; + interrupts =3D , + ; + interrupt-names =3D "thermal", "edp"; + clocks =3D <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + clock-names =3D "tsensor", "soctherm"; + resets =3D <&tegra_car 78>; + reset-names =3D "soctherm"; + + assigned-clocks =3D <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + assigned-clock-rates =3D <500000>, <51000000>; + + assigned-clock-parents =3D <&tegra_car TEGRA114_CLK_CLK_M>, + <&tegra_car TEGRA114_CLK_PLL_P>; + + #thermal-sensor-cells =3D <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority =3D <100>; + nvidia,cpu-throt-percent =3D <80>; + nvidia,gpu-throt-level =3D ; + #cooling-cells =3D <2>; + }; + + throttle_light: light { + nvidia,priority =3D <80>; + nvidia,cpu-throt-percent =3D <50>; + nvidia,gpu-throt-level =3D ; + #cooling-cells =3D <2>; + }; + }; + }; + dfll: clock@70110000 { compatible =3D "nvidia,tegra114-dfll"; reg =3D <0x70110000 0x100>, /* DFLL control */ @@ -858,24 +899,28 @@ cpu0: cpu@0 { clock-names =3D "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; /* FIXME: what's the actual transition time? */ clock-latency =3D <300000>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <1>; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <2>; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a15"; reg =3D <3>; + #cooling-cells =3D <2>; }; }; =20 @@ -888,6 +933,158 @@ pmu { interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; =20 + thermal-zones { + cpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + cpu_throttle_trip: cpu-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpu_balanced_trip: cpu-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_throttle_trip>; + cooling-device =3D <&throttle_heavy 1 1>; + }; + + map1 { + trip =3D <&cpu_balanced_trip>; + cooling-device =3D <&throttle_light 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + mem_throttle_trip: mem-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + mem_balanced_trip: mem-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + gpu_throttle_trip: gpu-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpu_balanced_trip: gpu-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&gpu_throttle_trip>; + cooling-device =3D <&throttle_heavy 1 1>; + }; + + map1 { + trip =3D <&gpu_balanced_trip>; + cooling-device =3D <&throttle_light 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + + thermal-sensors =3D + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature =3D <102000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + + pllx_throttle_trip: pllx-throttle-trip { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + pllx_balanced_trip: pllx-balanced-trip { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible =3D "arm,armv7-timer"; interrupts =3D --=20 2.48.1