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charset="utf-8" Add configurations in devicetree for PCIe1, board related gpios, PMIC regulators, etc for qcs8300-ride platform. Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index e8e382db2b99..bec2905c5d8f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -325,6 +325,23 @@ &pcie0_phy { status =3D "okay"; }; =20 +&pcie1 { + perst-gpios =3D <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -388,6 +405,29 @@ perst-pins { bias-pull-down; }; }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio22"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; }; =20 &uart7 { --=20 2.43.0