From nobody Sun Oct 5 01:49:31 2025 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 952BB21A92F; Mon, 11 Aug 2025 06:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892678; cv=none; b=OlMywI5WTn12fqtn6+Gun17d3kMus7ZgU8ZIPnqtAksY5///9XoGSaC9aQd2rEAOyzGMTsIXF9YqPiYlbP7DLXWdexYwYQXYLn4IDi+d5FJyeEYYsDpE+zH02EZ8cTj50x+A6rcxjWUycOQGnLSt2qRgOGCLbkxFzlFxC5APL24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892678; c=relaxed/simple; bh=wvqy4UJ6IUTFndqB+XoDiJyOKD1YlqbUlQRCilku3zU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m7xYPD8f/KewjLm9yfq2gl/N5X9n7WWiay/OZ4/ea4KPQxRk0LjFLMcMNQGGJkunWFzRM13xf0TuYbltGB5Myq6vJ3ZkK9OQC1pMPxh0+P4ZgQJvcv4x2k4OWMZdsojMTv2KFtV/rhGSPpDOdjOvZS5iMQzACaA67tYtDUf7d+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=EGRzsG7f; arc=none smtp.client-ip=115.124.30.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="EGRzsG7f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892673; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=DZN23X/8T7TOOtz+3clkVBeibPzLGB2AE7hvZ+c8lTI=; b=EGRzsG7foeIaWEDoJ3yy88g2Igmr+oiYKli+1AI6pQoi8NHmUNzmfF4PklComf+JsxtxEB/F4hnY4DfayApGoF3lgpSmn6fLDezYD5bzR4XzPT8+WwLy9+YuDfZ14M5lkvE8hsWYq300Pr6o+Rx9pYEZShwcTO8UTJoMspM1Pqc= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-v89_1754892670 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:11 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 1/6] RISC-V: Add more elements to irqbypass vcpu_info Date: Mon, 11 Aug 2025 14:10:59 +0800 Message-Id: <20250811061104.10326-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu To support MRIF mode, we need to add more elements to let the iommu driver get the ppn of MRIF. Signed-off-by: Fangyu Yu --- arch/riscv/include/asm/irq.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8588667cbb5f..6293ac00e051 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -30,6 +30,9 @@ struct riscv_iommu_vcpu_info { u32 group_index_shift; u64 gpa; u64 hpa; + u32 host_irq; + bool mrif; + struct msi_msg *host_msg; }; =20 #ifdef CONFIG_ACPI --=20 2.49.0 From nobody Sun Oct 5 01:49:31 2025 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0F592D8381; Mon, 11 Aug 2025 06:11:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892686; cv=none; b=V40OL4PBNH9vxpyj2lCV6MahFNWzc5xXu1lC4cUXhcvlYcIMZyi32jY8/HgE7YloZQzPJWzasSDUoCYah0VtqR3XVVLxlZ5sKNGtJmPpRec2Gy98gWwcnj5VA5HN7v6g+hVCUKZ/Of5YuAlyYfz4uKkP/oGuEkDdMsBpPLwr90M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892686; c=relaxed/simple; bh=TykNv5gkgpZAOZDIW+MRRdfsxuTLkyNVFKonDaW4f/Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iOCf4EAQhmKlNDcZEZ68v8/EgbV/hJBXVLH+LJZ+BpgN1nPTJrbkS3vgBLRtQq7vD/YbHaTeihOvJSERw52JlvAfn/t2vbKcNbmBoTOEt3gD0hR5sNh82lg3RwJowOLOfceWIkRPzUdF3vuAnyRgIO8phRidFX9YzuKz+Xhy/Cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=eap5vj5x; arc=none smtp.client-ip=115.124.30.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="eap5vj5x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892677; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=whyJDouuAuGf1j7b/5M2xWcx/VsvP58NxkP1IN3I0Kg=; b=eap5vj5xSFdMsiuuuxLcPgRxyY801HFUQUIvCCqkpAcHYj//JV5cuXJwf5j1YJm0/ee6jEICMpLSj9vYtmzqNDC0P4AsCA++zgDJ/6Xz3bzu8Mt2eGKZZZUxVQMxln1Cgp17Oapr64gInk8k46GeW/MWwpX4zMTNL+eZiutt98A= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-v9-_1754892672 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:13 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 2/6] RISC-V: KVM: Transfer the physical address of MRIF to iommu-ir Date: Mon, 11 Aug 2025 14:11:00 +0800 Message-Id: <20250811061104.10326-3-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu According to the RISC-V IOMMU Spec, an IOMMU may optionally support memory-resident interrupt files (MRIFs). When the guest interrupt files are used up, we transfer the physical address of MRIF to iommu-ir, and enable MRIF mode if the iommu-ir supports. Signed-off-by: Fangyu Yu --- arch/riscv/kvm/aia_imsic.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index 8f5703d9112a..e91164742fd0 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -21,6 +21,8 @@ =20 #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) =20 +static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *vcpu); + struct imsic_mrif_eix { unsigned long eip[BITS_PER_TYPE(u64) / BITS_PER_LONG]; unsigned long eie[BITS_PER_TYPE(u64) / BITS_PER_LONG]; @@ -717,7 +719,8 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *= vcpu) vcpu->arch.aia_context.imsic_addr, IMSIC_MMIO_PAGE_SZ); =20 - /* TODO: Purge the IOMMU mapping ??? */ + /* Update the IOMMU mapping */ + kvm_riscv_vcpu_irq_update(vcpu); =20 /* * At this point, all interrupt producers have been re-directed @@ -795,13 +798,14 @@ int kvm_arch_update_irqfd_routing(struct kvm *kvm, un= signed int host_irq, =20 read_lock_irqsave(&imsic->vsfile_lock, flags); =20 - if (WARN_ON_ONCE(imsic->vsfile_cpu < 0)) { - read_unlock_irqrestore(&imsic->vsfile_lock, flags); - goto out; + if (imsic->vsfile_cpu < 0) { + vcpu_info.hpa =3D imsic->swfile_pa; + vcpu_info.mrif =3D true; + } else { + vcpu_info.hpa =3D imsic->vsfile_pa; + vcpu_info.mrif =3D false; } =20 - vcpu_info.hpa =3D imsic->vsfile_pa; - ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret) { read_unlock_irqrestore(&imsic->vsfile_lock, flags); @@ -844,6 +848,13 @@ static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *= vcpu) if (!irqfd->producer) continue; host_irq =3D irqfd->producer->irq; + + if (imsic->vsfile_cpu < 0) { + vcpu_info.hpa =3D imsic->swfile_pa; + vcpu_info.mrif =3D true; + } else { + vcpu_info.mrif =3D false; + } ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret) { spin_unlock_irq(&kvm->irqfds.lock); --=20 2.49.0 From nobody Sun Oct 5 01:49:31 2025 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CBD42D5C9F; Mon, 11 Aug 2025 06:11:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892685; cv=none; b=WE7ks0ZTTmhDfW3w02MFMupaGsdv6oGpjqG3km3X2n1V+MSK3tB74D8ScvG2CCJ9Kdvbj85O6Zr/5rCwxh9RsUIehFBEFpyiW2dQ05/rkKXb74v44HeAFH5HoxE6/LUMh0Lh78MEqzL5B1L8YuNU681LFVhCgfbXOp2/2gEBZUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892685; c=relaxed/simple; bh=Ov9Ov+ktpF2ZZ1j0AFTGQpIp0s2TcvExe7S1kk/HsVg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P8bVS3IgD7SUFCxEHcogQR/C+MME5VqHfgcegcDXmYU791rx15zjrKgZLjIRgl72PN8hJbF2vd4Q6hcSxyCP5tXGjlNoS4HENsoee/o02iEkeFofBSAGxEestuOyOMFSmrLzF/0EaC8Iasmt4wpzG/6jrvzJgArk6g/0kFvhOmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=BN4UWneN; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="BN4UWneN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892678; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=JlGDH5MhkH4wQ0znvBetGKXo3m7u1SGgHzon2WgQpFY=; b=BN4UWneNvSBPAfLQVEsNVi6RTr6ni+AbqzEFojOj9/pZvyTGsCGuBU3WHlayX7FYcytgrYs7Ysj5F4MDcikB3NOH7laWiYg/38NQizE9/urLKVVV5WyglBP17iizx2d+ebgV6txiBBfY/khZ8k26YW1C8dW3hl6s7pFWSgEMkEo= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-v9j_1754892673 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:14 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 3/6] RISC-V: KVM: Add a xarray to record host irq msg Date: Mon, 11 Aug 2025 14:11:01 +0800 Message-Id: <20250811061104.10326-4-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu In the irq bypass scenario,the host interrupt comes from VFIO, and it is an enabled MSI/MSI-X interrupt. Due to the reconfiguration of the PCI-e BAR space during the irq bypass process,this host irq will not be triggered in the host system. We can use this host irq as a notice MSI in IOMMU MRIF mode. Signed-off-by: Fangyu Yu --- arch/riscv/kvm/aia_imsic.c | 69 +++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index e91164742fd0..58807e68a3dd 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -60,6 +60,9 @@ struct imsic { struct imsic_mrif *swfile; phys_addr_t swfile_pa; raw_spinlock_t swfile_extirq_lock; + + bool mrif_support; + struct xarray hostirq_array; /* Attached host irq array */ }; =20 #define imsic_vs_csr_read(__c) \ @@ -740,6 +743,57 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu = *vcpu) kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei); } =20 +static int kvm_arch_update_irqfd_unset(struct kvm *kvm, unsigned int host_= irq) +{ + struct kvm_vcpu *vcpu; + unsigned long tmp; + + kvm_for_each_vcpu(tmp, vcpu, kvm) { + struct imsic *imsic =3D vcpu->arch.aia_context.imsic_state; + struct msi_msg *curr =3D xa_load(&imsic->hostirq_array, host_irq); + + if (!curr) + continue; + + xa_erase(&imsic->hostirq_array, host_irq); + kfree(curr); + break; + } + + return irq_set_vcpu_affinity(host_irq, NULL); +} + +static struct msi_msg *kvm_arch_update_irqfd_hostirq(struct imsic *imsic, + unsigned int host_irq, int *ret, + struct kvm_kernel_irq_routing_entry *e) +{ + struct msi_msg *priv_msg =3D xa_load(&imsic->hostirq_array, host_irq); + + if (!priv_msg) { + priv_msg =3D kzalloc(sizeof(*priv_msg), GFP_KERNEL); + if (!priv_msg) { + *ret =3D -ENOMEM; + goto out; + } + + struct msi_msg host_msg, *curr; + + get_cached_msi_msg(host_irq, &host_msg); + priv_msg[0] =3D host_msg; + curr =3D xa_cmpxchg(&imsic->hostirq_array, host_irq, + NULL, priv_msg, GFP_ATOMIC); + if (WARN_ON_ONCE(curr)) { + *ret =3D xa_err(curr) ? : -EBUSY; + kfree(priv_msg); + goto out; + } + } + *ret =3D 0; + +out: + return priv_msg; +} + int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set) { @@ -750,7 +804,7 @@ int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsi= gned int host_irq, int idx, ret =3D -ENXIO; =20 if (!set) - return irq_set_vcpu_affinity(host_irq, NULL); + return kvm_arch_update_irqfd_unset(kvm, host_irq); =20 idx =3D srcu_read_lock(&kvm->irq_srcu); irq_rt =3D srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); @@ -795,6 +849,11 @@ int kvm_arch_update_irqfd_routing(struct kvm *kvm, uns= igned int host_irq, =20 vcpu_info.msi_addr_pattern =3D tppn & ~vcpu_info.msi_addr_mask; vcpu_info.gpa =3D target; + vcpu_info.host_irq =3D host_irq; + vcpu_info.host_msg =3D + kvm_arch_update_irqfd_hostirq(imsic, host_irq, &ret, e); + if (ret) + goto out; =20 read_lock_irqsave(&imsic->vsfile_lock, flags); =20 @@ -848,6 +907,10 @@ static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *= vcpu) if (!irqfd->producer) continue; host_irq =3D irqfd->producer->irq; + vcpu_info.host_irq =3D host_irq; + vcpu_info.host_msg =3D xa_load(&imsic->hostirq_array, host_irq); + if (!vcpu_info.host_msg) + continue; =20 if (imsic->vsfile_cpu < 0) { vcpu_info.hpa =3D imsic->swfile_pa; @@ -855,6 +918,7 @@ static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *v= cpu) } else { vcpu_info.mrif =3D false; } + ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret) { spin_unlock_irq(&kvm->irqfds.lock); @@ -1195,6 +1259,9 @@ int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vc= pu) imsic->swfile_pa =3D page_to_phys(swfile_page); raw_spin_lock_init(&imsic->swfile_extirq_lock); =20 + xa_init(&imsic->hostirq_array); + imsic->mrif_support =3D false; + /* Setup IO device */ kvm_iodevice_init(&imsic->iodev, &imsic_iodoev_ops); mutex_lock(&kvm->slots_lock); --=20 2.49.0 From nobody Sun Oct 5 01:49:31 2025 Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A035E29B799; Mon, 11 Aug 2025 06:11:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.111 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892682; cv=none; b=VCUr5P/AvBjv/NCs1ftFGlmsbP4RPrOJT5P91ypdLnm8r2B0+vY8sQU+pyXf078ZsT0gTrjnxipqWgxQIDRt4fFpX4z2m5p8ekA5r7xY/Y9e3+WWLQA8HyBgEkTtDXOcgnRDHE93p3sQ6f61exvvdAXqEl3dtFe7YNnz+1G5Y1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892682; c=relaxed/simple; bh=TfxPrKWVIK1V6hQzQuQJmaaZGOTAE6KC8lUXCNnwxR0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qxtQC2T0sLE0E8JFCWLDt4kMovuPdyQoyJ0KFNQeWvvvd5JKlydVhRyS5QyJYYPmrfMKc4EkuC/Owv0x1sI+3oddPMKbtsn9qb7hAWnkHkrj4WSdbbCSCRBiBhEYnBoU+WpGghMD1f1b07KVsq8FylI+jII1IcQLvh3f6FGDRgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=p7F1FiQj; arc=none smtp.client-ip=115.124.30.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="p7F1FiQj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892677; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=oqEUcnbYtVuGUfumL17PGMuD/BWybgobKSLXaGVbfnQ=; b=p7F1FiQjFVOhBjmJ6tW7ChyiSOJa5ZbWE4VfKrON2zuONDiW2jM4qGc3Ta3Te0NKl7f5y/M+wx5T9oa35PzTdH9LmxViwrIuB/WH1WF+VN3q3Xkwsn2bYerv3+JdvRyMHUQtw4O/VgOFJa4tSwAKSZ/+wo7rYe7OmawYaKEceWk= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-vAP_1754892675 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:16 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 4/6] iommu/riscv: Add irq_mask and irq_ack configure for iommu-ir Date: Mon, 11 Aug 2025 14:11:02 +0800 Message-Id: <20250811061104.10326-5-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu The irq_mask and irq_ack are required for host irq to be triggered under the host system. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-ir.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 5461dbe18159..73f552ed5b65 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -208,6 +208,7 @@ static struct irq_chip riscv_iommu_irq_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_set_affinity =3D irq_chip_set_affinity_parent, .irq_set_vcpu_affinity =3D riscv_iommu_irq_set_vcpu_affinity, + .irq_ack =3D irq_chip_ack_parent, }; =20 static int riscv_iommu_irq_domain_alloc_irqs(struct irq_domain *irqdomain, @@ -239,7 +240,9 @@ static const struct msi_parent_ops riscv_iommu_msi_pare= nt_ops =3D { .supported_flags =3D MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | - MSI_FLAG_USE_DEF_CHIP_OPS, + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, .init_dev_msi_info =3D msi_parent_init_dev_msi_info, }; =20 --=20 2.49.0 From nobody Sun Oct 5 01:49:31 2025 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CC5A2D63E5; Mon, 11 Aug 2025 06:11:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.99 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892684; cv=none; b=BVoy7K+cbgSB6AmPlz6uZVoak2QwKT8H+9cSpfgM16CuDsdaykpa86EGGNVxiSry4Lnek2e5DuPKXlj5hdOebag0fp4xuzl83PJEHjsrhupqDed0CQkwfCHTQnKynoDxqpMIBdT1uUggHI6paoYr3JfqcJz0/dTvGE56fmFU4Bo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892684; c=relaxed/simple; bh=x/6H8FCpaM1P1l+m7yJ/++snzFBZ4yex37yrKVs51rU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CmsPrVTkyCTbby3qs9TwFcL8TAEBxSw+Hz4HFAqKLgLrhMVMp6xs4VlHt3BxryuJVDveZPzoCuFCUWCLD4M4f1SaPWzyDA9ZxkZJLxcNLoeTOSPtnpgyIyjRaKdznOcZXfUHrLYI3jSQ1OqkMDXPAcf/jKLroi+fJRP99kbm7tI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=jrItEsXE; arc=none smtp.client-ip=115.124.30.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="jrItEsXE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892679; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=XDEJbKTMYToe/P3nkdkZb7Pdk39snYZKhujzTlABfAU=; b=jrItEsXEeshys8x7mIsACjcmCpUNC0rrwtNOXCei2hBNjtRZhCtStzqqjGN0Emb1DepMQUs3izVuAbZS126aIDL7FT62MRQkPkjSTKW4/KMl8LEuQo6ghPjvYoCMtIqnjLq8lj9BlttkR/QypoRqxAiot01CmE4pB3MDFDalh2k= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-vAn_1754892676 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:17 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 5/6] iommu/riscv: Add MRIF mode support Date: Mon, 11 Aug 2025 14:11:03 +0800 Message-Id: <20250811061104.10326-6-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu If the guest interrupt files are exhausted and the MRIF is supported we configure the MSI PTE with MRIF mode, and set the NPPN and NID using notice MSI from host irq. Otherwise, we redirect the guest interrupt back to the original host irq and inject the interrupt into the guest machine through irqfd. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 6 ++++++ drivers/iommu/riscv/iommu-ir.c | 35 +++++++++++++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index d3d98dbed709..3af6436d5c5c 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -39,6 +39,12 @@ /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=3D> PPN[53:10] */ #define riscv_iommu_phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << = 10)) #define riscv_iommu_ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << = 12)) +/* RISC-V IOMMU MRIF Address <> PHYS address conversions, PHYS <=3D> MRIF[= 53:7] */ +#define riscv_iommu_phys_to_mrif(pa) (((pa) >> 2) & (((1ULL << 47) - 1) <<= 7)) +/* RISC-V IOMMU nppn <> PHYS address conversions, PHYS <=3D> nppn[53:10] */ +#define riscv_iommu_phys_to_nppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) <<= 10)) +#define riscv_iommu_data_to_nid(data) \ + ((((data) & 0x3FFULL)) | (((((data) >> 10) & 1ULL)) << 60)) =20 /* 5.3 IOMMU Capabilities (64bits) */ #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 73f552ed5b65..f3ebf62de53e 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -150,9 +150,12 @@ static int riscv_iommu_irq_set_vcpu_affinity(struct ir= q_data *data, void *info) { struct riscv_iommu_vcpu_info *vcpu_info =3D info; struct riscv_iommu_domain *domain =3D data->domain->host_data; + struct device *dev =3D msi_desc_to_dev(irq_data_get_msi_desc(data)); + struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_msipte *pte; int ret =3D -EINVAL; - u64 pteval; + u64 pteval, mrifval =3D 0; + bool mrif_support =3D (iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_MRIF); =20 if (WARN_ON(domain->domain.type !=3D IOMMU_DOMAIN_UNMANAGED)) return ret; @@ -186,12 +189,38 @@ static int riscv_iommu_irq_set_vcpu_affinity(struct i= rq_data *data, void *info) if (!pte) goto out_unlock; =20 - pteval =3D FIELD_PREP(RISCV_IOMMU_MSIPTE_M, 3) | - riscv_iommu_phys_to_ppn(vcpu_info->hpa) | + if (!vcpu_info->mrif) { + pteval =3D FIELD_PREP(RISCV_IOMMU_MSIPTE_M, 3) | + riscv_iommu_phys_to_ppn(vcpu_info->hpa) | + FIELD_PREP(RISCV_IOMMU_MSIPTE_V, 1); + goto update_pte; + } + + pteval =3D FIELD_PREP(RISCV_IOMMU_MSIPTE_M, 1) | + riscv_iommu_phys_to_mrif(vcpu_info->hpa) | FIELD_PREP(RISCV_IOMMU_MSIPTE_V, 1); + if (mrif_support) { + mrifval =3D riscv_iommu_data_to_nid(vcpu_info->host_msg->data) | + riscv_iommu_phys_to_nppn( + (u64)vcpu_info->host_msg->address_hi << 32 | + vcpu_info->host_msg->address_lo); + } else { + /* If the guest interrupt file is exhausted and MRIF is not supported, we + * redirect the guest interrupt back to the original host interrupt and + * inject the interrupt into the guest machine through irqfd. + */ + struct irq_data *irqdata =3D irq_get_irq_data(vcpu_info->host_irq); + + irq_data_get_irq_chip(irqdata)->irq_write_msi_msg(irqdata, + vcpu_info->host_msg); + ret =3D -ENODEV; + goto out_unlock; + } =20 +update_pte: if (pte->pte !=3D pteval) { pte->pte =3D pteval; + pte->mrif_info =3D mrifval; riscv_iommu_ir_msitbl_inval(domain, pte); } =20 --=20 2.49.0 From nobody Sun Oct 5 01:49:31 2025 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52C8F2D9484; Mon, 11 Aug 2025 06:11:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892691; cv=none; b=XZFSyY+jCrRBDRXVD/MxzaM9MAX0AnWOu8gBRVL9Z4wpXhMIjMFcPPM4PtbnJnEGgx4IER5Qi4fYOpaAOypmaOIvZuTVWOkW0lnsspH5i0buPNAtiRDLnZ5d95HCwiU8DsQCwhYOXKE/NPMm/ttOlcznK21VmF2Fwr2nGRFBRHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754892691; c=relaxed/simple; bh=D6bWNCnFL2Dw0JQmRi3CW5HbqgQJLdJ91ORdGPwDaLw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cd5odsJIvwiVwqoZ7zvSD1+RU6qrU/kedoUh2GUyRcWhVny8CN00ILgBjapyO5qSBv6XV/5sWvbr3+RJhDmLXUMh2DuIMPtXYD7AWLNmjwgmuJlhmE0NsPo8AsUUirjFlipoP9dZI8u278xQwwR8bC/cOf3y7XGzPJkWcgWJlrU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=CyTu3IFN; arc=none smtp.client-ip=115.124.30.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="CyTu3IFN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1754892680; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=7J/clauWbQWRFTci+97Z7tJgolFj9hSh37VSydzAoWg=; b=CyTu3IFNVUSNNEH0LPWsZxuZhDpPPSIFNs9gYqC3x7Tniy+qJCZqCh0Vw/E/zMMp8DYp5sa1sr6RLT94t9F+5Mb1G/YUzPMqZrGEKFw8PIpFsN7XGVAcQGIuz4bdfdo6QcP4rmNkMFLKMN2E9sBq5Qk4agl4B0Oke0He/RhIDh8= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WlP-vBA_1754892678 cluster:ay36) by smtp.aliyun-inc.com; Mon, 11 Aug 2025 14:11:19 +0800 From: fangyu.yu@linux.alibaba.com To: anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, atishp@atishpatra.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, sunilvl@ventanamicro.com, rafael.j.wysocki@intel.com, tglx@linutronix.de, ajones@ventanamicro.com Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Fangyu Yu Subject: [RFC PATCH 6/6] RISC-V: KVM: Check the MRIF in notice MSI irq handler Date: Mon, 11 Aug 2025 14:11:04 +0800 Message-Id: <20250811061104.10326-7-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> References: <20250811061104.10326-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu In MRIF mode, the Advanced Interrupt Architecture Specification defines the operation to store the incoming MSIs into the MRIF and to generate the notice MSI,the software shold check the MRIF in the notice MSI irq handler. And without MRIF support,we redirect the guest interrupt back to the original host interrupt, the software update and check MRIF in host irq handler. Signed-off-by: Fangyu Yu --- arch/riscv/kvm/aia_imsic.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index 58807e68a3dd..f0d1acde0dd4 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -867,11 +867,16 @@ int kvm_arch_update_irqfd_routing(struct kvm *kvm, un= signed int host_irq, =20 ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret) { + if (ret =3D=3D -ENODEV) { + imsic->mrif_support =3D false; + ret =3D 0; + } read_unlock_irqrestore(&imsic->vsfile_lock, flags); goto out; } =20 - irq_data_get_irq_chip(irqdata)->irq_write_msi_msg(irqdata, msg); + if (imsic->mrif_support) + irq_data_get_irq_chip(irqdata)->irq_write_msi_msg(irqdata, msg); =20 read_unlock_irqrestore(&imsic->vsfile_lock, flags); } @@ -921,6 +926,10 @@ static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *= vcpu) =20 ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret) { + if (ret =3D=3D -ENODEV) { + imsic->mrif_support =3D false; + ret =3D 0; + } spin_unlock_irq(&kvm->irqfds.lock); return ret; } @@ -1182,8 +1191,24 @@ int kvm_riscv_vcpu_aia_imsic_inject(struct kvm_vcpu = *vcpu, if (imsic->vsfile_cpu >=3D 0) { writel(iid, imsic->vsfile_va + IMSIC_MMIO_SETIPNUM_LE); } else { + if (imsic->mrif_support) { + struct msi_msg *msg; + unsigned long idx; + + /* In MRIF mode, the noticed MSI irq handler will call here to + * determine whether the MRIF has been updated.Since the IOMMU + * hardware has updated the MRIF,the software does not need to + * update the MRIF file again. + */ + xa_for_each(&imsic->hostirq_array, idx, msg) { + if (msg->data =3D=3D iid) + goto skip_update_swfile; + } + } eix =3D &imsic->swfile->eix[iid / BITS_PER_TYPE(u64)]; set_bit(iid & (BITS_PER_TYPE(u64) - 1), eix->eip); + +skip_update_swfile: imsic_swfile_extirq_update(vcpu); } =20 @@ -1260,7 +1285,7 @@ int kvm_riscv_vcpu_aia_imsic_init(struct kvm_vcpu *vc= pu) raw_spin_lock_init(&imsic->swfile_extirq_lock); =20 xa_init(&imsic->hostirq_array); - imsic->mrif_support =3D false; + imsic->mrif_support =3D true; =20 /* Setup IO device */ kvm_iodevice_init(&imsic->iodev, &imsic_iodoev_ops); --=20 2.49.0