From nobody Sun Oct 5 03:38:49 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1203720C001; Mon, 11 Aug 2025 02:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; cv=none; b=IBOZ2MfWIcRc7NhrYPj0lJHcpUpwL0zUrRiIY0I9IP1pz2sJIlZaugqi9pkoNq9A/eyI8poC1R4zaejsBuzHO9dG2utxE4wX44NnDG/axL7BG3zSKKadnEZjyrpSU4MNMtJDQn+V2w6H6EQtaPI0Bn9ailYAXpUwxMh/4y3/FKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; c=relaxed/simple; bh=PoWL38fRU5C2OE+S08O2fNPsEzofkJYTBxIivUgIgWY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LzQ1ddTorSttQaSlTDt0herxw1NHxCbW4n/0PrccTYb2L9NWgRZPv2vGBujPGtJJnWs106lx7j0yWe4C4GrAF/RlWnmrjKl+tOLzUsalv9WwE02dtMQRzvlRVxr2PVVLkry3YsTzk2g4PzqauX21XpvXA2X4B/X5YfeVKpwxmG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxquDbUZlopxg+AQ--.12066S3; Mon, 11 Aug 2025 10:13:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S6; Mon, 11 Aug 2025 10:13:47 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] LoongArch: KVM: Add different length support in loongarch_pch_pic_write() Date: Mon, 11 Aug 2025 10:13:43 +0800 Message-Id: <20250811021344.3678306-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With function loongarch_pch_pic_write(), currently there is only four bytes register write support. In theory length 1/2/4/8 should be supported for all the registers, here adding different length support about register write emulation in function loongarch_pch_pic_write(). Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/pch_pic.c | 153 ++++++++++-------------------- 1 file changed, 51 insertions(+), 102 deletions(-) diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 2e2613c436f6..0710b5ab286e 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -77,45 +77,6 @@ void pch_msi_set_irq(struct kvm *kvm, int irq, int level) eiointc_set_irq(kvm->arch.eiointc, irq, level); } =20 -/* - * pch pic register is 64-bit, but it is accessed by 32-bit, - * so we use high to get whether low or high 32 bits we want - * to read. - */ -static u32 pch_pic_read_reg(u64 *s, int high) -{ - u64 val =3D *s; - - /* read the high 32 bits when high is 1 */ - return high ? (u32)(val >> 32) : (u32)val; -} - -/* - * pch pic register is 64-bit, but it is accessed by 32-bit, - * so we use high to get whether low or high 32 bits we want - * to write. - */ -static u32 pch_pic_write_reg(u64 *s, int high, u32 v) -{ - u64 val =3D *s, data =3D v; - - if (high) { - /* - * Clear val high 32 bits - * Write the high 32 bits when the high is 1 - */ - *s =3D (val << 32 >> 32) | (data << 32); - val >>=3D 32; - } else - /* - * Clear val low 32 bits - * Write the low 32 bits when the high is 0 - */ - *s =3D (val >> 32 << 32) | v; - - return (u32)val; -} - static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr,= int len, void *val) { int offset, ret =3D 0; @@ -201,80 +162,68 @@ static int loongarch_pch_pic_write(struct loongarch_p= ch_pic *s, gpa_t addr, int len, const void *val) { int ret; - u32 old, data, offset, index; - u64 irq; + u32 offset; + u64 old, data, mask; + void *ptemp; =20 - ret =3D 0; - data =3D *(u32 *)val; - offset =3D addr - s->pch_pic_base; + switch (len) { + case 1: + data =3D *(u8 *)val; + mask =3D 0xFF; + break; + case 2: + data =3D *(u16 *)val; + mask =3D USHRT_MAX; + break; + case 4: + data =3D *(u32 *)val; + mask =3D UINT_MAX; + break; + default: + data =3D *(u64 *)val; + mask =3D ULONG_MAX; + break; + } =20 + offset =3D (addr - s->pch_pic_base) & 7; + mask =3D mask << (offset * 8); + data =3D data << (offset * 8); + ret =3D 0; + offset =3D (addr - s->pch_pic_base) - offset; spin_lock(&s->lock); switch (offset) { - case PCH_PIC_MASK_START ... PCH_PIC_MASK_END: - offset -=3D PCH_PIC_MASK_START; - /* get whether high or low 32 bits we want to write */ - index =3D offset >> 2; - old =3D pch_pic_write_reg(&s->mask, index, data); - /* enable irq when mask value change to 0 */ - irq =3D (old & ~data) << (32 * index); - pch_pic_update_batch_irqs(s, irq, 1); - /* disable irq when mask value change to 1 */ - irq =3D (~old & data) << (32 * index); - pch_pic_update_batch_irqs(s, irq, 0); - break; - case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END: - offset -=3D PCH_PIC_HTMSI_EN_START; - index =3D offset >> 2; - pch_pic_write_reg(&s->htmsi_en, index, data); + case PCH_PIC_MASK_START: + old =3D s->mask; + s->mask =3D (old & ~mask) | data; + if (old & ~data) + pch_pic_update_batch_irqs(s, old & ~data, 1); + if (~old & data) + pch_pic_update_batch_irqs(s, ~old & data, 0); break; - case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END: - offset -=3D PCH_PIC_EDGE_START; - index =3D offset >> 2; - /* 1: edge triggered, 0: level triggered */ - pch_pic_write_reg(&s->edge, index, data); - break; - case PCH_PIC_CLEAR_START ... PCH_PIC_CLEAR_END: - offset -=3D PCH_PIC_CLEAR_START; - index =3D offset >> 2; - /* write 1 to clear edge irq */ - old =3D pch_pic_read_reg(&s->irr, index); - /* - * get the irq bitmap which is edge triggered and - * already set and to be cleared - */ - irq =3D old & pch_pic_read_reg(&s->edge, index) & data; - /* write irr to the new state where irqs have been cleared */ - pch_pic_write_reg(&s->irr, index, old & ~irq); - /* update cleared irqs */ - pch_pic_update_batch_irqs(s, irq, 0); + case PCH_PIC_HTMSI_EN_START: + s->htmsi_en =3D (s->htmsi_en & ~mask) | data; break; - case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END: - offset -=3D PCH_PIC_AUTO_CTRL0_START; - index =3D offset >> 2; - /* we only use default mode: fixed interrupt distribution mode */ - pch_pic_write_reg(&s->auto_ctrl0, index, 0); + case PCH_PIC_EDGE_START: + s->edge =3D (s->edge & ~mask) | data; break; - case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END: - offset -=3D PCH_PIC_AUTO_CTRL1_START; - index =3D offset >> 2; - /* we only use default mode: fixed interrupt distribution mode */ - pch_pic_write_reg(&s->auto_ctrl1, index, 0); + case PCH_PIC_POLARITY_START: + s->polarity =3D (s->polarity & ~mask) | data; break; - case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END: - offset -=3D PCH_PIC_ROUTE_ENTRY_START; - /* only route to int0: eiointc */ - s->route_entry[offset] =3D 1; + case PCH_PIC_CLEAR_START: + old =3D s->irr & s->edge & data; + if (old) { + s->irr &=3D ~old; + pch_pic_update_batch_irqs(s, old, 0); + } break; case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END: - /* route table to eiointc */ - offset -=3D PCH_PIC_HTMSI_VEC_START; - s->htmsi_vector[offset] =3D (u8)data; + ptemp =3D s->htmsi_vector + (offset - PCH_PIC_HTMSI_VEC_START); + *(u64 *)ptemp =3D (*(u64 *)ptemp & ~mask) | data; break; - case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END: - offset -=3D PCH_PIC_POLARITY_START; - index =3D offset >> 2; - /* we only use defalut value 0: high level triggered */ - pch_pic_write_reg(&s->polarity, index, 0); + /* Not implemented */ + case PCH_PIC_AUTO_CTRL0_START: + case PCH_PIC_AUTO_CTRL1_START: + case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END: break; default: ret =3D -EINVAL; --=20 2.39.3