From nobody Sun Oct 5 01:51:59 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 780B257C9F; Mon, 11 Aug 2025 02:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878438; cv=none; b=uqUKBnmCn4CEaNh1YXIJogQTnC/USyAXOwvGi063Y0cNuNRRCTSxCqJIlVlD8VAqaNJXVwSltAShNk8FHbdx4pnfMpmG9UkLqsjPUJvx+PTd9krSoU1vIMyElOFmWBplxh5xUol6ebfZYo2AWJfjDU+OkoyJftF6Je49Hbl7kq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878438; c=relaxed/simple; bh=WG6yIOZUAT/D/HhjVb6MFrB/X8K8IjW1AFFtDlQJeJA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BgskU3u+lbQSHwLvgLOF0vk2JBE2RPymt+ueAPy5klDIRMs2FvH/Kown2uWM4vtnTeQ96vEj6Qqv02uQVR8zc8thjcMZKJRZ8rdJ7mXTkdPDU0CCd0ypdI0nyKGdllkQo7M+X0XloEroEtJl7ousqcs+pwCfP51y6u6b0tuT1EY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxrOLaUZlonBg+AQ--.11514S3; Mon, 11 Aug 2025 10:13:46 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S3; Mon, 11 Aug 2025 10:13:45 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] LoongArch: KVM: Set version information at initial stage Date: Mon, 11 Aug 2025 10:13:40 +0800 Message-Id: <20250811021344.3678306-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Register PCH_PIC_INT_ID constains version and supported irq number information, and it is read only register. The detailed value can be set at initial stage, rather than read callback. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_pch_pic.h | 15 +++++++++++- arch/loongarch/kvm/intc/pch_pic.c | 30 +++++++++++++++++------- 2 files changed, 35 insertions(+), 10 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_pch_pic.h b/arch/loongarch/incl= ude/asm/kvm_pch_pic.h index e6df6a4c1c70..3228db8f84a3 100644 --- a/arch/loongarch/include/asm/kvm_pch_pic.h +++ b/arch/loongarch/include/asm/kvm_pch_pic.h @@ -34,13 +34,26 @@ #define PCH_PIC_INT_ISR_END 0x3af #define PCH_PIC_POLARITY_START 0x3e0 #define PCH_PIC_POLARITY_END 0x3e7 -#define PCH_PIC_INT_ID_VAL 0x7000000UL +#define PCH_PIC_INT_ID_VAL 0x7UL #define PCH_PIC_INT_ID_VER 0x1UL =20 +union LoongArchPIC_ID { + struct { + uint8_t _reserved_0[3]; + uint8_t id; + uint8_t version; + uint8_t _reserved_1; + uint8_t irq_num; + uint8_t _reserved_2; + } desc; + uint64_t data; +}; + struct loongarch_pch_pic { spinlock_t lock; struct kvm *kvm; struct kvm_io_device device; + union LoongArchPIC_ID id; uint64_t mask; /* 1:disable irq, 0:enable irq */ uint64_t htmsi_en; /* 1:msi */ uint64_t edge; /* 1:edge triggered, 0:level triggered */ diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 6f00ffe05c54..2c26c0836a05 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -120,20 +120,13 @@ static int loongarch_pch_pic_read(struct loongarch_pc= h_pic *s, gpa_t addr, int l { int offset, index, ret =3D 0; u32 data =3D 0; - u64 int_id =3D 0; =20 offset =3D addr - s->pch_pic_base; =20 spin_lock(&s->lock); switch (offset) { case PCH_PIC_INT_ID_START ... PCH_PIC_INT_ID_END: - /* int id version */ - int_id |=3D (u64)PCH_PIC_INT_ID_VER << 32; - /* irq number */ - int_id |=3D (u64)31 << (32 + 16); - /* int id value */ - int_id |=3D PCH_PIC_INT_ID_VAL; - *(u64 *)val =3D int_id; + *(u64 *)val =3D s->id.data; break; case PCH_PIC_MASK_START ... PCH_PIC_MASK_END: offset -=3D PCH_PIC_MASK_START; @@ -467,7 +460,7 @@ static int kvm_setup_default_irq_routing(struct kvm *kv= m) =20 static int kvm_pch_pic_create(struct kvm_device *dev, u32 type) { - int ret; + int ret, i, irq_num; struct kvm *kvm =3D dev->kvm; struct loongarch_pch_pic *s; =20 @@ -483,6 +476,25 @@ static int kvm_pch_pic_create(struct kvm_device *dev, = u32 type) if (!s) return -ENOMEM; =20 + /* + * With Loongson 7A1000 user manual + * Chapter 5.2 "Description of Interrupt-related Registers" + * + * Interrupt controller identification register 1 + * Bit 24-31 Interrupt Controller ID + * Interrupt controller identification register 2 + * Bit 0-7 Interrupt Controller version number + * Bit 16-23 The number of interrupt sources supported + */ + irq_num =3D 32; + s->id.desc.id =3D PCH_PIC_INT_ID_VAL; + s->id.desc.version =3D PCH_PIC_INT_ID_VER; + s->id.desc.irq_num =3D irq_num - 1; + s->mask =3D -1UL; + for (i =3D 0; i < irq_num; i++) { + s->route_entry[i] =3D 1; + s->htmsi_vector[i] =3D i; + } spin_lock_init(&s->lock); s->kvm =3D kvm; kvm->arch.pch_pic =3D s; --=20 2.39.3 From nobody Sun Oct 5 01:51:59 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5C16C2566F5; Mon, 11 Aug 2025 02:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878440; cv=none; b=F6KNvuNgf2eimmfqjmDVDYQ0nRBxSz3TjHTQFSn5gK6oxrXQKYpTVuPh9Frm9ogczCX5zpZ1mCihwKUHtfa1R3a0c8Ngah2AW7pv0jgSmVVEXCr9NA+a2euIgim4e52/n9uMk09ku3LJFJ6vXu+It1imVVtTQze3IK7abAOFpwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878440; c=relaxed/simple; bh=yhCPk/afV0DT8k1q58coV6ibSQtTlsNl6zwwhFxWqi0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RVrKiuI0VMxCAjsV4soMqE5A/EecqmTO34ttRl+XQwGrdj3IVf30bhy8LhDvFfeZ22iRziciEKX+ITo6KxvfqGubZ/t/AIZYlenXHYd6k/jrOyMdcJM0EXITq/KsFzD9eoFvx+qIbL9133kCx8zJgu8hrmKEkYgArSdERXm/oEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxQK3aUZlooBg+AQ--.35201S3; Mon, 11 Aug 2025 10:13:46 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S4; Mon, 11 Aug 2025 10:13:46 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] LoongArch: KVM: Add read length support in loongarch_pch_pic_read() Date: Mon, 11 Aug 2025 10:13:41 +0800 Message-Id: <20250811021344.3678306-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With function loongarch_pch_pic_read(), currently it is hardcoded length for different registers, the length comes from exising linux pch_pic driver code. In theory length 1/2/4/8 should be supported for all the registers, here adding different length support about register read emulation in function loongarch_pch_pic_read(). Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/pch_pic.c | 42 ++++++++++++++----------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 2c26c0836a05..70b8cbeea869 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -118,61 +118,57 @@ static u32 pch_pic_write_reg(u64 *s, int high, u32 v) =20 static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr,= int len, void *val) { - int offset, index, ret =3D 0; - u32 data =3D 0; + int offset, ret =3D 0; + u64 data =3D 0; + void *ptemp; =20 offset =3D addr - s->pch_pic_base; + offset -=3D offset & 7; =20 spin_lock(&s->lock); switch (offset) { case PCH_PIC_INT_ID_START ... PCH_PIC_INT_ID_END: - *(u64 *)val =3D s->id.data; + data =3D s->id.data; break; case PCH_PIC_MASK_START ... PCH_PIC_MASK_END: - offset -=3D PCH_PIC_MASK_START; - index =3D offset >> 2; - /* read mask reg */ - data =3D pch_pic_read_reg(&s->mask, index); - *(u32 *)val =3D data; + data =3D s->mask; break; case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END: - offset -=3D PCH_PIC_HTMSI_EN_START; - index =3D offset >> 2; /* read htmsi enable reg */ - data =3D pch_pic_read_reg(&s->htmsi_en, index); - *(u32 *)val =3D data; + data =3D s->htmsi_en; break; case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END: - offset -=3D PCH_PIC_EDGE_START; - index =3D offset >> 2; /* read edge enable reg */ - data =3D pch_pic_read_reg(&s->edge, index); - *(u32 *)val =3D data; + data =3D s->edge; break; case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END: case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END: /* we only use default mode: fixed interrupt distribution mode */ - *(u32 *)val =3D 0; break; case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END: /* only route to int0: eiointc */ - *(u8 *)val =3D 1; + ptemp =3D s->route_entry + (offset - PCH_PIC_ROUTE_ENTRY_START); + data =3D *(u64 *)ptemp; break; case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END: - offset -=3D PCH_PIC_HTMSI_VEC_START; /* read htmsi vector */ - data =3D s->htmsi_vector[offset]; - *(u8 *)val =3D data; + ptemp =3D s->htmsi_vector + (offset - PCH_PIC_HTMSI_VEC_START); + data =3D *(u64 *)ptemp; break; case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END: - /* we only use defalut value 0: high level triggered */ - *(u32 *)val =3D 0; + data =3D s->polarity; break; default: ret =3D -EINVAL; } spin_unlock(&s->lock); =20 + if (ret) + return ret; + + offset =3D (addr - s->pch_pic_base) & 7; + data =3D data >> (offset * 8); + memcpy(val, &data, len); return ret; } =20 --=20 2.39.3 From nobody Sun Oct 5 01:51:59 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1208F21D3F8; Mon, 11 Aug 2025 02:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; cv=none; b=Ygeu6ni4dNAUGjIzASZx/BGnUpJLf2mO1KZ5+B5AJgt4WogIQ0+eoeHnCU4MMgXnHxFn01QASSF4beAy4n5eUXKB6ENr8HMWeWn8k7+iD5FuX1Rm+2R9/ialTpoOoFtHhLXVEQkLgQeMW0dCuj4RM/Jsr1O5iCOfn/S0hd++27w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; c=relaxed/simple; bh=7vAkJtKo3FveG5MTxuL5gAc7sv8e8abfVuekYqY2PPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CrRlw4VqW7eWB+EQXGjtMhoZHuaPzBud9xojBf0MjGruiouqptC4URSnkpPz9HMINUecUAzSXXsxdyh1u6b3srzmB3JuZ2xgbJAKFEUvzXXtvMAb8oB7k9ZkDfUU4Set/jFwbJDj0/3us2A6gz6ROBp9mSzkrU/j0p1PJPYsm5E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxYa_bUZlooxg+AQ--.12809S3; Mon, 11 Aug 2025 10:13:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S5; Mon, 11 Aug 2025 10:13:46 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] LoongArch: KVM: Add IRR and ISR register read emulation Date: Mon, 11 Aug 2025 10:13:42 +0800 Message-Id: <20250811021344.3678306-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With 7A1000 user manual, there is register PCH_PIC_INT_IRR_START and PCH_PIC_INT_ISR_START, add read access emulation in function loongarch_pch_pic_read() here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/pch_pic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 70b8cbeea869..2e2613c436f6 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -158,6 +158,12 @@ static int loongarch_pch_pic_read(struct loongarch_pch= _pic *s, gpa_t addr, int l case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END: data =3D s->polarity; break; + case PCH_PIC_INT_IRR_START: + data =3D s->irr; + break; + case PCH_PIC_INT_ISR_START: + data =3D s->isr; + break; default: ret =3D -EINVAL; } --=20 2.39.3 From nobody Sun Oct 5 01:51:59 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1203720C001; Mon, 11 Aug 2025 02:13:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; cv=none; b=IBOZ2MfWIcRc7NhrYPj0lJHcpUpwL0zUrRiIY0I9IP1pz2sJIlZaugqi9pkoNq9A/eyI8poC1R4zaejsBuzHO9dG2utxE4wX44NnDG/axL7BG3zSKKadnEZjyrpSU4MNMtJDQn+V2w6H6EQtaPI0Bn9ailYAXpUwxMh/4y3/FKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878439; c=relaxed/simple; bh=PoWL38fRU5C2OE+S08O2fNPsEzofkJYTBxIivUgIgWY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LzQ1ddTorSttQaSlTDt0herxw1NHxCbW4n/0PrccTYb2L9NWgRZPv2vGBujPGtJJnWs106lx7j0yWe4C4GrAF/RlWnmrjKl+tOLzUsalv9WwE02dtMQRzvlRVxr2PVVLkry3YsTzk2g4PzqauX21XpvXA2X4B/X5YfeVKpwxmG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxquDbUZlopxg+AQ--.12066S3; Mon, 11 Aug 2025 10:13:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S6; Mon, 11 Aug 2025 10:13:47 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] LoongArch: KVM: Add different length support in loongarch_pch_pic_write() Date: Mon, 11 Aug 2025 10:13:43 +0800 Message-Id: <20250811021344.3678306-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With function loongarch_pch_pic_write(), currently there is only four bytes register write support. In theory length 1/2/4/8 should be supported for all the registers, here adding different length support about register write emulation in function loongarch_pch_pic_write(). Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/pch_pic.c | 153 ++++++++++-------------------- 1 file changed, 51 insertions(+), 102 deletions(-) diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 2e2613c436f6..0710b5ab286e 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -77,45 +77,6 @@ void pch_msi_set_irq(struct kvm *kvm, int irq, int level) eiointc_set_irq(kvm->arch.eiointc, irq, level); } =20 -/* - * pch pic register is 64-bit, but it is accessed by 32-bit, - * so we use high to get whether low or high 32 bits we want - * to read. - */ -static u32 pch_pic_read_reg(u64 *s, int high) -{ - u64 val =3D *s; - - /* read the high 32 bits when high is 1 */ - return high ? (u32)(val >> 32) : (u32)val; -} - -/* - * pch pic register is 64-bit, but it is accessed by 32-bit, - * so we use high to get whether low or high 32 bits we want - * to write. - */ -static u32 pch_pic_write_reg(u64 *s, int high, u32 v) -{ - u64 val =3D *s, data =3D v; - - if (high) { - /* - * Clear val high 32 bits - * Write the high 32 bits when the high is 1 - */ - *s =3D (val << 32 >> 32) | (data << 32); - val >>=3D 32; - } else - /* - * Clear val low 32 bits - * Write the low 32 bits when the high is 0 - */ - *s =3D (val >> 32 << 32) | v; - - return (u32)val; -} - static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr,= int len, void *val) { int offset, ret =3D 0; @@ -201,80 +162,68 @@ static int loongarch_pch_pic_write(struct loongarch_p= ch_pic *s, gpa_t addr, int len, const void *val) { int ret; - u32 old, data, offset, index; - u64 irq; + u32 offset; + u64 old, data, mask; + void *ptemp; =20 - ret =3D 0; - data =3D *(u32 *)val; - offset =3D addr - s->pch_pic_base; + switch (len) { + case 1: + data =3D *(u8 *)val; + mask =3D 0xFF; + break; + case 2: + data =3D *(u16 *)val; + mask =3D USHRT_MAX; + break; + case 4: + data =3D *(u32 *)val; + mask =3D UINT_MAX; + break; + default: + data =3D *(u64 *)val; + mask =3D ULONG_MAX; + break; + } =20 + offset =3D (addr - s->pch_pic_base) & 7; + mask =3D mask << (offset * 8); + data =3D data << (offset * 8); + ret =3D 0; + offset =3D (addr - s->pch_pic_base) - offset; spin_lock(&s->lock); switch (offset) { - case PCH_PIC_MASK_START ... PCH_PIC_MASK_END: - offset -=3D PCH_PIC_MASK_START; - /* get whether high or low 32 bits we want to write */ - index =3D offset >> 2; - old =3D pch_pic_write_reg(&s->mask, index, data); - /* enable irq when mask value change to 0 */ - irq =3D (old & ~data) << (32 * index); - pch_pic_update_batch_irqs(s, irq, 1); - /* disable irq when mask value change to 1 */ - irq =3D (~old & data) << (32 * index); - pch_pic_update_batch_irqs(s, irq, 0); - break; - case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END: - offset -=3D PCH_PIC_HTMSI_EN_START; - index =3D offset >> 2; - pch_pic_write_reg(&s->htmsi_en, index, data); + case PCH_PIC_MASK_START: + old =3D s->mask; + s->mask =3D (old & ~mask) | data; + if (old & ~data) + pch_pic_update_batch_irqs(s, old & ~data, 1); + if (~old & data) + pch_pic_update_batch_irqs(s, ~old & data, 0); break; - case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END: - offset -=3D PCH_PIC_EDGE_START; - index =3D offset >> 2; - /* 1: edge triggered, 0: level triggered */ - pch_pic_write_reg(&s->edge, index, data); - break; - case PCH_PIC_CLEAR_START ... PCH_PIC_CLEAR_END: - offset -=3D PCH_PIC_CLEAR_START; - index =3D offset >> 2; - /* write 1 to clear edge irq */ - old =3D pch_pic_read_reg(&s->irr, index); - /* - * get the irq bitmap which is edge triggered and - * already set and to be cleared - */ - irq =3D old & pch_pic_read_reg(&s->edge, index) & data; - /* write irr to the new state where irqs have been cleared */ - pch_pic_write_reg(&s->irr, index, old & ~irq); - /* update cleared irqs */ - pch_pic_update_batch_irqs(s, irq, 0); + case PCH_PIC_HTMSI_EN_START: + s->htmsi_en =3D (s->htmsi_en & ~mask) | data; break; - case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END: - offset -=3D PCH_PIC_AUTO_CTRL0_START; - index =3D offset >> 2; - /* we only use default mode: fixed interrupt distribution mode */ - pch_pic_write_reg(&s->auto_ctrl0, index, 0); + case PCH_PIC_EDGE_START: + s->edge =3D (s->edge & ~mask) | data; break; - case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END: - offset -=3D PCH_PIC_AUTO_CTRL1_START; - index =3D offset >> 2; - /* we only use default mode: fixed interrupt distribution mode */ - pch_pic_write_reg(&s->auto_ctrl1, index, 0); + case PCH_PIC_POLARITY_START: + s->polarity =3D (s->polarity & ~mask) | data; break; - case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END: - offset -=3D PCH_PIC_ROUTE_ENTRY_START; - /* only route to int0: eiointc */ - s->route_entry[offset] =3D 1; + case PCH_PIC_CLEAR_START: + old =3D s->irr & s->edge & data; + if (old) { + s->irr &=3D ~old; + pch_pic_update_batch_irqs(s, old, 0); + } break; case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END: - /* route table to eiointc */ - offset -=3D PCH_PIC_HTMSI_VEC_START; - s->htmsi_vector[offset] =3D (u8)data; + ptemp =3D s->htmsi_vector + (offset - PCH_PIC_HTMSI_VEC_START); + *(u64 *)ptemp =3D (*(u64 *)ptemp & ~mask) | data; break; - case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END: - offset -=3D PCH_PIC_POLARITY_START; - index =3D offset >> 2; - /* we only use defalut value 0: high level triggered */ - pch_pic_write_reg(&s->polarity, index, 0); + /* Not implemented */ + case PCH_PIC_AUTO_CTRL0_START: + case PCH_PIC_AUTO_CTRL1_START: + case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END: break; default: ret =3D -EINVAL; --=20 2.39.3 From nobody Sun Oct 5 01:51:59 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 730C62580CF; Mon, 11 Aug 2025 02:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878440; cv=none; b=FnzelPVEJkumuHXng1lPXBuIM7qdFrSBWqv6UDq53AGdml2wANB5XwDomQJvOQiWaIhbePg4ZLwXjhZxV/1b07mTr6ejjIt9ntkOwHf+Q4UA0PjVaSM8I62C9md8ohkxA7MZcwJKQ1Bit/xENg4jqsARbAMtUJVnhC3VCL2i2ic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754878440; c=relaxed/simple; bh=R3ZYPelq7B2wOcscDEbwM8RdfSfF7asWSOgJ1o3wNwQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lGXx+D202moRaEkCd2X/9jdOs/Bbmbp8Zf2tilvw/7ve95e3SKwd/9ZimdlbI6k/k9f8M7dJ9G3hadi0bS5l3dJjSKoEkEGzwpEmXlS+WHCXGbSy1dCtmph0/wqyfPVgiA8iQuDMIpW4KOSA0htOdaq0kG4lhSMRaz/pcxZRMdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxlnDcUZlorBg+AQ--.51719S3; Mon, 11 Aug 2025 10:13:48 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxQ+TYUZloMZtBAA--.48509S7; Mon, 11 Aug 2025 10:13:47 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] LoongArch: KVM: Add address alignment check in pch_pic register access Date: Mon, 11 Aug 2025 10:13:44 +0800 Message-Id: <20250811021344.3678306-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250811021344.3678306-1-maobibo@loongson.cn> References: <20250811021344.3678306-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxQ+TYUZloMZtBAA--.48509S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With pch_pic device, its register is based on MMIO address space, different access size 1/2/4/8 is supported. And base address should be naturally aligned with its access size, here add alignment check in its register access emulation function. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/pch_pic.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 0710b5ab286e..5ee24dbf3c4c 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -151,6 +151,11 @@ static int kvm_pch_pic_read(struct kvm_vcpu *vcpu, return -EINVAL; } =20 + if (addr & (len - 1)) { + kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, le= n); + return -EINVAL; + } + /* statistics of pch pic reading */ vcpu->stat.pch_pic_read_exits++; ret =3D loongarch_pch_pic_read(s, addr, len, val); @@ -246,6 +251,11 @@ static int kvm_pch_pic_write(struct kvm_vcpu *vcpu, return -EINVAL; } =20 + if (addr & (len - 1)) { + kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, le= n); + return -EINVAL; + } + /* statistics of pch pic writing */ vcpu->stat.pch_pic_write_exits++; ret =3D loongarch_pch_pic_write(s, addr, len, val); --=20 2.39.3