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Mon, 11 Aug 2025 21:40:44 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 5142891819712798634 EX-QQ-RecipientCnt: 16 From: Troy Mitchell Date: Mon, 11 Aug 2025 21:40:34 +0800 Subject: [PATCH v5 2/2] clk: spacemit: fix sspax_clk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-k1-clk-i2s-v5-2-ebadd06e1e91@linux.spacemit.com> References: <20250811-k1-clk-i2s-v5-0-ebadd06e1e91@linux.spacemit.com> In-Reply-To: <20250811-k1-clk-i2s-v5-0-ebadd06e1e91@linux.spacemit.com> To: Michael Turquette , Stephen Boyd , Yixun Lan , Alex Elder , Haylen Chu , Inochi Amaoto , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Troy Mitchell , Yao Zi X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC= ") Suggested-by: Yao Zi Reviewed-by: Haylen Chu Signed-off-by: Troy Mitchell --- drivers/clk/spacemit/ccu-k1.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 65e6de030717afa60eefab7bda88f9a13b857650..62cdba516a29f960e15e0464247= 0f55e3d85bfad 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -247,7 +247,14 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), = APBC_AIB_CLK_RST, BIT(1), =20 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK= _RST, BIT(1), 0); =20 -static const struct clk_parent_data sspa_parents[] =3D { +/* + * When i2s_bclk is selected as the parent clock of sspa, + * the hardware requires bit3 to be set + */ +CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RS= T, BIT(3), 0); +CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RS= T, BIT(3), 0); + +static const struct clk_parent_data sspa0_parents[] =3D { CCU_PARENT_HW(pll1_d384_6p4), CCU_PARENT_HW(pll1_d192_12p8), CCU_PARENT_HW(pll1_d96_25p6), @@ -255,10 +262,22 @@ static const struct clk_parent_data sspa_parents[] = =3D { CCU_PARENT_HW(pll1_d768_3p2), CCU_PARENT_HW(pll1_d1536_1p6), CCU_PARENT_HW(pll1_d3072_0p8), - CCU_PARENT_HW(i2s_bclk), + CCU_PARENT_HW(sspa0_i2s_bclk), }; -CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT= (1), 0); -CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT= (1), 0); +CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BI= T(1), 0); + +static const struct clk_parent_data sspa1_parents[] =3D { + CCU_PARENT_HW(pll1_d384_6p4), + CCU_PARENT_HW(pll1_d192_12p8), + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(pll1_d48_51p2), + CCU_PARENT_HW(pll1_d768_3p2), + CCU_PARENT_HW(pll1_d1536_1p6), + CCU_PARENT_HW(pll1_d3072_0p8), + CCU_PARENT_HW(sspa1_i2s_bclk), +}; +CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BI= T(1), 0); + CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1),= 0); CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0= ); CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1= ), 0); @@ -865,6 +884,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] =3D { [CLK_SSPA1_BUS] =3D &sspa1_bus_clk.common.hw, [CLK_TSEN_BUS] =3D &tsen_bus_clk.common.hw, [CLK_IPC_AP2AUD_BUS] =3D &ipc_ap2aud_bus_clk.common.hw, + [CLK_SSPA0_I2S_BCLK] =3D &sspa0_i2s_bclk.common.hw, + [CLK_SSPA1_I2S_BCLK] =3D &sspa1_i2s_bclk.common.hw, }; =20 static const struct spacemit_ccu_data k1_ccu_apbc_data =3D { --=20 2.50.1