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Mon, 11 Aug 2025 08:02:07 -0700 (PDT) From: Bartosz Golaszewski Date: Mon, 11 Aug 2025 17:02:00 +0200 Subject: [PATCH 1/5] pinctrl: stm32: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-gpio-mmio-pinctrl-conv-v1-1-a84c5da2be20@linaro.org> References: <20250811-gpio-mmio-pinctrl-conv-v1-0-a84c5da2be20@linaro.org> In-Reply-To: <20250811-gpio-mmio-pinctrl-conv-v1-0-a84c5da2be20@linaro.org> To: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , Linus Walleij , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Cc: linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/stm32/pinctrl-stm32-hdp.c | 32 ++++++++++++++++++---------= ---- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c b/drivers/pinctrl/st= m32/pinctrl-stm32-hdp.c index e91442eb566bb21f7691fa14fcf684957eb6549b..dea49b9aabf2aebbaaa3cb33c8a= dd9926972ed9f 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32-hdp.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -45,7 +46,7 @@ struct stm32_hdp { void __iomem *base; struct clk *clk; struct pinctrl_dev *pctl_dev; - struct gpio_chip gpio_chip; + struct gpio_generic_chip gpio_chip; u32 mux_conf; u32 gposet_conf; const char * const *func_name; @@ -603,6 +604,7 @@ MODULE_DEVICE_TABLE(of, stm32_hdp_of_match); =20 static int stm32_hdp_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct stm32_hdp *hdp; u8 version; @@ -635,21 +637,25 @@ static int stm32_hdp_probe(struct platform_device *pd= ev) if (err) return dev_err_probe(dev, err, "Failed to enable pinctrl\n"); =20 - hdp->gpio_chip.get_direction =3D stm32_hdp_gpio_get_direction; - hdp->gpio_chip.ngpio =3D ARRAY_SIZE(stm32_hdp_pins); - hdp->gpio_chip.can_sleep =3D true; - hdp->gpio_chip.names =3D stm32_hdp_pins_group; + hdp->gpio_chip.gc.get_direction =3D stm32_hdp_gpio_get_direction; + hdp->gpio_chip.gc.ngpio =3D ARRAY_SIZE(stm32_hdp_pins); + hdp->gpio_chip.gc.can_sleep =3D true; + hdp->gpio_chip.gc.names =3D stm32_hdp_pins_group; =20 - err =3D bgpio_init(&hdp->gpio_chip, dev, 4, - hdp->base + HDP_GPOVAL, - hdp->base + HDP_GPOSET, - hdp->base + HDP_GPOCLR, - NULL, NULL, BGPIOF_NO_INPUT); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D hdp->base + HDP_GPOVAL, + .set =3D hdp->base + HDP_GPOSET, + .clr =3D hdp->base + HDP_GPOCLR, + .flags =3D BGPIOF_NO_INPUT, + }; + + err =3D gpio_generic_chip_init(&hdp->gpio_chip, &config); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/pinctrl-equilibrium.c | 26 ++++++++++++++++---------- drivers/pinctrl/pinctrl-equilibrium.h | 2 +- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctr= l-equilibrium.c index fce804d42e7d7f9233b2da0fb26e482170629424..210044185679384d03278e200d8= f7723324487cd 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -2,6 +2,7 @@ /* Copyright (C) 2019 Intel Corporation */ =20 #include +#include #include #include #include @@ -179,7 +180,7 @@ static int gpiochip_setup(struct device *dev, struct eq= br_gpio_ctrl *gctrl) struct gpio_irq_chip *girq; struct gpio_chip *gc; =20 - gc =3D &gctrl->chip; + gc =3D &gctrl->chip.gc; gc->label =3D gctrl->name; gc->fwnode =3D gctrl->fwnode; gc->request =3D gpiochip_generic_request; @@ -191,7 +192,7 @@ static int gpiochip_setup(struct device *dev, struct eq= br_gpio_ctrl *gctrl) return 0; } =20 - girq =3D &gctrl->chip.irq; + girq =3D &gctrl->chip.gc.irq; gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); girq->parent_handler =3D eqbr_irq_handler; girq->num_parents =3D 1; @@ -208,6 +209,7 @@ static int gpiochip_setup(struct device *dev, struct eq= br_gpio_ctrl *gctrl) =20 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata) { + struct gpio_generic_chip_config config; struct device *dev =3D drvdata->dev; struct eqbr_gpio_ctrl *gctrl; struct device_node *np; @@ -239,12 +241,16 @@ static int gpiolib_reg(struct eqbr_pinctrl_drv_data *= drvdata) } raw_spin_lock_init(&gctrl->lock); =20 - ret =3D bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8, - gctrl->membase + GPIO_IN, - gctrl->membase + GPIO_OUTSET, - gctrl->membase + GPIO_OUTCLR, - gctrl->membase + GPIO_DIR, - NULL, 0); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D gctrl->bank->nr_pins / 8, + .dat =3D gctrl->membase + GPIO_IN, + .set =3D gctrl->membase + GPIO_OUTSET, + .clr =3D gctrl->membase + GPIO_OUTCLR, + .dirout =3D gctrl->membase + GPIO_DIR, + }; + + ret =3D gpio_generic_chip_init(&gctrl->chip, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; @@ -254,7 +260,7 @@ static int gpiolib_reg(struct eqbr_pinctrl_drv_data *dr= vdata) if (ret) return ret; =20 - ret =3D devm_gpiochip_add_data(dev, &gctrl->chip, gctrl); + ret =3D devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); if (ret) return ret; } @@ -499,7 +505,7 @@ static int eqbr_pinconf_set(struct pinctrl_dev *pctldev= , unsigned int pin, bank->pin_base, pin); return -ENODEV; } - gc =3D &gctrl->chip; + gc =3D &gctrl->chip.gc; gc->direction_output(gc, offset, 0); continue; default: diff --git a/drivers/pinctrl/pinctrl-equilibrium.h b/drivers/pinctrl/pinctr= l-equilibrium.h index b4d149bde39d8dd08a962bb05ccf026364dd9f68..b56124d7fe9132c875d2768b0af= 8b939f1a4fbf8 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.h +++ b/drivers/pinctrl/pinctrl-equilibrium.h @@ -96,7 +96,7 @@ struct fwnode_handle; * @lock: spin lock to protect gpio register write. */ struct eqbr_gpio_ctrl { - struct gpio_chip chip; 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Mon, 11 Aug 2025 08:02:10 -0700 (PDT) From: Bartosz Golaszewski Date: Mon, 11 Aug 2025 17:02:02 +0200 Subject: [PATCH 3/5] pinctrl: npcm8xx: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-gpio-mmio-pinctrl-conv-v1-3-a84c5da2be20@linaro.org> References: <20250811-gpio-mmio-pinctrl-conv-v1-0-a84c5da2be20@linaro.org> In-Reply-To: <20250811-gpio-mmio-pinctrl-conv-v1-0-a84c5da2be20@linaro.org> To: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , Linus Walleij , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Cc: linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 154 +++++++++++++++-----------= ---- 1 file changed, 78 insertions(+), 76 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nu= voton/pinctrl-npcm8xx.c index 3c3b9d8d3681c64c21927615e1bb49f157f156b5..0f155a685bbae774129aa55b838= 65e546314e81c 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -90,7 +91,7 @@ struct debounce_time { }; =20 struct npcm8xx_gpio { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *base; struct debounce_time debounce; int irqbase; @@ -115,24 +116,20 @@ struct npcm8xx_pinctrl { }; =20 /* GPIO handling in the pinctrl driver */ -static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, +static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *re= g, unsigned int pinmask) { - unsigned long flags; + guard(gpio_generic_lock_irqsave)(chip); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); iowrite32(ioread32(reg) | pinmask, reg); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 -static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, +static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *re= g, unsigned int pinmask) { - unsigned long flags; + guard(gpio_generic_lock_irqsave)(chip); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); iowrite32(ioread32(reg) & ~pinmask, reg); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -233,32 +230,32 @@ static int npcmgpio_set_irq_type(struct irq_data *d, = unsigned int type) =20 switch (type) { case IRQ_TYPE_EDGE_RISING: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); break; case IRQ_TYPE_EDGE_FALLING: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); break; case IRQ_TYPE_EDGE_BOTH: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio); break; case IRQ_TYPE_LEVEL_LOW: - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); break; case IRQ_TYPE_LEVEL_HIGH: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio); break; default: return -EINVAL; } =20 if (type & IRQ_TYPE_LEVEL_MASK) { - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_level_irq); } else if (type & IRQ_TYPE_EDGE_BOTH) { - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_edge_irq); } =20 @@ -1842,7 +1839,7 @@ static void npcm8xx_setfunc(struct regmap *gcr_regmap= , const unsigned int *pin, static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, struct regmap *gcr_regmap, unsigned int pin) { - int gpio =3D pin % bank->gc.ngpio; + int gpio =3D pin % bank->chip.gc.ngpio; unsigned long pinmask =3D BIT(gpio); u32 val; =20 @@ -1862,15 +1859,15 @@ static int npcm8xx_set_slew_rate(struct npcm8xx_gpi= o *bank, int arg) { void __iomem *OSRC_Offset =3D bank->base + NPCM8XX_GP_N_OSRC; - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); =20 if (pincfg[pin].flag & SLEW) { switch (arg) { case 0: - npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); + npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio); return 0; case 1: - npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); + npcm_gpio_set(&bank->chip, OSRC_Offset, gpio); return 0; default: return -EINVAL; @@ -1902,7 +1899,7 @@ static int npcm8xx_get_drive_strength(struct pinctrl_= dev *pctldev, struct npcm8xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; - int gpio =3D pin % bank->gc.ngpio; + int gpio =3D pin % bank->chip.gc.ngpio; unsigned long pinmask =3D BIT(gpio); int flg, val; u32 ds =3D 0; @@ -1913,7 +1910,7 @@ static int npcm8xx_get_drive_strength(struct pinctrl_= dev *pctldev, =20 val =3D ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; ds =3D val ? DSHI(flg) : DSLO(flg); - dev_dbg(bank->gc.parent, "pin %d strength %d =3D %d\n", pin, val, ds); + dev_dbg(bank->chip.gc.parent, "pin %d strength %d =3D %d\n", pin, val, ds= ); =20 return ds; } @@ -1923,15 +1920,15 @@ static int npcm8xx_set_drive_strength(struct npcm8x= x_pinctrl *npcm, { struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); int v; =20 v =3D pincfg[pin].flag & DRIVE_STRENGTH_MASK; =20 if (DSLO(v) =3D=3D nval) - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); else if (DSHI(v) =3D=3D nval) - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio); else return -ENOTSUPP; =20 @@ -2054,7 +2051,7 @@ static int npcm_gpio_set_direction(struct pinctrl_dev= *pctldev, struct npcm8xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; - int gpio =3D BIT(offset % bank->gc.ngpio); + int gpio =3D BIT(offset % bank->chip.gc.ngpio); =20 if (input) iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); @@ -2085,7 +2082,7 @@ static int debounce_timing_setting(struct npcm8xx_gpi= o *bank, u32 gpio, if (bank->debounce.set_val[i]) { if (bank->debounce.nanosec_val[i] =3D=3D nanosecs) { debounce_select =3D i << gpio_debounce; - npcm_gpio_set(&bank->gc, DBNCS_offset, + npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select); break; } @@ -2093,7 +2090,7 @@ static int debounce_timing_setting(struct npcm8xx_gpi= o *bank, u32 gpio, bank->debounce.set_val[i] =3D true; bank->debounce.nanosec_val[i] =3D nanosecs; debounce_select =3D i << gpio_debounce; - npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); + npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select); switch (nanosecs) { case 1 ... 1040: iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); @@ -2145,21 +2142,21 @@ static int npcm_set_debounce(struct npcm8xx_pinctrl= *npcm, unsigned int pin, { struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); int ret; =20 if (nanosecs) { - ret =3D debounce_timing_setting(bank, pin % bank->gc.ngpio, + ret =3D debounce_timing_setting(bank, pin % bank->chip.gc.ngpio, nanosecs); if (ret) dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, p= lease use one of exist debounce values\n", pin); else - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio); return ret; } =20 - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio); =20 return 0; } @@ -2172,7 +2169,7 @@ static int npcm8xx_config_get(struct pinctrl_dev *pct= ldev, unsigned int pin, struct npcm8xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; - int gpio =3D pin % bank->gc.ngpio; + int gpio =3D pin % bank->chip.gc.ngpio; unsigned long pinmask =3D BIT(gpio); u32 ie, oe, pu, pd; int rc =3D 0; @@ -2235,34 +2232,34 @@ static int npcm8xx_config_set_one(struct npcm8xx_pi= nctrl *npcm, struct npcm8xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; u32 arg =3D pinconf_to_config_argument(config); - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); =20 switch (param) { case PIN_CONFIG_BIAS_DISABLE: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); break; case PIN_CONFIG_BIAS_PULL_DOWN: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); break; case PIN_CONFIG_BIAS_PULL_UP: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio); break; case PIN_CONFIG_INPUT_ENABLE: iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); break; case PIN_CONFIG_OUTPUT: - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); break; case PIN_CONFIG_DRIVE_PUSH_PULL: - npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: - npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio); break; case PIN_CONFIG_INPUT_DEBOUNCE: return npcm_set_debounce(npcm, pin, arg * 1000); @@ -2313,13 +2310,14 @@ static int npcmgpio_add_pin_ranges(struct gpio_chip= *chip) { struct npcm8xx_gpio *bank =3D gpiochip_get_data(chip); =20 - return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), - bank->pinctrl_id, bank->gc.base, - bank->gc.ngpio); + return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent), + bank->pinctrl_id, bank->chip.gc.base, + bank->chip.gc.ngpio); } =20 static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) { + struct gpio_generic_chip_config config; struct fwnode_reference_args args; struct device *dev =3D pctrl->dev; struct fwnode_handle *child; @@ -2331,15 +2329,19 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *= pctrl) if (!pctrl->gpio_bank[id].base) return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); =20 - ret =3D bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, - NULL, - NULL, - pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, + .set =3D pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, + .dirin =3D pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); if (ret) - return dev_err_probe(dev, ret, "bgpio_init() failed\n"); + return dev_err_probe(dev, ret, + "failed to initialize the generic GPIO chip\n"); =20 ret =3D fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3= , 0, &args); if (ret < 0) @@ -2353,26 +2355,26 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *= pctrl) pctrl->gpio_bank[id].irq_chip =3D npcmgpio_irqchip; pctrl->gpio_bank[id].irqbase =3D id * NPCM8XX_GPIO_PER_BANK; pctrl->gpio_bank[id].pinctrl_id =3D args.args[0]; - pctrl->gpio_bank[id].gc.base =3D -1; - pctrl->gpio_bank[id].gc.ngpio =3D args.args[2]; - pctrl->gpio_bank[id].gc.owner =3D THIS_MODULE; - pctrl->gpio_bank[id].gc.parent =3D dev; - pctrl->gpio_bank[id].gc.fwnode =3D child; - pctrl->gpio_bank[id].gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "%pfw"= , child); - if (pctrl->gpio_bank[id].gc.label =3D=3D NULL) + pctrl->gpio_bank[id].chip.gc.base =3D -1; + pctrl->gpio_bank[id].chip.gc.ngpio =3D args.args[2]; + pctrl->gpio_bank[id].chip.gc.owner =3D THIS_MODULE; + pctrl->gpio_bank[id].chip.gc.parent =3D dev; + pctrl->gpio_bank[id].chip.gc.fwnode =3D child; + pctrl->gpio_bank[id].chip.gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "= %pfw", child); + if (pctrl->gpio_bank[id].chip.gc.label =3D=3D NULL) return -ENOMEM; =20 - pctrl->gpio_bank[id].gc.dbg_show =3D npcmgpio_dbg_show; - pctrl->gpio_bank[id].direction_input =3D pctrl->gpio_bank[id].gc.directi= on_input; - pctrl->gpio_bank[id].gc.direction_input =3D npcmgpio_direction_input; - pctrl->gpio_bank[id].direction_output =3D pctrl->gpio_bank[id].gc.direct= ion_output; - pctrl->gpio_bank[id].gc.direction_output =3D npcmgpio_direction_output; - pctrl->gpio_bank[id].request =3D pctrl->gpio_bank[id].gc.request; - pctrl->gpio_bank[id].gc.request =3D npcmgpio_gpio_request; - pctrl->gpio_bank[id].gc.free =3D pinctrl_gpio_free; + pctrl->gpio_bank[id].chip.gc.dbg_show =3D npcmgpio_dbg_show; + pctrl->gpio_bank[id].direction_input =3D pctrl->gpio_bank[id].chip.gc.di= rection_input; + pctrl->gpio_bank[id].chip.gc.direction_input =3D npcmgpio_direction_inpu= t; + pctrl->gpio_bank[id].direction_output =3D pctrl->gpio_bank[id].chip.gc.d= irection_output; + pctrl->gpio_bank[id].chip.gc.direction_output =3D npcmgpio_direction_out= put; + pctrl->gpio_bank[id].request =3D pctrl->gpio_bank[id].chip.gc.request; + pctrl->gpio_bank[id].chip.gc.request =3D npcmgpio_gpio_request; + pctrl->gpio_bank[id].chip.gc.free =3D pinctrl_gpio_free; for (i =3D 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) pctrl->gpio_bank[id].debounce.set_val[i] =3D false; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 181 +++++++++++++++-----------= ---- 1 file changed, 90 insertions(+), 91 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nu= voton/pinctrl-npcm7xx.c index b8872d8f5930ad931dad208afec4e08a23c3d653..c2ca71ebb9736d1b3043fa66267= 67811a67e61f2 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -4,6 +4,7 @@ =20 #include #include +#include #include #include #include @@ -77,7 +78,7 @@ /* Structure for register banks */ struct npcm7xx_gpio { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip chip; int irqbase; int irq; u32 pinctrl_id; @@ -99,32 +100,26 @@ struct npcm7xx_pinctrl { }; =20 /* GPIO handling in the pinctrl driver */ -static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, +static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *re= g, unsigned int pinmask) { - unsigned long flags; unsigned long val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(chip); =20 val =3D ioread32(reg) | pinmask; iowrite32(val, reg); - - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 -static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, +static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *re= g, unsigned int pinmask) { - unsigned long flags; unsigned long val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(chip); =20 val =3D ioread32(reg) & ~pinmask; iowrite32(val, reg); - - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -132,9 +127,9 @@ static void npcmgpio_dbg_show(struct seq_file *s, struc= t gpio_chip *chip) struct npcm7xx_gpio *bank =3D gpiochip_get_data(chip); =20 seq_printf(s, "-- module %d [gpio%d - %d]\n", - bank->gc.base / bank->gc.ngpio, - bank->gc.base, - bank->gc.base + bank->gc.ngpio); + bank->chip.gc.base / bank->chip.gc.ngpio, + bank->chip.gc.base, + bank->chip.gc.base + bank->chip.gc.ngpio); seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", ioread32(bank->base + NPCM7XX_GP_N_DIN), ioread32(bank->base + NPCM7XX_GP_N_DOUT), @@ -220,7 +215,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); sts =3D ioread32(bank->base + NPCM7XX_GP_N_EVST); en =3D ioread32(bank->base + NPCM7XX_GP_N_EVEN); - dev_dbg(bank->gc.parent, "=3D=3D> got irq sts %.8lx %.8lx\n", sts, + dev_dbg(bank->chip.gc.parent, "=3D=3D> got irq sts %.8lx %.8lx\n", sts, en); =20 sts &=3D en; @@ -235,42 +230,42 @@ static int npcmgpio_set_irq_type(struct irq_data *d, = unsigned int type) struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); unsigned int gpio =3D BIT(irqd_to_hwirq(d)); =20 - dev_dbg(bank->gc.parent, "setirqtype: %u.%u =3D %u\n", gpio, + dev_dbg(bank->chip.gc.parent, "setirqtype: %u.%u =3D %u\n", gpio, d->irq, type); switch (type) { case IRQ_TYPE_EDGE_RISING: - dev_dbg(bank->gc.parent, "edge.rising\n"); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); + dev_dbg(bank->chip.gc.parent, "edge.rising\n"); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); break; case IRQ_TYPE_EDGE_FALLING: - dev_dbg(bank->gc.parent, "edge.falling\n"); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); + dev_dbg(bank->chip.gc.parent, "edge.falling\n"); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); break; case IRQ_TYPE_EDGE_BOTH: - dev_dbg(bank->gc.parent, "edge.both\n"); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); + dev_dbg(bank->chip.gc.parent, "edge.both\n"); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); break; case IRQ_TYPE_LEVEL_LOW: - dev_dbg(bank->gc.parent, "level.low\n"); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); + dev_dbg(bank->chip.gc.parent, "level.low\n"); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); break; case IRQ_TYPE_LEVEL_HIGH: - dev_dbg(bank->gc.parent, "level.high\n"); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); + dev_dbg(bank->chip.gc.parent, "level.high\n"); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); break; default: - dev_dbg(bank->gc.parent, "invalid irq type\n"); + dev_dbg(bank->chip.gc.parent, "invalid irq type\n"); return -EINVAL; } =20 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_level_irq); } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); irq_set_handler_locked(d, handle_edge_irq); } =20 @@ -283,7 +278,7 @@ static void npcmgpio_irq_ack(struct irq_data *d) struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); unsigned int gpio =3D irqd_to_hwirq(d); =20 - dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); + dev_dbg(bank->chip.gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); } =20 @@ -295,7 +290,7 @@ static void npcmgpio_irq_mask(struct irq_data *d) unsigned int gpio =3D irqd_to_hwirq(d); =20 /* Clear events */ - dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); + dev_dbg(bank->chip.gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); gpiochip_disable_irq(gc, gpio); } @@ -309,7 +304,7 @@ static void npcmgpio_irq_unmask(struct irq_data *d) =20 /* Enable events */ gpiochip_enable_irq(gc, gpio); - dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); + dev_dbg(bank->chip.gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); } =20 @@ -1423,7 +1418,7 @@ static int npcm7xx_get_slew_rate(struct npcm7xx_gpio = *bank, struct regmap *gcr_regmap, unsigned int pin) { u32 val; - int gpio =3D (pin % bank->gc.ngpio); + int gpio =3D (pin % bank->chip.gc.ngpio); unsigned long pinmask =3D BIT(gpio); =20 if (pincfg[pin].flag & SLEW) @@ -1443,16 +1438,16 @@ static int npcm7xx_set_slew_rate(struct npcm7xx_gpi= o *bank, struct regmap *gcr_regmap, unsigned int pin, int arg) { - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); =20 if (pincfg[pin].flag & SLEW) { switch (arg) { case 0: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, gpio); return 0; case 1: - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, gpio); return 0; default: @@ -1485,7 +1480,7 @@ static int npcm7xx_get_drive_strength(struct pinctrl_= dev *pctldev, struct npcm7xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm7xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; - int gpio =3D (pin % bank->gc.ngpio); + int gpio =3D (pin % bank->chip.gc.ngpio); unsigned long pinmask =3D BIT(gpio); u32 ds =3D 0; int flg, val; @@ -1496,7 +1491,7 @@ static int npcm7xx_get_drive_strength(struct pinctrl_= dev *pctldev, val =3D ioread32(bank->base + NPCM7XX_GP_N_ODSC) & pinmask; ds =3D val ? DSHI(flg) : DSLO(flg); - dev_dbg(bank->gc.parent, + dev_dbg(bank->chip.gc.parent, "pin %d strength %d =3D %d\n", pin, val, ds); return ds; } @@ -1511,20 +1506,20 @@ static int npcm7xx_set_drive_strength(struct npcm7x= x_pinctrl *npcm, int v; struct npcm7xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); =20 v =3D (pincfg[pin].flag & DRIVE_STRENGTH_MASK); if (!nval || !v) return -ENOTSUPP; if (DSLO(v) =3D=3D nval) { - dev_dbg(bank->gc.parent, + dev_dbg(bank->chip.gc.parent, "setting pin %d to low strength [%d]\n", pin, nval); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); return 0; } else if (DSHI(v) =3D=3D nval) { - dev_dbg(bank->gc.parent, + dev_dbg(bank->chip.gc.parent, "setting pin %d to high strength [%d]\n", pin, nval); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); return 0; } =20 @@ -1657,9 +1652,9 @@ static int npcm_gpio_set_direction(struct pinctrl_dev= *pctldev, struct npcm7xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm7xx_gpio *bank =3D &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; - int gpio =3D BIT(offset % bank->gc.ngpio); + int gpio =3D BIT(offset % bank->chip.gc.ngpio); =20 - dev_dbg(bank->gc.parent, "GPIO Set Direction: %d =3D %d\n", offset, + dev_dbg(bank->chip.gc.parent, "GPIO Set Direction: %d =3D %d\n", offset, input); if (input) iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); @@ -1687,7 +1682,7 @@ static int npcm7xx_config_get(struct pinctrl_dev *pct= ldev, unsigned int pin, struct npcm7xx_pinctrl *npcm =3D pinctrl_dev_get_drvdata(pctldev); struct npcm7xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; - int gpio =3D (pin % bank->gc.ngpio); + int gpio =3D (pin % bank->chip.gc.ngpio); unsigned long pinmask =3D BIT(gpio); u32 ie, oe, pu, pd; int rc =3D 0; @@ -1750,38 +1745,38 @@ static int npcm7xx_config_set_one(struct npcm7xx_pi= nctrl *npcm, u16 arg =3D pinconf_to_config_argument(config); struct npcm7xx_gpio *bank =3D &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; - int gpio =3D BIT(pin % bank->gc.ngpio); + int gpio =3D BIT(pin % bank->chip.gc.ngpio); =20 - dev_dbg(bank->gc.parent, "param=3D%d %d[GPIO]\n", param, pin); + dev_dbg(bank->chip.gc.parent, "param=3D%d %d[GPIO]\n", param, pin); switch (param) { case PIN_CONFIG_BIAS_DISABLE: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); break; case PIN_CONFIG_BIAS_PULL_DOWN: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); break; case PIN_CONFIG_BIAS_PULL_UP: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); break; case PIN_CONFIG_INPUT_ENABLE: iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); - bank->direction_input(&bank->gc, pin % bank->gc.ngpio); + bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); break; case PIN_CONFIG_OUTPUT: - bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); + bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); break; case PIN_CONFIG_DRIVE_PUSH_PULL: - npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); + npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); break; case PIN_CONFIG_INPUT_DEBOUNCE: - npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); + npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_DBNC, gpio); break; case PIN_CONFIG_SLEW_RATE: return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); @@ -1829,6 +1824,7 @@ static const struct pinctrl_desc npcm7xx_pinctrl_desc= =3D { =20 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) { + struct gpio_generic_chip_config config; int ret =3D -ENXIO; struct device *dev =3D pctrl->dev; struct fwnode_reference_args args; @@ -1840,15 +1836,18 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *= pctrl) if (!pctrl->gpio_bank[id].base) return -EINVAL; =20 - ret =3D bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, - NULL, - NULL, - pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, + .set =3D pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, + .dirin =3D pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); if (ret) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize the generic GPIO chip\n"); return ret; } =20 @@ -1866,23 +1865,23 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *= pctrl) pctrl->gpio_bank[id].irq =3D ret; pctrl->gpio_bank[id].irqbase =3D id * NPCM7XX_GPIO_PER_BANK; pctrl->gpio_bank[id].pinctrl_id =3D args.args[0]; - pctrl->gpio_bank[id].gc.base =3D args.args[1]; - pctrl->gpio_bank[id].gc.ngpio =3D args.args[2]; - pctrl->gpio_bank[id].gc.owner =3D THIS_MODULE; - pctrl->gpio_bank[id].gc.parent =3D dev; - pctrl->gpio_bank[id].gc.fwnode =3D child; - pctrl->gpio_bank[id].gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "%pfw"= , child); - if (pctrl->gpio_bank[id].gc.label =3D=3D NULL) + pctrl->gpio_bank[id].chip.gc.base =3D args.args[1]; + pctrl->gpio_bank[id].chip.gc.ngpio =3D args.args[2]; + pctrl->gpio_bank[id].chip.gc.owner =3D THIS_MODULE; + pctrl->gpio_bank[id].chip.gc.parent =3D dev; + pctrl->gpio_bank[id].chip.gc.fwnode =3D child; + pctrl->gpio_bank[id].chip.gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "= %pfw", child); + if (pctrl->gpio_bank[id].chip.gc.label =3D=3D NULL) return -ENOMEM; =20 - pctrl->gpio_bank[id].gc.dbg_show =3D npcmgpio_dbg_show; - pctrl->gpio_bank[id].direction_input =3D pctrl->gpio_bank[id].gc.directi= on_input; - pctrl->gpio_bank[id].gc.direction_input =3D npcmgpio_direction_input; - pctrl->gpio_bank[id].direction_output =3D pctrl->gpio_bank[id].gc.direct= ion_output; - pctrl->gpio_bank[id].gc.direction_output =3D npcmgpio_direction_output; - pctrl->gpio_bank[id].request =3D pctrl->gpio_bank[id].gc.request; - pctrl->gpio_bank[id].gc.request =3D npcmgpio_gpio_request; - pctrl->gpio_bank[id].gc.free =3D pinctrl_gpio_free; + pctrl->gpio_bank[id].chip.gc.dbg_show =3D npcmgpio_dbg_show; + pctrl->gpio_bank[id].direction_input =3D pctrl->gpio_bank[id].chip.gc.di= rection_input; + pctrl->gpio_bank[id].chip.gc.direction_input =3D npcmgpio_direction_inpu= t; + pctrl->gpio_bank[id].direction_output =3D pctrl->gpio_bank[id].chip.gc.d= irection_output; + pctrl->gpio_bank[id].chip.gc.direction_output =3D npcmgpio_direction_out= put; + pctrl->gpio_bank[id].request =3D pctrl->gpio_bank[id].chip.gc.request; + pctrl->gpio_bank[id].chip.gc.request =3D npcmgpio_gpio_request; + pctrl->gpio_bank[id].chip.gc.free =3D pinctrl_gpio_free; id++; } =20 @@ -1897,7 +1896,7 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinct= rl *pctrl) for (id =3D 0 ; id < pctrl->bank_num ; id++) { struct gpio_irq_chip *girq; =20 - girq =3D &pctrl->gpio_bank[id].gc.irq; + girq =3D &pctrl->gpio_bank[id].chip.gc.irq; gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip); girq->parent_handler =3D npcmgpio_irq_handler; girq->num_parents =3D 1; @@ -1912,21 +1911,21 @@ static int npcm7xx_gpio_register(struct npcm7xx_pin= ctrl *pctrl) girq->default_type =3D IRQ_TYPE_NONE; girq->handler =3D handle_level_irq; ret =3D devm_gpiochip_add_data(pctrl->dev, - &pctrl->gpio_bank[id].gc, + &pctrl->gpio_bank[id].chip.gc, &pctrl->gpio_bank[id]); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 44 ++++++++++++++++++++-------= ---- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nu= voton/pinctrl-wpcm450.c index 8d8314ba0e4cb55db2b1d3adf2de07e6fb93c279..4dd8a3daa83e44b0e2780fedb03= ab11fa46a4b7d 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -47,7 +48,7 @@ struct wpcm450_pinctrl; struct wpcm450_bank; =20 struct wpcm450_gpio { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct wpcm450_pinctrl *pctrl; const struct wpcm450_bank *bank; }; @@ -184,11 +185,12 @@ static void wpcm450_gpio_irq_unmask(struct irq_data *= d) } =20 /* - * This is an implementation of the gpio_chip->get() function, for use in - * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided - * implementation there, because it would require taking gpio_chip->bgpio_= lock, - * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts = where - * a raw spin lock is held. + * FIXME: This is an implementation of the gpio_chip->get() function, for = use + * in wpcm450_gpio_fix_evpol(). It was implemented back when gpio-mmio use= d a + * regular spinlock internally, while wpcm450_gpio_fix_evpol() needed to w= ork + * in contexts with a raw spinlock held. Since then, the gpio generic chip= has + * been switched to using a raw spinlock so this should be converted to us= ing + * the locking interfaces provided in linux/gpio/gneneric.h. */ static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) { @@ -329,7 +331,7 @@ static void wpcm450_gpio_irqhandler(struct irq_desc *de= sc) for_each_set_bit(bit, &pending, 32) { int offset =3D wpcm450_irq_bitnum_to_gpio(gpio, bit); =20 - generic_handle_domain_irq(gpio->gc.irq.domain, offset); + generic_handle_domain_irq(gpio->chip.gc.irq.domain, offset); } chained_irq_exit(chip, desc); } @@ -1012,7 +1014,7 @@ static int wpcm450_gpio_add_pin_ranges(struct gpio_ch= ip *chip) struct wpcm450_gpio *gpio =3D gpiochip_get_data(chip); const struct wpcm450_bank *bank =3D gpio->bank; =20 - return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev), + return gpiochip_add_pin_range(&gpio->chip.gc, dev_name(gpio->pctrl->dev), 0, bank->base, bank->length); } =20 @@ -1029,6 +1031,7 @@ static int wpcm450_gpio_register(struct platform_devi= ce *pdev, "Resource fail for GPIO controller\n"); =20 for_each_gpiochip_node(dev, child) { + struct gpio_generic_chip_config config; void __iomem *dat =3D NULL; void __iomem *set =3D NULL; void __iomem *dirout =3D NULL; @@ -1060,17 +1063,26 @@ static int wpcm450_gpio_register(struct platform_de= vice *pdev, } else { flags =3D BGPIOF_NO_OUTPUT; } - ret =3D bgpio_init(&gpio->gc, dev, 4, - dat, set, NULL, dirout, NULL, flags); + + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .dirout =3D dirout, + .flags =3D flags, + }; + + ret =3D gpio_generic_chip_init(&gpio->chip, &config); if (ret < 0) return dev_err_probe(dev, ret, "GPIO initialization failed\n"); =20 - gpio->gc.ngpio =3D bank->length; - gpio->gc.set_config =3D wpcm450_gpio_set_config; - gpio->gc.fwnode =3D child; - gpio->gc.add_pin_ranges =3D wpcm450_gpio_add_pin_ranges; + gpio->chip.gc.ngpio =3D bank->length; + gpio->chip.gc.set_config =3D wpcm450_gpio_set_config; + gpio->chip.gc.fwnode =3D child; + gpio->chip.gc.add_pin_ranges =3D wpcm450_gpio_add_pin_ranges; =20 - girq =3D &gpio->gc.irq; + girq =3D &gpio->chip.gc.irq; gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); girq->parent_handler =3D wpcm450_gpio_irqhandler; girq->parents =3D devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, @@ -1094,7 +1106,7 @@ static int wpcm450_gpio_register(struct platform_devi= ce *pdev, girq->num_parents++; } =20 - ret =3D devm_gpiochip_add_data(dev, &gpio->gc, gpio); + ret =3D devm_gpiochip_add_data(dev, &gpio->chip.gc, gpio); if (ret) return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); } --=20 2.48.1