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Mon, 11 Aug 2025 15:18:35 +0000 (UTC) From: Brian Masney via B4 Relay Date: Mon, 11 Aug 2025 11:19:38 -0400 Subject: [PATCH 106/114] clk: versaclock5: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-clk-for-stephen-round-rate-v1-106-b3bf97b038dc@redhat.com> References: <20250811-clk-for-stephen-round-rate-v1-0-b3bf97b038dc@redhat.com> In-Reply-To: <20250811-clk-for-stephen-round-rate-v1-0-b3bf97b038dc@redhat.com> To: Michael Turquette , Stephen Boyd , Sudeep Holla , Cristian Marussi , Chen Wang , Inochi Amaoto , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Paul Cercueil , Keguang Zhang , Taichi Sugaya , Takao Orito , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jacky Huang , Shan-Chun Hung , Vladimir Zapolskiy , Piotr Wojtaszczyk , Paul Walmsley , Samuel Holland , Yixun Lan , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Orson Zhai , Baolin Wang , Chunyan Zhang , Maxime Coquelin , Alexandre Torgue , Michal Simek , Maxime Ripard , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Eugeniy Paltsev , Ray Jui , Scott Branden , Broadcom internal kernel review list , Max Filippov , Matthias Brugger , AngeloGioacchino Del Regno , Daniel Palmer , Romain Perier , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Bjorn Andersson , Geert Uytterhoeven , Heiko Stuebner , Andrea della Porta , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Qin Jian , Viresh Kumar , Ulf Hansson , Luca Ceresoli , Alex Helms , Linus Walleij , Liviu Dudau , Lorenzo Pieralisi , Nobuhiro Iwamatsu Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sophgo@lists.linux.dev, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, patches@opensource.cirrus.com, linux-actions@lists.infradead.org, asahi@lists.linux.dev, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754925498; l=6516; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=XKgkkzQfXsal4tbcIQtc1juzVPJNcjhK8nlpaSZyjxs=; b=/kjWcKQ9Zcr2pUuyG6Lr+yWj6Q4DGldsVrZfZ8dUcszB2kOq+wcYal8JNiLPoeTKadFCo9Tka YkV2e4JPDpDCttNDDbSVeAhG4NLOZp0im3I/GBJ1u6SmobtclsiEMpv X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= X-Endpoint-Received: by B4 Relay for bmasney@redhat.com/20250528 with auth_id=472 X-Original-From: Brian Masney Reply-To: bmasney@redhat.com From: Brian Masney The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Reviewed-by: Luca Ceresoli --- drivers/clk/clk-versaclock5.c | 71 ++++++++++++++++++++++++---------------= ---- 1 file changed, 40 insertions(+), 31 deletions(-) diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 4200022d20846038f02e191042da2a188c392402..57228e88e81dc6f2af955a82a32= 75430e46c0920 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -304,11 +304,11 @@ static unsigned long vc5_dbl_recalc_rate(struct clk_h= w *hw, return parent_rate; } =20 -static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int vc5_dbl_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - if ((*parent_rate =3D=3D rate) || ((*parent_rate * 2) =3D=3D rate)) - return rate; + if ((req->best_parent_rate =3D=3D req->rate) || ((req->best_parent_rate *= 2) =3D=3D req->rate)) + return 0; else return -EINVAL; } @@ -332,7 +332,7 @@ static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned= long rate, =20 static const struct clk_ops vc5_dbl_ops =3D { .recalc_rate =3D vc5_dbl_recalc_rate, - .round_rate =3D vc5_dbl_round_rate, + .determine_rate =3D vc5_dbl_determine_rate, .set_rate =3D vc5_dbl_set_rate, }; =20 @@ -363,24 +363,29 @@ static unsigned long vc5_pfd_recalc_rate(struct clk_h= w *hw, return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); } =20 -static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int vc5_pfd_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long idiv; =20 /* PLL cannot operate with input clock above 50 MHz. */ - if (rate > 50000000) + if (req->rate > 50000000) return -EINVAL; =20 /* CLKIN within range of PLL input, feed directly to PLL. */ - if (*parent_rate <=3D 50000000) - return *parent_rate; + if (req->best_parent_rate <=3D 50000000) { + req->rate =3D req->best_parent_rate; + + return 0; + } =20 - idiv =3D DIV_ROUND_UP(*parent_rate, rate); + idiv =3D DIV_ROUND_UP(req->best_parent_rate, req->rate); if (idiv > 127) return -EINVAL; =20 - return *parent_rate / idiv; + req->rate =3D req->best_parent_rate / idiv; + + return 0; } =20 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, @@ -420,7 +425,7 @@ static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned= long rate, =20 static const struct clk_ops vc5_pfd_ops =3D { .recalc_rate =3D vc5_pfd_recalc_rate, - .round_rate =3D vc5_pfd_round_rate, + .determine_rate =3D vc5_pfd_determine_rate, .set_rate =3D vc5_pfd_set_rate, }; =20 @@ -444,30 +449,32 @@ static unsigned long vc5_pll_recalc_rate(struct clk_h= w *hw, return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); } =20 -static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int vc5_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct vc5_hw_data *hwdata =3D container_of(hw, struct vc5_hw_data, hw); struct vc5_driver_data *vc5 =3D hwdata->vc5; u32 div_int; u64 div_frc; =20 - rate =3D clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); + req->rate =3D clamp(req->rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); =20 /* Determine integer part, which is 12 bit wide */ - div_int =3D rate / *parent_rate; + div_int =3D req->rate / req->best_parent_rate; if (div_int > 0xfff) - rate =3D *parent_rate * 0xfff; + req->rate =3D req->best_parent_rate * 0xfff; =20 /* Determine best fractional part, which is 24 bit wide */ - div_frc =3D rate % *parent_rate; + div_frc =3D req->rate % req->best_parent_rate; div_frc *=3D BIT(24) - 1; - do_div(div_frc, *parent_rate); + do_div(div_frc, req->best_parent_rate); =20 hwdata->div_int =3D div_int; hwdata->div_frc =3D (u32)div_frc; =20 - return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); + req->rate =3D (req->best_parent_rate * div_int) + ((req->best_parent_rate= * div_frc) >> 24); + + return 0; } =20 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, @@ -488,7 +495,7 @@ static int vc5_pll_set_rate(struct clk_hw *hw, unsigned= long rate, =20 static const struct clk_ops vc5_pll_ops =3D { .recalc_rate =3D vc5_pll_recalc_rate, - .round_rate =3D vc5_pll_round_rate, + .determine_rate =3D vc5_pll_determine_rate, .set_rate =3D vc5_pll_set_rate, }; =20 @@ -520,17 +527,17 @@ static unsigned long vc5_fod_recalc_rate(struct clk_h= w *hw, return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); } =20 -static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int vc5_fod_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct vc5_hw_data *hwdata =3D container_of(hw, struct vc5_hw_data, hw); /* VCO frequency is divided by two before entering FOD */ - u32 f_in =3D *parent_rate / 2; + u32 f_in =3D req->best_parent_rate / 2; u32 div_int; u64 div_frc; =20 /* Determine integer part, which is 12 bit wide */ - div_int =3D f_in / rate; + div_int =3D f_in / req->rate; /* * WARNING: The clock chip does not output signal if the integer part * of the divider is 0xfff and fractional part is non-zero. @@ -538,18 +545,20 @@ static long vc5_fod_round_rate(struct clk_hw *hw, uns= igned long rate, */ if (div_int > 0xffe) { div_int =3D 0xffe; - rate =3D f_in / div_int; + req->rate =3D f_in / div_int; } =20 /* Determine best fractional part, which is 30 bit wide */ - div_frc =3D f_in % rate; + div_frc =3D f_in % req->rate; div_frc <<=3D 24; - do_div(div_frc, rate); + do_div(div_frc, req->rate); =20 hwdata->div_int =3D div_int; hwdata->div_frc =3D (u32)div_frc; =20 - return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); + req->rate =3D div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div= _frc); + + return 0; } =20 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, @@ -589,7 +598,7 @@ static int vc5_fod_set_rate(struct clk_hw *hw, unsigned= long rate, =20 static const struct clk_ops vc5_fod_ops =3D { .recalc_rate =3D vc5_fod_recalc_rate, - .round_rate =3D vc5_fod_round_rate, + .determine_rate =3D vc5_fod_determine_rate, .set_rate =3D vc5_fod_set_rate, }; =20 --=20 2.50.1