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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:46 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:12 -0400 Subject: [PATCH 7/7] clk: ti: fapll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-7-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=3724; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=35dv85IMLqZUQXMLmdKz9Cv7IO7JQIrFzXOoEzRX50w=; b=N25Ia/p/HvCELWsArvVY0UtQVgJ3XAaJSxes8tGYmI13Fnbu/6iFvl8iKyxqGdFoqRprtooUL btcrwmBZrFsDgLojbWvoFnBiuu79baJzYrO8uPhWQ0uNx1ED+hva180 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/ti/fapll.c | 48 +++++++++++++++++++++++++++-------------------= -- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index 2db3fc4a443e052722d5c01e5ef38cc1417d818f..4f28138d2d8abfa63e13c23d6a7= 326f3a2cdbf86 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -214,24 +214,27 @@ static int ti_fapll_set_div_mult(unsigned long rate, return 0; } =20 -static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int ti_fapll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 pre_div_p, mult_n; int error; =20 - if (!rate) + if (!req->rate) return -EINVAL; =20 - error =3D ti_fapll_set_div_mult(rate, *parent_rate, + error =3D ti_fapll_set_div_mult(req->rate, req->best_parent_rate, &pre_div_p, &mult_n); - if (error) - return error; + if (error) { + req->rate =3D error; =20 - rate =3D *parent_rate / pre_div_p; - rate *=3D mult_n; + return 0; + } =20 - return rate; + req->rate =3D req->best_parent_rate / pre_div_p; + req->rate *=3D mult_n; + + return 0; } =20 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, @@ -268,7 +271,7 @@ static const struct clk_ops ti_fapll_ops =3D { .is_enabled =3D ti_fapll_is_enabled, .recalc_rate =3D ti_fapll_recalc_rate, .get_parent =3D ti_fapll_get_parent, - .round_rate =3D ti_fapll_round_rate, + .determine_rate =3D ti_fapll_determine_rate, .set_rate =3D ti_fapll_set_rate, }; =20 @@ -399,14 +402,14 @@ static u32 ti_fapll_synth_set_frac_rate(struct fapll_= synth *synth, return post_div_m; } =20 -static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rat= e, - unsigned long *parent_rate) +static int ti_fapll_synth_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct fapll_synth *synth =3D to_synth(hw); struct fapll_data *fd =3D synth->fd; unsigned long r; =20 - if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) + if (ti_fapll_clock_is_bypass(fd) || !synth->div || !req->rate) return -EINVAL; =20 /* Only post divider m available with no fractional divider? */ @@ -414,23 +417,26 @@ static long ti_fapll_synth_round_rate(struct clk_hw *= hw, unsigned long rate, unsigned long frac_rate; u32 synth_post_div_m; =20 - frac_rate =3D ti_fapll_synth_get_frac_rate(hw, *parent_rate); - synth_post_div_m =3D DIV_ROUND_UP(frac_rate, rate); + frac_rate =3D ti_fapll_synth_get_frac_rate(hw, + req->best_parent_rate); + synth_post_div_m =3D DIV_ROUND_UP(frac_rate, req->rate); r =3D DIV_ROUND_UP(frac_rate, synth_post_div_m); goto out; } =20 - r =3D *parent_rate * SYNTH_PHASE_K; - if (rate > r) + r =3D req->best_parent_rate * SYNTH_PHASE_K; + if (req->rate > r) goto out; =20 r =3D DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); - if (rate < r) + if (req->rate < r) goto out; =20 - r =3D rate; + r =3D req->rate; out: - return r; + req->rate =3D r; + + return 0; } =20 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, @@ -477,7 +483,7 @@ static const struct clk_ops ti_fapll_synt_ops =3D { .disable =3D ti_fapll_synth_disable, .is_enabled =3D ti_fapll_synth_is_enabled, .recalc_rate =3D ti_fapll_synth_recalc_rate, - .round_rate =3D ti_fapll_synth_round_rate, + .determine_rate =3D ti_fapll_synth_determine_rate, .set_rate =3D ti_fapll_synth_set_rate, }; =20 --=20 2.50.1