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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:26 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:06 -0400 Subject: [PATCH 1/7] clk: ti: dpll: remove round_rate() in favor of determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-1-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=2854; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=797B/i7zAYqS3C3fUwjFhBm7v2UlPo/3f5vR7+9WseU=; b=f6AxDfpy+RCAm2k48bLMU6hHsZhiIhyDPP0Xu8DVBbm+SnUO1/phMmAPOVEmJhxdvCZ+PrTeV 420mVDpwyjfC9nn3pdrhSYEiP3VtgDwWcEOhdEyNFp3IV+ZmVRFc1tT X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= This driver implements both the determine_rate() and round_rate() clk ops, and the round_rate() clk ops is deprecated. When both are defined, clk_core_determine_round_nolock() from the clk core will only use the determine_rate() clk ops, so let's remove the round_rate() clk ops since it's unused. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/dpll.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 3386bd1903df6d6cc443c9e087497167682da8c4..1f55554e0d73ca0323459e88231= 25b22623ae4a9 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -25,7 +25,6 @@ static const struct clk_ops dpll_m4xen_ck_ops =3D { .enable =3D &omap3_noncore_dpll_enable, .disable =3D &omap3_noncore_dpll_disable, .recalc_rate =3D &omap4_dpll_regm4xen_recalc, - .round_rate =3D &omap4_dpll_regm4xen_round_rate, .set_rate =3D &omap3_noncore_dpll_set_rate, .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_noncore_dpll_set_rate_and_parent, @@ -48,7 +47,6 @@ static const struct clk_ops dpll_ck_ops =3D { .enable =3D &omap3_noncore_dpll_enable, .disable =3D &omap3_noncore_dpll_disable, .recalc_rate =3D &omap3_dpll_recalc, - .round_rate =3D &omap2_dpll_round_rate, .set_rate =3D &omap3_noncore_dpll_set_rate, .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_noncore_dpll_set_rate_and_parent, @@ -61,7 +59,6 @@ static const struct clk_ops dpll_ck_ops =3D { static const struct clk_ops dpll_no_gate_ck_ops =3D { .recalc_rate =3D &omap3_dpll_recalc, .get_parent =3D &omap2_init_dpll_parent, - .round_rate =3D &omap2_dpll_round_rate, .set_rate =3D &omap3_noncore_dpll_set_rate, .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_noncore_dpll_set_rate_and_parent, @@ -103,7 +100,6 @@ static const struct clk_ops omap3_dpll_ck_ops =3D { .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_noncore_dpll_set_rate_and_parent, .determine_rate =3D &omap3_noncore_dpll_determine_rate, - .round_rate =3D &omap2_dpll_round_rate, }; =20 static const struct clk_ops omap3_dpll5_ck_ops =3D { @@ -115,7 +111,6 @@ static const struct clk_ops omap3_dpll5_ck_ops =3D { .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_noncore_dpll_set_rate_and_parent, .determine_rate =3D &omap3_noncore_dpll_determine_rate, - .round_rate =3D &omap2_dpll_round_rate, }; =20 static const struct clk_ops omap3_dpll_per_ck_ops =3D { @@ -127,7 +122,6 @@ static const struct clk_ops omap3_dpll_per_ck_ops =3D { .set_parent =3D &omap3_noncore_dpll_set_parent, .set_rate_and_parent =3D &omap3_dpll4_set_rate_and_parent, .determine_rate =3D &omap3_noncore_dpll_determine_rate, - .round_rate =3D &omap2_dpll_round_rate, }; #endif =20 --=20 2.50.1 From nobody Sun Oct 5 00:09:22 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C4372D837F for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:28 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:07 -0400 Subject: [PATCH 2/7] clk: ti: dpll: change error return from ~0 to -EINVAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-2-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=1755; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=Z/Z8aNwjy/UKmGQb7dk5/C7R8VIWNkrG3ytaz73rEYE=; b=J9gUf0U1U5jq8sGZEfz6AEmIUDhkUmMSeIZZYSu0dbqaAVuS0vdyu5EjSZOZiuMAUcRlcCwZb Fe8jvzOxIOuDPrsHiJFffOGHuTTuNmlFlQ/8USEG6GDyc4rGrcWmgcn X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= When the requested rate cannot be achieved, omap2_dpll_round_rate() will return ~0. Let's change this to -EINVAL to make the code a little cleaner to read. This is no functional change. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/clkt_dpll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index dfaa4d1f0b64b8e3606d928af7cef701be3fc677..a8c0fc20f791689c74868b98810= b1af2c78b18c8 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -277,8 +277,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *c= lk) * possible, programmable rate for this DPLL. Attempts to select the * minimum possible n. Stores the computed (m, n) in the DPLL's * dpll_data structure so set_rate() will not need to call this - * (expensive) function again. Returns ~0 if the target rate cannot - * be rounded, or the rounded rate upon success. + * (expensive) function again. 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:31 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:08 -0400 Subject: [PATCH 3/7] clk: ti: dpll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-3-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=12349; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=DNZBuAZfcx9FexqFDGC7waIYnaLgayG+z6+X0rCNNVg=; b=jxq1//VKLI2tsa207Bys+TKqhvSir68NtMzcMG/IbDYgfpdvtAKr65MGt26U4gjUylZOT8xdq YgftMLgHZAfBJXXHVWSAeGUxHmLb4bDbuuQ02HOnlTGlBfSZ4OVnkrB X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate(). Part of these changes were done using the Coccinelle semantic patch on the cover letter of this series, and the rest of the changes were manually done. omap4_dpll_regm4xen_round_rate() is now only called by omap4_dpll_regm4xen_determine_rate(), so let's merge that functionality into one function. This is needed for another cleanup to completely remove the round_rate() clk ops from the clk core. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/clkt_dpll.c | 28 +++++++-------- drivers/clk/ti/clock.h | 6 +--- drivers/clk/ti/dpll.c | 4 +-- drivers/clk/ti/dpll3xxx.c | 7 ++-- drivers/clk/ti/dpll44xx.c | 89 ++++++++++++++++--------------------------= ---- include/linux/clk/ti.h | 8 ++--- 6 files changed, 57 insertions(+), 85 deletions(-) diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index a8c0fc20f791689c74868b98810b1af2c78b18c8..2ecd66968af4dce4228cbb33e9b= 7d3378668545a 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -268,10 +268,9 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *= clk) /* DPLL rate rounding code */ =20 /** - * omap2_dpll_round_rate - round a target rate for an OMAP DPLL + * omap2_dpll_determine_rate - round a target rate for an OMAP DPLL * @hw: struct clk_hw containing the struct clk * for a DPLL - * @target_rate: desired DPLL clock rate - * @parent_rate: parent's DPLL clock rate + * @req: rate request * * Given a DPLL and a desired target rate, round the target rate to a * possible, programmable rate for this DPLL. Attempts to select the @@ -280,8 +279,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *c= lk) * (expensive) function again. Returns -EINVAL if the target rate * cannot be rounded, or the rounded rate upon success. */ -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate) +int omap2_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *= req) { struct clk_hw_omap *clk =3D to_clk_hw_omap(hw); int m, n, r, scaled_max_m; @@ -299,15 +297,15 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigne= d long target_rate, =20 dd =3D clk->dpll_data; =20 - if (dd->max_rate && target_rate > dd->max_rate) - target_rate =3D dd->max_rate; + if (dd->max_rate && req->rate > dd->max_rate) + req->rate =3D dd->max_rate; =20 ref_rate =3D clk_hw_get_rate(dd->clk_ref); clk_name =3D clk_hw_get_name(hw); pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", - clk_name, target_rate); + clk_name, req->rate); =20 - scaled_rt_rp =3D target_rate / (ref_rate / DPLL_SCALE_FACTOR); + scaled_rt_rp =3D req->rate / (ref_rate / DPLL_SCALE_FACTOR); scaled_max_m =3D dd->max_multiplier * DPLL_SCALE_FACTOR; =20 dd->last_rounded_rate =3D 0; @@ -332,7 +330,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned = long target_rate, if (m > scaled_max_m) break; =20 - r =3D _dpll_test_mult(&m, n, &new_rate, target_rate, + r =3D _dpll_test_mult(&m, n, &new_rate, req->rate, ref_rate); =20 /* m can't be set low enough for this n - try with a larger n */ @@ -340,7 +338,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned = long target_rate, continue; =20 /* skip rates above our target rate */ - delta =3D target_rate - new_rate; + delta =3D req->rate - new_rate; if (delta < 0) continue; =20 @@ -359,13 +357,15 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigne= d long target_rate, =20 if (prev_min_delta =3D=3D LONG_MAX) { pr_debug("clock: %s: cannot round to rate %lu\n", - clk_name, target_rate); + clk_name, req->rate); return -EINVAL; } =20 dd->last_rounded_m =3D min_delta_m; dd->last_rounded_n =3D min_delta_n; - dd->last_rounded_rate =3D target_rate - prev_min_delta; + dd->last_rounded_rate =3D req->rate - prev_min_delta; =20 - return dd->last_rounded_rate; + req->rate =3D dd->last_rounded_rate; + + return 0; } diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 2de7acea1ea0503790754a5d4b9bcfe42da701d3..d5e24fe4ae3af67907e01055fcd= caa266459eb08 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -273,8 +273,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_h= w *hw, u8 index); int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); +int omap2_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *= req); unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, unsigned long parent_rate); =20 @@ -296,9 +295,6 @@ void omap3_clk_lock_dpll5(void); =20 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, unsigned long parent_rate); -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate); int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw)); diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 1f55554e0d73ca0323459e8823125b22623ae4a9..971adafd9a8bbb17a801260f0e1= bf27fed5e51c0 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -77,7 +77,7 @@ const struct clk_hw_omap_ops clkhwops_omap3_dpll =3D {}; static const struct clk_ops omap2_dpll_core_ck_ops =3D { .get_parent =3D &omap2_init_dpll_parent, .recalc_rate =3D &omap2_dpllcore_recalc, - .round_rate =3D &omap2_dpll_round_rate, + .determine_rate =3D &omap2_dpll_determine_rate, .set_rate =3D &omap2_reprogram_dpllcore, }; #else @@ -88,7 +88,7 @@ static const struct clk_ops omap2_dpll_core_ck_ops =3D {}; static const struct clk_ops omap3_dpll_core_ck_ops =3D { .get_parent =3D &omap2_init_dpll_parent, .recalc_rate =3D &omap3_dpll_recalc, - .round_rate =3D &omap2_dpll_round_rate, + .determine_rate =3D &omap2_dpll_determine_rate, }; =20 static const struct clk_ops omap3_dpll_ck_ops =3D { diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 00680486b1bd06ac653dda0cce186acf68736755..8c51b988a04ff0bfe79f39a7eb7= 727ac2edce149 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -587,6 +587,7 @@ int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, { struct clk_hw_omap *clk =3D to_clk_hw_omap(hw); struct dpll_data *dd; + int ret; =20 if (!req->rate) return -EINVAL; @@ -599,8 +600,10 @@ int omap3_noncore_dpll_determine_rate(struct clk_hw *h= w, (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { req->best_parent_hw =3D dd->clk_bypass; } else { - req->rate =3D omap2_dpll_round_rate(hw, req->rate, - &req->best_parent_rate); + ret =3D omap2_dpll_determine_rate(hw, req); + if (ret !=3D 0) + return ret; + req->best_parent_hw =3D dd->clk_ref; } =20 diff --git a/drivers/clk/ti/dpll44xx.c b/drivers/clk/ti/dpll44xx.c index 3fc2cab69a3fe6cfadb3d6bbb3ff87d434c32e6a..08ed57f181b49d00aa4efd2f18f= 3df000ae3c9d3 100644 --- a/drivers/clk/ti/dpll44xx.c +++ b/drivers/clk/ti/dpll44xx.c @@ -133,61 +133,6 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw= *hw, return rate; } =20 -/** - * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN = bit - * @hw: struct hw_clk containing the struct clk * of the DPLL to round a r= ate for - * @target_rate: the desired rate of the DPLL - * @parent_rate: clock rate of the DPLL parent - * - * Compute the rate that would be programmed into the DPLL hardware - * for @clk if set_rate() were to be provided with the rate - * @target_rate. Takes the REGM4XEN bit into consideration, which is - * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before - * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or - * ~0 if an error occurred in omap2_dpll_round_rate(). - */ -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate) -{ - struct clk_hw_omap *clk =3D to_clk_hw_omap(hw); - struct dpll_data *dd; - long r; - - if (!clk || !clk->dpll_data) - return -EINVAL; - - dd =3D clk->dpll_data; - - dd->last_rounded_m4xen =3D 0; - - /* - * First try to compute the DPLL configuration for - * target rate without using the 4X multiplier. - */ - r =3D omap2_dpll_round_rate(hw, target_rate, NULL); - if (r !=3D ~0) - goto out; - - /* - * If we did not find a valid DPLL configuration, try again, but - * this time see if using the 4X multiplier can help. Enabling the - * 4X multiplier is equivalent to dividing the target rate by 4. - */ - r =3D omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, - NULL); - if (r =3D=3D ~0) - return r; - - dd->last_rounded_rate *=3D OMAP4430_REGM4XEN_MULT; - dd->last_rounded_m4xen =3D 1; - -out: - omap4_dpll_lpmode_recalc(dd); - - return dd->last_rounded_rate; -} - /** * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL * @hw: pointer to the clock to determine rate for @@ -195,7 +140,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, * * Determines which DPLL mode to use for reaching a desired rate. * Checks whether the DPLL shall be in bypass or locked mode, and if - * locked, calculates the M,N values for the DPLL via round-rate. + * locked, calculates the M,N values for the DPLL. * Returns 0 on success and a negative error value otherwise. */ int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, @@ -215,8 +160,36 @@ int omap4_dpll_regm4xen_determine_rate(struct clk_hw *= hw, (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { req->best_parent_hw =3D dd->clk_bypass; } else { - req->rate =3D omap4_dpll_regm4xen_round_rate(hw, req->rate, - &req->best_parent_rate); + struct clk_rate_request tmp_req; + long r; + + clk_hw_init_rate_request(hw, &tmp_req, req->rate); + dd->last_rounded_m4xen =3D 0; + + /* + * First try to compute the DPLL configuration for + * target rate without using the 4X multiplier. + */ + + r =3D omap2_dpll_determine_rate(hw, &tmp_req); + if (r < 0) { + /* + * If we did not find a valid DPLL configuration, try again, but + * this time see if using the 4X multiplier can help. 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:34 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:09 -0400 Subject: [PATCH 4/7] clk: ti: composite: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-4-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=1303; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=d4r/MgwDOiJAMmN6yEZ45olvnlGBMIdC6u8+ioBthwU=; b=ZXYI0k5UF214vcjvF2S5pTp2vZZGvwDBNbWPCyvcQChrwBFslhaaWy3Uye/F5OEI+WDcrXqb3 bukwMYnrZdVD6xRhNkTv4k1shexBAsgCQNHEasZdWAnesixMa26c530 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/composite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index b85382c370f7e49ae320c6c47152a2675ca36645..8cba259188d412fee179efe0ffc= 5df627e42e3eb 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -26,8 +26,8 @@ static unsigned long ti_composite_recalc_rate(struct clk_= hw *hw, return ti_clk_divider_ops.recalc_rate(hw, parent_rate); } =20 -static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int ti_composite_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { return -EINVAL; } @@ -40,7 +40,7 @@ static int ti_composite_set_rate(struct clk_hw *hw, unsig= ned long rate, =20 static const struct clk_ops ti_composite_divider_ops =3D { .recalc_rate =3D &ti_composite_recalc_rate, - .round_rate =3D &ti_composite_round_rate, + .determine_rate =3D &ti_composite_determine_rate, .set_rate =3D &ti_composite_set_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:41 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:10 -0400 Subject: [PATCH 5/7] clk: ti: divider: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-5-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=1648; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=KZev2woXWU9HznU+gcnRnr0OtzfEyHcHVt06Cr6pNMU=; b=9HtWsQuOhfM98X55HNWOck7M08AwApUYonHPDgwcZa8S/UhZwBGL/lFQadP95RXlxeEt3lQtd BZJ3vwA7z0fDwJ7YnZJoOWmOvTB+trUUgK5JvgAJBPVoJnuqf7KVZLm X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/divider.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index ade99ab6cfa9b18e5bcfb616273b5c06637035c1..6f58a0f2e74aec14fd3711d722e= 66b6ecbaef104 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -223,13 +223,15 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, = unsigned long rate, return bestdiv; } =20 -static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rat= e, - unsigned long *prate) +static int ti_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { int div; - div =3D ti_clk_divider_bestdiv(hw, rate, prate); + div =3D ti_clk_divider_bestdiv(hw, req->rate, &req->best_parent_rate); =20 - return DIV_ROUND_UP(*prate, div); + req->rate =3D DIV_ROUND_UP(req->best_parent_rate, div); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:43 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:11 -0400 Subject: [PATCH 6/7] clk: ti: dra7-atl: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-6-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=1630; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=l6XgJ6W7yha/WW016u8LdUqKQRLgIir6odjd16bnNlg=; b=n2iLjG9nS7jOmK+UVJevc5Xa5r8KpCC7ggEeWCcVvPhhhsGoThO6dmi5mnXDQ7f0SjWodiNh7 OICvVHC6qGwCevKiZrShkiskzIyE+56+lWC/ZlUJVesZbHlGF3hDgyy X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/clk-dra7-atl.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 0eab7f3e2eab9edb18a5f881ce329db1abdb5be0..b02f84d49b966ec0e14a4bf89e3= 9306048b964b6 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -120,16 +120,18 @@ static unsigned long atl_clk_recalc_rate(struct clk_h= w *hw, return parent_rate / cdesc->divider; } =20 -static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int atl_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned divider; =20 - divider =3D (*parent_rate + rate / 2) / rate; + divider =3D (req->best_parent_rate + req->rate / 2) / req->rate; if (divider > DRA7_ATL_DIVIDER_MASK + 1) divider =3D DRA7_ATL_DIVIDER_MASK + 1; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4aef746b6efsm138724001cf.15.2025.08.11.05.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 05:48:46 -0700 (PDT) From: Brian Masney Date: Mon, 11 Aug 2025 08:48:12 -0400 Subject: [PATCH 7/7] clk: ti: fapll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-b4-clk-ti-round-rate-v1-7-cc0840594a49@redhat.com> References: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> In-Reply-To: <20250811-b4-clk-ti-round-rate-v1-0-cc0840594a49@redhat.com> To: Tero Kristo , Michael Turquette , Stephen Boyd , Maxime Ripard Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754916502; l=3724; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=35dv85IMLqZUQXMLmdKz9Cv7IO7JQIrFzXOoEzRX50w=; b=N25Ia/p/HvCELWsArvVY0UtQVgJ3XAaJSxes8tGYmI13Fnbu/6iFvl8iKyxqGdFoqRprtooUL btcrwmBZrFsDgLojbWvoFnBiuu79baJzYrO8uPhWQ0uNx1ED+hva180 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Reviewed-by: Kevin Hilman Tested-by: Anddreas Kemnade # OMAP3 GTA04, OMAP4 Pan= da Tested-by: Kevin Hilman --- drivers/clk/ti/fapll.c | 48 +++++++++++++++++++++++++++-------------------= -- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index 2db3fc4a443e052722d5c01e5ef38cc1417d818f..4f28138d2d8abfa63e13c23d6a7= 326f3a2cdbf86 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -214,24 +214,27 @@ static int ti_fapll_set_div_mult(unsigned long rate, return 0; } =20 -static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int ti_fapll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { u32 pre_div_p, mult_n; int error; =20 - if (!rate) + if (!req->rate) return -EINVAL; =20 - error =3D ti_fapll_set_div_mult(rate, *parent_rate, + error =3D ti_fapll_set_div_mult(req->rate, req->best_parent_rate, &pre_div_p, &mult_n); - if (error) - return error; + if (error) { + req->rate =3D error; =20 - rate =3D *parent_rate / pre_div_p; - rate *=3D mult_n; + return 0; + } =20 - return rate; + req->rate =3D req->best_parent_rate / pre_div_p; + req->rate *=3D mult_n; + + return 0; } =20 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, @@ -268,7 +271,7 @@ static const struct clk_ops ti_fapll_ops =3D { .is_enabled =3D ti_fapll_is_enabled, .recalc_rate =3D ti_fapll_recalc_rate, .get_parent =3D ti_fapll_get_parent, - .round_rate =3D ti_fapll_round_rate, + .determine_rate =3D ti_fapll_determine_rate, .set_rate =3D ti_fapll_set_rate, }; =20 @@ -399,14 +402,14 @@ static u32 ti_fapll_synth_set_frac_rate(struct fapll_= synth *synth, return post_div_m; } =20 -static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rat= e, - unsigned long *parent_rate) +static int ti_fapll_synth_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct fapll_synth *synth =3D to_synth(hw); struct fapll_data *fd =3D synth->fd; unsigned long r; =20 - if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) + if (ti_fapll_clock_is_bypass(fd) || !synth->div || !req->rate) return -EINVAL; =20 /* Only post divider m available with no fractional divider? */ @@ -414,23 +417,26 @@ static long ti_fapll_synth_round_rate(struct clk_hw *= hw, unsigned long rate, unsigned long frac_rate; u32 synth_post_div_m; =20 - frac_rate =3D ti_fapll_synth_get_frac_rate(hw, *parent_rate); - synth_post_div_m =3D DIV_ROUND_UP(frac_rate, rate); + frac_rate =3D ti_fapll_synth_get_frac_rate(hw, + req->best_parent_rate); + synth_post_div_m =3D DIV_ROUND_UP(frac_rate, req->rate); r =3D DIV_ROUND_UP(frac_rate, synth_post_div_m); goto out; } =20 - r =3D *parent_rate * SYNTH_PHASE_K; - if (rate > r) + r =3D req->best_parent_rate * SYNTH_PHASE_K; + if (req->rate > r) goto out; =20 r =3D DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); - if (rate < r) + if (req->rate < r) goto out; =20 - r =3D rate; + r =3D req->rate; out: - return r; + req->rate =3D r; + + return 0; } =20 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, @@ -477,7 +483,7 @@ static const struct clk_ops ti_fapll_synt_ops =3D { .disable =3D ti_fapll_synth_disable, .is_enabled =3D ti_fapll_synth_is_enabled, .recalc_rate =3D ti_fapll_synth_recalc_rate, - .round_rate =3D ti_fapll_synth_round_rate, + .determine_rate =3D ti_fapll_synth_determine_rate, .set_rate =3D ti_fapll_synth_set_rate, }; =20 --=20 2.50.1