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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:56:12 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:43 +0800 Subject: [PATCH v8 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-11-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7534; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=7EU0MUNMGUJfOI70oZadjXP+yGDc8z46FXbU6drpbPk=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZC6wZUizMlp44vG9N8fgHrmYBEokbYHmv5/ m1ohHgn6jaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QgAKCRABygi3psUI JCcXD/9u9KrmKwCUE/ua79BFz01euFukCva1OyKZuybT6Wws58o6HyQLmJdlRZA9sLvTtaE4Xoq RRlxAdVipa8N8U1YeVx/wNYXA9pOtvFCwDMefDrwu4L+eZueXvFae3v8+W18H3VIX8bQ5osiU6s t1mDW3P776kF3FX3T3v0x5C/0m8Kgm0a6K+P6vBViqwOPl1RkdYND/tMpmbkEtVH7y+n7jWfPAZ IC3yYdxkgjhExQV8PsOmS4oPI45etcW/3BHI7RFqHxt8YWeE9Z64YB2sdf5SkglNvIL2QVIWn9t evt+DwCeotfxjbPlNPzJ4zzR/xyz8gB+s8W63DZSQQLCxTJN+prpQ1C+u5K83XZE0Tk3wGIsE7t 0rrjWYQ9F0DMFxJe86HmeG5HXz7hKcHeJK4gNZNoE/dKgjh542OzLRdAO+PszBkakQI6inl8ttZ wOA6wMhBA5MnmFWdnC8wH3pwbz6+yV+3lGS9MjHp9e8ZJhEjKgVxdlmj52470lXlmwifL86tHuH JSZfflgDwiUFtK5fHHWzJ1unx25CzM/z6linXblUMBund/8mo6dNvNoeQb6719d34Ese2Lb7n2q HhLM40pwVCYVjazeEcKmc8ojFNipQWkOnNItzcBEHtxGlncYmc6aupFxV9paUpoRTmXiOXqqrP7 NbXTe702qNhwSgw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Tested-by: Ivaylo Ivanov Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index bfaf926fd47b02a7d77ac31cbb97779b5ebedec4..37ca7e99aaad97526c468d3c98e= c7ce4fe115763 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR= _LAST + 1] =3D { [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A10_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A10_PMU_PERFCTR_MAP_STALL =3D 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A10_PMU_PERFCTR_INST_ALL =3D 0x8c, + A10_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A10_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A10_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A10_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A10_PMU_PERFCTR_INST_LDST =3D 0x9b, + A10_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A10_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A10_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER =3D BIT(8), + A10_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A10_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -905,6 +1014,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events = *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } =20 +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1105,6 +1220,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_fusion_pmu"; + cpu_pmu->get_event_idx =3D a10_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1154,6 +1280,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, --=20 2.50.1