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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:25 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:33 +0800 Subject: [PATCH v8 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-1-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1102; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=5SPeH4B0HCgQ3mPJQ2F9oSAh7NyxBKYYgDF4wIcu5t0=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZAO5K+imeOa8Dg5N4+Q+5ghWt5CcWmhnuwD QW3eaYi3JuJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QAAKCRABygi3psUI JDWKD/9QBGFFlKRW8463W701zQkmmFBupQgVn7DNzI60gxpZrl6zbdgY0GYMCNYZghcz2jbhOUY XechMJLG/nhbRUvM3SunUisReUoZ8RyOdd8+hQNLPGt2raNZnuw3AJlC9mse+vpTFAiN7r3bPFk cndw31xaSCtRKxcFjtIuD6zrasEzIkn5gHPwhgj/4n8lkbVB4J0YqVCfJooAUcG/Wmx8eSuXV7E a8bRkvIiUJ5vzDjGfP78bhbk2rjhPIvzSov4UJeZUo67a2HC2LDDUg0NV9kFVVlFabbjD8Dtb3A dBnkNy1+T5faRIhDNnxCr06QSMX56SqE4MHLWXaS2zEwzQnFcBhy/O8oyihWbIqOGEmAiJ0I2a9 m+jJ7xchh4jFo8We8SiXdc5vZe8QZqWlXoq8/BVnEAZpf5BXEkYQYJXxs2pGBqNUj9Cvu/cJhUc QwohgEye2EijPCbmT0TvQ2ouzjnXiQ9zC/O/LmCqtOlSW98buKEBPC2G6NrPlys0PWddBLe2xZB k7CHuuIDoWij9kxdtvLDC2wFovfWrlDIoHK8jjgOh77NfB7KMJNdQCvMVPrJoKozyFJZHtXYFLt KSDOTS9NxNP4jvcP6sVcaaMKs3rgze7vdbKAeQC0IHAHrsu6RgsIe53F/wfuW0E2CRDzIAREf1Y LB0pE1lHU/YtNoA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Document the compatibles for Apple A7-A11 SoC CPU PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 295963a3cae799a54560557137dd6b3cf4bd00f9..3726e1b78c42f150cf1dc68a6b3= aa3541517c311 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -22,8 +22,14 @@ properties: - apm,potenza-pmu - apple,avalanche-pmu - apple,blizzard-pmu + - apple,cyclone-pmu - apple,firestorm-pmu + - apple,fusion-pmu - apple,icestorm-pmu + - apple,monsoon-pmu + - apple,mistral-pmu + - apple,twister-pmu + - apple,typhoon-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F7C2236E9; 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:30 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:34 +0800 Subject: [PATCH v8 02/21] drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-2-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1251; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=/PeiCZRRXTs+WYDUarH1jFdEbam99TBMronNZaQIczY=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZAjJ6DSFyNEbqI7WQb0Cs1/cpoqcmkC5M9x edA1YRSzTyJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QAAKCRABygi3psUI JAlRD/sH1t2xS6IlKyOl1wO70gblqwbM1KqyPFJvf1yS37xaYtta2EkTYwoDnFJRADzM4QOucKk EuCEThPdttD95EZUcAjkRVe+c5FInsMfLCUlOnBzOXh6pI7mU8f2l7On2mMyuRR35Nnj5dI1ZqN l4Xozo6NtcqOHGkO2In7dkEqrTaiBUFzxdkux/24RHK2LgD5KvuFi/v2PL+IgSxWtB4NcZ3pZGe q2xTGJA8h31gqwrZSAhU8NZdDFEqa6vIXJrbuqU3KEXB2xFoBXo07TvFDIBsdX/xolnlcSse+G/ 85NbGGinRlTvj71bYqnYES0DChPgkFHyYdFgevzSPIn8jU77Czue3U17LRln3D0yhQkTW1UIJ+7 jL/N4QyZj2sHTMqcFIyqtA0QA4HaR+vNf0sSnYVpcv5+suUB1Q2H0LAOxhp/3GpboWnBnX5gi4o sWCHwFDJHbuEQyjfKFZYLoKpC6CwfYDZKt9RRxjbwwcZn/0wb2YzTVU46pgsEyuQliProBHsmyA MttHNUmZxVqRt7qJt8eVNu86C3ZFZr+mPqeOa2Hd32VVqXsuGPKN1iLkhKDZbO2BdctJdCyhykG lAJLxrUwg9aSmiXbsAIFyhpzqSAJlh0UBDKn1GH3sD5h4NmbdbX2msqe9IhVZwvtXLQ2kr62VY5 oFjjgMuO95pcYYg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 The events in the Apple A7 PMU is very different from the ones in M1, and EL2 is not available on Apple A7. Instead of assigning the wrong PMUv3 remap on A7 or declaring a new PMUv3 remap that would never be used in practice, skip initializing PMUv3 remap altogther when EL2 is unavailable. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 81b6f1a623499566ef04d04075752f34e2cb6a92..f3948528e28e0189efd0f17fde0= d808930d936af 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -645,8 +645,10 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 fl= ags) cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 - cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; - m1_pmu_init_pmceid(cpu_pmu); + if (is_hyp_mode_available()) { + cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + } =20 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC7521ABAD; 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:34 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:35 +0800 Subject: [PATCH v8 03/21] drivers/perf: apple_m1: Support per-implementation event tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-3-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5769; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=L2YMsQakHXAovXEtkfkDoO7BcCisDs2noWQ8gSGB4P4=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZBqHdal0BAjjTgQbH52DWluytNz3S2xTEzC s+6fQn6qcWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QQAKCRABygi3psUI JCgbD/kB5IrVKa5WSvD4j+qzCZ7IawmO0u+5y8zwKQrp3Qyl20OdNTRrtAbErhIf8BBRuDBafU5 abcoH+dUwb5fmQDxo13ZdulVpVqNPxXKXYGhuvaeWyDieZgtp3SHYV/3mEcSHSZZSYwftYJ9Dxo vTtlKLK2JDHXr7R15AKZKeuB4I6c34p1Lpz+1mS5iXpFNFDha1R2/kuMjpLS6BeoTggUEfmJ8cs AHJviwFNEproj3Gff+DIx/AgroktT5t39QtvFBH9F/viiQbob26YBLvpX6UIvtl2ehZSHSG6r4Z BduXTZkZUldXe/lgJGVm21+46O1ma9s0kjJMwfODiFF9cQn0oNWIRk7f1nLGs1zNKkiObNH+2Bx OUD0etGDV7JNe/I+m6yUB7EM5Tj+EftkLtS5JIGpjDeYMnmV4LlgJJbe4jl+DGqsb1el9RrkC9r t+0Gfj7KJAGLqZmm9fxcf2O9bE1FJakg4C0GbWSh+hvI5OKHYhjUrGOp4qMkXABdXDtAr2pDKWx evpuRFx0ooXSvcvY9iocDHa7RFg/sd1nzCJsh562luG3BTWGl4CQwQwz+PJ0FlvZOlnahz1g7Jt 7Q4WC5e0/IH8Se+4i/wqx5X6ozCiJ/2ElxFraD3muszE90l7Lc808eMPD5E9WJ0c/SinlQty6PI l1LUXwR9E9qJPEQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f3948528e28e0189efd0f17fde0d808930d936af..b4ab6a3e5df965b7ef450d7e533= 995f3cc8633fd 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, @@ -493,11 +490,12 @@ static void m1_pmu_write_counter(struct perf_event *e= vent, u64 value) isb(); } =20 -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[]) { unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + unsigned long affinity =3D event_affinities[evtype]; int idx; =20 /* @@ -516,6 +514,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return -EAGAIN; } =20 +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -543,7 +547,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } =20 -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -551,18 +556,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |=3D ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |=3D ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } =20 static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -623,25 +639,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_eve= nt *event, return 0; } =20 -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; cpu_pmu->disable =3D m1_pmu_disable_event; cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; - cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event =3D m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event =3D m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -660,25 +667,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 f= lags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FE9021A457; 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Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b4ab6a3e5df965b7ef450d7e533995f3cc8633fd..b5fe04ef186f04b4af32524fe43= 3afb79979b791 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -20,6 +20,7 @@ #include =20 #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 =20 #define M1_PMU_CFG_EVENT GENMASK(7, 0) =20 @@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cp= u_pmu) =20 regs =3D get_irq_regs(); =20 - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct perf_sample_data data; =20 @@ -506,7 +507,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events= *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -601,13 +602,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu) } } =20 -static void m1_pmu_reset(void *info) +static void apple_pmu_reset(void *info, u32 counters) { int i; =20 __m1_pmu_set_mode(PMCR0_IMODE_OFF); =20 - for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i =3D 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -616,6 +617,11 @@ static void m1_pmu_reset(void *info) isb(); } =20 +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -639,7 +645,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, return 0; } =20 -static int apple_pmu_init(struct arm_pmu *cpu_pmu) +static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; @@ -649,7 +655,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 if (is_hyp_mode_available()) { @@ -657,7 +662,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) m1_pmu_init_pmceid(cpu_pmu); } =20 - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; @@ -669,7 +674,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_icestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -677,7 +683,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_firestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -685,7 +692,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->name =3D "apple_avalanche_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -693,7 +701,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_blizzard_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:44 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:37 +0800 Subject: [PATCH v8 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-5-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1977; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=xtnMIatmASrpTNqfCZXR2dLamBkEP1A2TcLh/eTOrpY=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZB/dg/RHdFjAxNBqXHOldYRPqycv+vcx/Ez XyK2llBy8eJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QQAKCRABygi3psUI JMVfD/45BRjXAHLm5YqyfCfUhQP2PwOD1WRl56SyuyNQv36fUcBNpM/ERYzgfNT1UoLpos1chxh lehGTKQAJUZY2OwIs279qILgKGXBRqlpaXQVsUcnNsm5TAagvITimAxTIRnwC4YF0mLRO9cN0wz ZzOxVaSGztxeVB2IKT40AR+3Gwomx6rg4ZSM49NzkdPuRx/2D64MUlpC8Jpa+zIr3IbAiZfzP/O gLAAJ2BwnTemgwz8++KFJw60xaIOm3hNJZW1clw2oFwlehs/UU+XrFwddK5Dq1hnGk45x4Yqhc7 8481K4CeD/pSxQqthFg08WziwUIk8oTznh6O02NpE1iZgbKHzEelS4vOC5OEPbLvfOIGP+5h34O GhLRGVDu4unyIjoGtzBNpsEgt2VA8+zrAz5vGhudSimkZM8UF3Lt11vY9IQyLpaq7H3oEjc3RiR X1juNO7oCnP59Zve63U2bqa9Tro0OSb4msi6e3XiOrV/czprHQA1EFGQ3F7skVOBstcKajJwN8n lQowfiEbdPqonyh0h8MUvtwSSifc9K7P9078aHUlOtztScyZK30Q9hvHsY7xi2nMe85sm1FRGZ/ GQwV1HuOs8Jw1AJpX9L7jXM9qXFEZZfIP75Nc+UcGIahVsjtB18Vw6EFwVWQopg9EKMpvaTZp6i YSGO4GAp69cwg7A== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 2 ++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 02e05d05851f739b985bf416f1aa3baeafd691dc..8a667e7f07a517419c22a4f9309= 47347be8546f7 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -38,8 +38,10 @@ =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) #define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) =20 diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b5fe04ef186f04b4af32524fe433afb79979b791..fb2759069fe9e47146f0342fa46= e40f3ab836926 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -348,10 +348,16 @@ static void __m1_pmu_configure_event_filter(unsigned = int index, bool user, case 0 ... 7: user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:48 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:38 +0800 Subject: [PATCH v8 06/21] drivers/perf: apple_m1: Support per-implementation PMU startup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-6-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=MBYkOMp8zRY3vG74r0/6XW89V1iPdN6l9V1/vB4q2xk=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZBt0TVBcxz/c5qr7JmkQBF5U88g5YmXrAFU 387FXSG2faJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QQAKCRABygi3psUI JMdqEACWf9cYzVRAvPO4kE63gH5ewqMqVwB6jD1J+tfwEiXp+Fr7BHWs67QTeMB1RvNG3dXs+zx 8LYbi7RNJ9O1fpDHGdrxl7GREHlp3U7Fc1GpP4OZJS68TxsDbB+tPSy/i6lGK1H8E3zJvQ1LlXu Fl/WZQI7Qfx9lR5WoTjeV3PjAGmCWjj1Kvuw9tA9ortgG5KKU8uST4yxb/hwdTIJiRFoz4rwQsB oBuaimMRGBFV6z2vC7N+B18V4+kOFiwLzl5Up3okjP0C4OcSMA6W8kBrnQoVGHnjHr//s6cmSBT 4woRXP0MQkbu4ueQhA/fgJCub55EzKWfxIA0IgdmE9xHoj5mrVIsAt5WiAHiSgSXqFmO7AzqJcT fLgvZZJjddkfFJTsvGZ0TPOeUvBGOUcK0i85bpqdTpd2E9MdFBNxlrtDwmny1o6oo527I/7msbd 3nWgozb0k5bRBgQgadcrYHbZyWSQY8GdCQJEgpe86+uwMiLAR81Xn5SVcaRHz2ckmixDJhNTIqZ ds2iEckJkQVKP3BW/Dp1ptrx0n4SHqi590VzWSRdCSOjIXuEPJd17F1uFU4u+aBsS7C5KFmloed dGG8Eg1ZZmZZYfHmtNXIPpK014nExmv5LchT02piUGLTv5xkfxsNgQlnpjhyN4Uep2iZi0lOLtV 5J9LY8BGXyzbHTQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation startup function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index fb2759069fe9e47146f0342fa46e40f3ab836926..303c0e62432281e899a33fc1973= 65c70078d6ac1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -659,7 +659,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; - cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -681,6 +680,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -690,6 +690,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -699,6 +700,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -708,6 +710,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 508702D3228; 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Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 303c0e62432281e899a33fc197365c70078d6ac1..d0362a1813788776f4210523efe= 33a3018cfef2a 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -668,7 +668,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) } =20 bitmap_set(cpu_pmu->cntr_mask, 0, counters); - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; } @@ -681,6 +680,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -691,6 +691,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -701,6 +702,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -711,6 +713,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FD9B2DE718; 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:55:57 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:40 +0800 Subject: [PATCH v8 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-8-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=+LJO62oOzNOE3W3QjbhqRWaYWvRbJogCNl2YzLIGJDM=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZBkx5s7RXQXmDlTeJTFIVAfIwR+nU8o+5ef 1flYi+l8BeJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QQAKCRABygi3psUI JA7uEACZFAUWLVhZKPGWt7tBn0+XI+y5gRUC4olpNQoLLxXMLtZbPzViF4gu4hIKTSligv0k1NY r4lIfI3VPKxI/wr/vJMveKvroMRJv+xTDcilLTk33/Eew3TMXHGTflVzA49WWxZGCVg3RE+wSHX g1f4zir9+Wsop8/RzjXHnMHiKf13EYJNwukw1aSYt1aQV8RAsxSOlfsDkIfOMuz/eN+CH0XxRR+ 2sSTfqPNPONQrvhVbxTzEZJOWhXwCFMefdhFUzR5r5PvE22p0fIOP3mYkFZgdOmiTg5ZFdq2xCj f2ndVkY/YyOE4nmmORJrQUhr+Zd7fUNrk950eymuHRdtjKMq9O81+pev+KjIIejp0rSEbnrqxFU 7ov05jEm6q9kCsnJU/XPSH+TMwk2qsHQB0n/DjOwMtgo6KPmgkHFPc3QVsnPk2VKZdXFyIqem6t IlEa6J6ErYxaGMKqOOgN+0pRrmJf9JtqZXskThwx1rmy5VxCBc/ZfQaVGzEbiwAH62PjJYw+rmJ bXvVlxE/5HzGmf7KHQwJFXr0Cqty7TXdwInWJZtSZkCZfHR2LGXYLHVSHBerlhTivvg8V/m5ewp 6k+qxj8vmr/gS0+EnL1ONgm1Rv0UFkeO63194PnQIZmaqig8oZZIRuBwjivD09tfnDNg3hsVeLm aTviJzVkT0ilYqA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index d0362a1813788776f4210523efe33a3018cfef2a..afcf7c951379698ceff21c1a99c= ca31b3a6177b1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -521,6 +678,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,6 +707,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -578,6 +746,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -623,6 +796,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -673,6 +851,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:56:02 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:41 +0800 Subject: [PATCH v8 09/21] drivers/perf: apple_m1: Add Apple A8/A8X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-9-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7370; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=pymodVDjkymPU76ZXTw5IlzwIXD4zHyf40Nqmh2xgvg=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZCk9q7xCDfJfHyIhHmrzPcKLWCM4sEUP9ny RZcIOvQ8BWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QgAKCRABygi3psUI JJc1EACthBI9pB7MbMAQ77EjqRD9DESUe88v3f1lQ7fJxO8ZC6W5O+cy7MbnNviP4isZRLzR17L GxvgHm2VGdAROVsjB8YteDkSM1/dcNtBUUjMXv1HaYzoWa+4cue3gRa4ZndNLrUxmK2Ne9hAtoN pxIgu3t7dr2sBj8CqpLBSIJlnL0dNq9Ti8ePwZ4cZ9HhnvfckVFbH0EIanY8teS5m3lypCAZ8fP FGeW7BDKB5aXuoc6nv0GbFO+5qNZFxbgM6zNGPdQzx9PxQecb6BG6G2u/YkUW4izGhAY3xmFjH2 jG9gNn2bE+eMyeRq6Lut6nBEqXCCyR182wIJGXVt21PRvlLdhUoRtVhOo9Qlx0zpy0UMeJ7lDXT SPbbzFW/xYu4dZSbI21LqhYrHGqgUngRDKf52NZdeKW2/rexo7Z2cWc6L6vMdFoqyUksqHnc4WA x0css5LfEmpifUcVK95X7zQZzMU00cyjap7oN1h//J6LRNDRvqbIgIO+eTVvSVQlLTQQ5vDSszr 5HXwhpOf7NcZt8757Z85P74WsCGpEfBex2LiCumZEabmL+Ylg+gG8NqW43TjCtrpXoZIswS2v2R lpoa0KVaf5MwV0Xxq5TrCDSsZ0GUMKGeuUeTyhlLGiizwE0IaZeqpplibNmy5D6QITKrKM6tH5Y MgDadfxsR/XJs3g== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found on the Apple A8, A8X SoCs. Tested-by: Ivaylo Ivanov Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index afcf7c951379698ceff21c1a99cca31b3a6177b1..a95f4b717857b30284470487827= 954dd4b139010 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -28,6 +28,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) =20 /* @@ -183,6 +184,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR= _LAST + 1] =3D { [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A8_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A8_PMU_PERFCTR_MAP_STALL =3D 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP =3D 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A8_PMU_PERFCTR_INST_A32 =3D 0x8a, + A8_PMU_PERFCTR_INST_T32 =3D 0x8b, + A8_PMU_PERFCTR_INST_ALL =3D 0x8c, + A8_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A8_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A8_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A8_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A8_PMU_PERFCTR_INST_LDST =3D 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A8_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER =3D BIT(8), + A8_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A8_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -684,6 +790,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } =20 +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -862,6 +974,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_typhoon_pmu"; + cpu_pmu->get_event_idx =3D a8_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.56.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:56:07 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:42 +0800 Subject: [PATCH v8 10/21] drivers/perf: apple_m1: Add A9/A9X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-10-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6996; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=WuH8YXRWTDJpsqx0u6Hpuz6usLUPET5IKer40y1frRo=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZCWmCfZi0x4WcuwRWfWR4pOc02bLS7TmsfL GlRiMrv7nOJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QgAKCRABygi3psUI JJn1D/91gQc72s2uw5Y5vyAn0IW141NhTedP0ezv+UN3wQRDjh24MDb4xQxbdcBazJwPXipXDxI GaqOBQc583X5WTStNAPf+Hff50R9rU17Z/kVAOdWWqnq3VCr0NgKtuehp5SRGoLuAIzHV66prVp T8T3r47HlezDyQLKePPsfp0gXgQ4h+U+jbmF1bVYf3gXFU4enRIpAyhu5Yg5WkLkcNNZwyz6Fe5 uQpOpd1GengoRjYcGi6GuMNFCXdefj8vJq/PIh739lm7STOxxdLXYZwFlEjD5VbqqknbB99AEvu tpC99OVSHPBVnwkH60UjRRvWEoUf3HqfXpVD56nX6wpLSM2P7TYVKiACXwa4zV1+bpr1UHmRv6M Lztt9AmX6t8ClmJZNyRhqASGtWMazZTuj6TdOQFHAzRmXU7Sq/HDOSEsHroIHzgo5LCZffDxv13 BaWgsAXSvsH+NnmKkX9AinEou258uOEYtLKpb5xy4q/Ha7hzMSro11VYOaHWgT0S+whjlcVDnkY mOkiilhsyWSEjfkcRO54lhuAkZitWxtIkq59ZdUfDeLqOxx1WfzuomCeOx63MNPWTS9KC0Y2bI4 EB/VKO3f5qiXbeRNjwzCRh+xFh55jZp4/pqXeyiCW/wqguATfYF43USFsIjR8E2+dh0W1yFtfhH Kk1K1DOfkBLqmvw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index a95f4b717857b30284470487827954dd4b139010..bfaf926fd47b02a7d77ac31cbb9= 7779b5ebedec4 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -796,6 +899,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -985,6 +1094,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1034,6 +1154,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D0D82DFA54; Mon, 11 Aug 2025 13:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:56:12 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:43 +0800 Subject: [PATCH v8 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-11-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7534; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=7EU0MUNMGUJfOI70oZadjXP+yGDc8z46FXbU6drpbPk=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZC6wZUizMlp44vG9N8fgHrmYBEokbYHmv5/ m1ohHgn6jaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QgAKCRABygi3psUI JCcXD/9u9KrmKwCUE/ua79BFz01euFukCva1OyKZuybT6Wws58o6HyQLmJdlRZA9sLvTtaE4Xoq RRlxAdVipa8N8U1YeVx/wNYXA9pOtvFCwDMefDrwu4L+eZueXvFae3v8+W18H3VIX8bQ5osiU6s t1mDW3P776kF3FX3T3v0x5C/0m8Kgm0a6K+P6vBViqwOPl1RkdYND/tMpmbkEtVH7y+n7jWfPAZ IC3yYdxkgjhExQV8PsOmS4oPI45etcW/3BHI7RFqHxt8YWeE9Z64YB2sdf5SkglNvIL2QVIWn9t evt+DwCeotfxjbPlNPzJ4zzR/xyz8gB+s8W63DZSQQLCxTJN+prpQ1C+u5K83XZE0Tk3wGIsE7t 0rrjWYQ9F0DMFxJe86HmeG5HXz7hKcHeJK4gNZNoE/dKgjh542OzLRdAO+PszBkakQI6inl8ttZ wOA6wMhBA5MnmFWdnC8wH3pwbz6+yV+3lGS9MjHp9e8ZJhEjKgVxdlmj52470lXlmwifL86tHuH JSZfflgDwiUFtK5fHHWzJ1unx25CzM/z6linXblUMBund/8mo6dNvNoeQb6719d34Ese2Lb7n2q HhLM40pwVCYVjazeEcKmc8ojFNipQWkOnNItzcBEHtxGlncYmc6aupFxV9paUpoRTmXiOXqqrP7 NbXTe702qNhwSgw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Tested-by: Ivaylo Ivanov Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index bfaf926fd47b02a7d77ac31cbb97779b5ebedec4..37ca7e99aaad97526c468d3c98e= c7ce4fe115763 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR= _LAST + 1] =3D { [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A10_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A10_PMU_PERFCTR_MAP_STALL =3D 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A10_PMU_PERFCTR_INST_ALL =3D 0x8c, + A10_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A10_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A10_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A10_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A10_PMU_PERFCTR_INST_LDST =3D 0x9b, + A10_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A10_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A10_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER =3D BIT(8), + A10_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A10_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -905,6 +1014,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events = *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } =20 +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1105,6 +1220,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_fusion_pmu"; + cpu_pmu->get_event_idx =3D a10_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; 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[61.92.221.177]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-b422bb1133fsm23585496a12.56.2025.08.11.06.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 06:56:16 -0700 (PDT) From: Nick Chan Date: Mon, 11 Aug 2025 21:54:44 +0800 Subject: [PATCH v8 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250811-apple-cpmu-v8-12-c560ebd9ca46@gmail.com> References: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> In-Reply-To: <20250811-apple-cpmu-v8-0-c560ebd9ca46@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7991; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=GbBsZLU6LcYQItYH6LxeFjqfhzMXOcLKbuyFdqUdTvA=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBomfZCUK0/mVTyMsN2St/7DA8ARfUMHWvopG0+u O+Dy7fxsiWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaJn2QgAKCRABygi3psUI JD2FEAC1DkjcxnKa4tNZY0hTXM3G3PvJhM2AfQqKho1vRKqXkKCx8y6UBVTQCpp+Q2nGJCrG3zF /PiHoDRFKcwTPuqpZ4XzsqVlpdXU8fTITTHA6kNCW7HVHSIrZjthof2v8YQbvkjpZdb+XSWlxzd s/Jw8xIYKPaCcDY9nmgpqmm5/XAz1ZYE7VXJzZ+rDnrPFBRt7PjgxQQDC1lxnnErhGprSPvosjX 0sHCKiiXwbzMNOL7OgkA3VDfPBdalkvNvd2PSPfZKEmibdZYUaIWnHn+mfvJkEMTRr6dqrHZMzS onJ+Nlu5M7AWFdteP/zNUAVtItpwysP4BfGA0tuov4mN2SI3cT5LIROmOPEeXh1Py/szmXFJZZW M95d7VsZ/sWYu2/Bf/zvH8jZVCCBMfSlpy0vF9FtpCcxXHkCT01/7okBPfCM/pJsUr61TeKiqer 3nahI0PS9oPjUNSaUyb2Y99jv1GsSHZJ0xA54hS8pGcZylatH3SZ9dnGKwqn2tvMAaOieZt6Eng GLOtJ/6Pd7iI0jjOrbEvYRQyKHSNZGgjkKRS6mR8l28oAUAGigt51jiNxI9Mn9zPnRQMFXAhf2F t1erQfH/52WxQ86Y7creW3cdWws2EGDOe2sOVGBHrhxINrkEYZE9BhbnF5tsib/wnbiWhx1HjWO TAQwP8nKbkv5unA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 37ca7e99aaad97526c468d3c98ec7ce4fe115763..31fe89c928364719ee0d7101128= 6a91adaf6b99f 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_A32 =3D 0x8a, + A11_PMU_PERFCTR_INST_T32 =3D 0x8b, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1020,6 +1127,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1231,6 +1344,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1280,6 +1415,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B096D2E040C; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/= apple/s5l8960x.dtsi index 5b5175d6978c45052ded495fc0d18ee3a8fbfdcb..1a3a90f7b9ded42e371ef0b4105= 7fd3081579615 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -151,6 +151,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,cyclone-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s5l8960x-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6BA218AD1; Mon, 11 Aug 2025 13:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/app= le/t7000.dtsi index 52edc8d776a936ca5ba58537d4d68e153023f536..98c41473a84098bd70df86c2728= a8080b05b41f4 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -206,6 +206,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t7000-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F1F82E093A; Mon, 11 Aug 2025 13:56:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index a2efa81305df47bdfea6bc2a4d6749719a6ee619..0e414018f5acbcdb10db92bec6e= 26ba32e53c781 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -199,6 +199,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t7001-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED04E222596; Mon, 11 Aug 2025 13:56:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/= apple/s800-0-3.dtsi index 09db4ed64054aefe5b8f8298553d87fe5514e81a..bdb66f7e0de43a6a751af37c9ce= abba44ef907d6 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -180,6 +180,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s800-0-3-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BA112E11B0; Mon, 11 Aug 2025 13:56:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index fee3507658948a9b4db6a185665fdff9f5acc446..ee2702fc807b678023915f72b52= 76cc5a31e1222 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -222,6 +222,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s8001-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24D9D2E1720; Mon, 11 Aug 2025 13:56:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/app= le/t8010.dtsi index b961d4f65bc379da3b215ca76d5f68691df06f4d..d187fbf7e7a214cbbc1027034ef= d0724ef7f8b83 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -256,6 +256,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8010-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13DDF2E1720; Mon, 11 Aug 2025 13:56:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/app= le/t8011.dtsi index 974f78cc77cfe28d3c26a52a292b643172d8f5bd..ac203ac4d6eca75655cd590deba= 5c361accf2375 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -253,6 +253,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t8011-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D8C62E2666; Mon, 11 Aug 2025 13:56:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi index a259e5735d938cfa5b29cee6c754c7a3c0aaae08..fc87ab818d975974dd811cedde2= 7292ec79f2c8b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -289,6 +289,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8012-pmgr.dtsi" --=20 2.50.1 From nobody Sun Oct 5 00:07:09 2025 Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 760972E2666; Mon, 11 Aug 2025 13:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index 12acf8fc8bc6bcde6b11773cadd97e9ee115f510..9bf5157f0e504b7394ef5354411= d3d37e8d5760a 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -284,6 +284,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells =3D <3>; interrupt-controller; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p0 &cpu_p1>; + }; + }; }; =20 pmgr: power-management@232000000 { @@ -412,6 +424,18 @@ timer { interrupts =3D , ; }; + + pmu-e { + compatible =3D "apple,mistral-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,monsoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; }; =20 #include "t8015-pmgr.dtsi" --=20 2.50.1