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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459c58ed07fsm319461145e9.22.2025.08.10.11.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 11:52:50 -0700 (PDT) From: Daniel Lezcano To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi.Procopciuc@nxp.com, s32@nxp.com Subject: [PATCH v1 1/2] dt: bindings: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3 Date: Sun, 10 Aug 2025 20:52:17 +0200 Message-ID: <20250810185221.2767567-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250810185221.2767567-1-daniel.lezcano@linaro.org> References: <20250810185221.2767567-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S32G2 and S32G3 have a FlexTimer (FTM) available which is the same as the one found on the Vybrid Family and the i.MX8. Add the compatibles in the bindings Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml b= /Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml index 7f9f72d95e7a..c7a10180208e 100644 --- a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml @@ -26,9 +26,14 @@ maintainers: =20 properties: compatible: - enum: - - fsl,vf610-ftm-pwm - - fsl,imx8qm-ftm-pwm + oneOf: + - enum: + - fsl,vf610-ftm-pwm + - fsl,imx8qm-ftm-pwm + - nxp,s32g2-ftm-pwm + - items: + - const: nxp,s32g3-ftm-pwm + - const: nxp,s32g2-ftm-pwm =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sun Oct 5 03:35:13 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE9871FBEB6 for ; Sun, 10 Aug 2025 18:52:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754851976; cv=none; b=DwziNK2+tJaJKwl3LLI/FNBVZeP+Big6mzmIDzNxswKnnNvbhtH5gB4rM9HaMmNhOAHg+HjPAovHAZom2BVV2rCf1tVF0S4VP1PiZGM8MPajmg9a9qFYnr1gnxe/c/CIEbyNlin6P8rZC/IeWNckxk/yN/SOLUjJAOHxiUsms+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754851976; c=relaxed/simple; bh=P2Fu72CQaNHCt9JS3YRrF2AbMeOcEEBOTRXmAyjvBGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T1QtnAAM9J6KIWe9QY0e70NctqzOXn1qLH6+Rhx/lAtgCqzMgreAerCjvynyNjbCWfkKrZt2z0CiyzjNatyicQz/BakpdYBbjSN8Rf01Mx4OiV86lf5Hd16WKChHpEBvC8auhJAdQzxw8B16/GoGrcdRiR6VgEEXqBDk3OCcR7k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ffavlSyv; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ffavlSyv" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-458b49c98a7so23164215e9.1 for ; Sun, 10 Aug 2025 11:52:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1754851972; x=1755456772; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nFEz1nclHsvZ5p/yQBGHENq//Wd3Y52xpznrZUoy7hY=; b=ffavlSyvULV9XGBkHd5bq5yfTJVVKkK24pnXF6JGTHRtpZg4Bp6bNojz88qDEJsZoR 50v+iBD8AtPvDervR2icKjk6bh1WiJI1c+31oSEUwEsTQc+F5jRKuae1rHVxIMwuHcPv N+ysgTPS7OZUwjZH6f9ON5lg2mVK0TuzCCI1wrGOyQQxZ8yCdZ1uj9F8Rk002xr7ieqD zb/3a3lJDN0cPU4jc/YWT9fKgm0Scern/rzDDgV97cHYXI5A2+7I0Htk/dDkCug3gUpG cO55uMTewqnaJpnXtunX7jdp5URyDgeiiR/FpsL4p59+24Y789TVzlnqaxWxLYlGZj8g laMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754851972; x=1755456772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nFEz1nclHsvZ5p/yQBGHENq//Wd3Y52xpznrZUoy7hY=; b=WzHJe+y+stTe3lMZkUjR9uisL2mwstT4zbQCybGiWhCL4JWoPyMWIkDnLgc+uAhVRc QN3Ljp7FsWG3AATe8w/vg+P5ioz0KTvvu66IMJVvuLlnuuy1naDA4C/xFytxxhiCkZ/i XqPVhm1WO8YgZiRcksZM1RGQ8TFmR4wFqRCxcUDG4BYM14s2KvpvQjbkquZ0TCCExcgd pIFublJpVQLxTm4/KG/BaLwm3iO2VuaNAhjmVHQQrJs/32bsBX9N82nA/c8fFBnGoxHm +g8hySqLrLoXuwuZEwHigmlVZBWn1Q0AsPCunC+DBHXBAHBzSO+gc4CH1Ic7by8PVqIE HkKw== X-Forwarded-Encrypted: i=1; AJvYcCUEDFfQiRSWm70p7XjeX86bag6JvvMsAB9GqVBzrXF4BHoniZ81+OyVvqCqIzNX8Gk4G8DZwm6KfUIo4lo=@vger.kernel.org X-Gm-Message-State: AOJu0YyckmEnXvAdg0to4ykWesEp5vpJCDoKsoMnYGgXps3Sx4z42M6I 6Zb6leegTNiKExIsBf9eJSSnaca7GxsR0Cj/V9rJB/UR7O1vZiYDYGWZh1POF+19nkM= X-Gm-Gg: ASbGncuUEQAXaFABo5tTb4VckV0NmpKd0SEyFkCvoPCbWvNHVi0gz2z6jH1po3tp7le n8bMS18p+nnbhXcNQpBVAWBUsZzLm/cs45uLPZf1uCbuXdmLyiAOSs0XYO1f1OZfAoubvmpW97u W1M1Pc/KvFPbZ4Q7ro0Rge3yGiCmW32Z62aojd5KDxAEiHivOvY+1yEE33O+P4AT1VY+faPJhTM wsi5RHr33DhWUhYDoOQiKfv6w/rs2K7HiXwQyn3F24Cvx4i58AjZGpFoa5ZmsScMcNfeiBNAsjt TnYk6T1NNsPm6u6xbvseX9M5WhCU0aCh2e8Cj+unDl5H23DNUUyeUOVOTIEkIVb7Mbl/Ha40nzp Iv3CQTRGWMAYKeSRgzNPDgLyllrgZ9/ZI7OqwDl8rrpfu3/c4 X-Google-Smtp-Source: AGHT+IHWEczYoBoBFfJKfiPTtisF+slaMpEsHwic/e3e52JoQy92AoB9CQoFKFa36R/flhTCcQ+URA== X-Received: by 2002:a05:600c:1c98:b0:458:bfb1:1fc7 with SMTP id 5b1f17b1804b1-459f4f2e2f9mr83878475e9.6.1754851972158; Sun, 10 Aug 2025 11:52:52 -0700 (PDT) Received: from mai.. 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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459c58ed07fsm319461145e9.22.2025.08.10.11.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 11:52:51 -0700 (PDT) From: Daniel Lezcano To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Frank.Li@nxp.com Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ghennadi.Procopciuc@nxp.com, s32@nxp.com Subject: [PATCH v1 2/2] pwm: Add the S32G support in the Freescale FTM driver Date: Sun, 10 Aug 2025 20:52:18 +0200 Message-ID: <20250810185221.2767567-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250810185221.2767567-1-daniel.lezcano@linaro.org> References: <20250810185221.2767567-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ghennadi Procopciuc The Automotive S32G2 and S32G3 platforms include two FTM timers for pwm. Each FTM has 6 PWM channels. The current Freescale FTM driver supports the iMX8 and the Vybrid Family FTM IP. The FTM IP found on the S32G platforms is almost identical except for the number of channels and the register mapping. These changes allow to deal with different number of channels and support the holes found in the register memory mapping for s32gx for suspend / resume. Tested on a s32g274-rdb2 J5 PWM pin output with signal visualization on oscilloscope. Signed-off-by: Ghennadi Procopciuc Co-developed-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/pwm/pwm-fsl-ftm.c | 42 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c index c45a5fca4cbb..cdf2e3572c90 100644 --- a/drivers/pwm/pwm-fsl-ftm.c +++ b/drivers/pwm/pwm-fsl-ftm.c @@ -3,6 +3,7 @@ * Freescale FlexTimer Module (FTM) PWM Driver * * Copyright 2012-2013 Freescale Semiconductor, Inc. + * Copyright 2020-2025 NXP */ =20 #include @@ -31,6 +32,9 @@ enum fsl_pwm_clk { =20 struct fsl_ftm_soc { bool has_enable_bits; + bool has_fltctrl; + bool has_fltpol; + unsigned int npwm; }; =20 struct fsl_pwm_periodcfg { @@ -386,6 +390,23 @@ static bool fsl_pwm_volatile_reg(struct device *dev, u= nsigned int reg) return false; } =20 +static bool fsl_pwm_is_reg(struct device *dev, unsigned int reg) +{ + struct pwm_chip *chip =3D dev_get_drvdata(dev); + struct fsl_pwm_chip *fpc =3D to_fsl_chip(chip); + + if (reg >=3D FTM_CSC(fpc->soc->npwm) && reg < FTM_CNTIN) + return false; + + if (reg =3D=3D FTM_FLTCTRL && !fpc->soc->has_fltctrl) + return false; + + if (reg =3D=3D FTM_FLTPOL && !fpc->soc->has_fltpol) + return false; + + return true; +} + static const struct regmap_config fsl_pwm_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -394,23 +415,26 @@ static const struct regmap_config fsl_pwm_regmap_conf= ig =3D { .max_register =3D FTM_PWMLOAD, .volatile_reg =3D fsl_pwm_volatile_reg, .cache_type =3D REGCACHE_FLAT, + .writeable_reg =3D fsl_pwm_is_reg, + .readable_reg =3D fsl_pwm_is_reg, }; =20 static int fsl_pwm_probe(struct platform_device *pdev) { + const struct fsl_ftm_soc *soc =3D of_device_get_match_data(&pdev->dev); struct pwm_chip *chip; struct fsl_pwm_chip *fpc; void __iomem *base; int ret; =20 - chip =3D devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc)); + chip =3D devm_pwmchip_alloc(&pdev->dev, soc->npwm, sizeof(*fpc)); if (IS_ERR(chip)) return PTR_ERR(chip); fpc =3D to_fsl_chip(chip); =20 mutex_init(&fpc->lock); =20 - fpc->soc =3D of_device_get_match_data(&pdev->dev); + fpc->soc =3D soc; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -526,15 +550,29 @@ static const struct dev_pm_ops fsl_pwm_pm_ops =3D { =20 static const struct fsl_ftm_soc vf610_ftm_pwm =3D { .has_enable_bits =3D false, + .has_fltctrl =3D true, + .has_fltpol =3D true, + .npwm =3D 8, }; =20 static const struct fsl_ftm_soc imx8qm_ftm_pwm =3D { .has_enable_bits =3D true, + .has_fltctrl =3D true, + .has_fltpol =3D true, + .npwm =3D 8, +}; + +static const struct fsl_ftm_soc s32g2_ftm_pwm =3D { + .has_enable_bits =3D true, + .has_fltctrl =3D false, + .has_fltpol =3D false, + .npwm =3D 6, }; =20 static const struct of_device_id fsl_pwm_dt_ids[] =3D { { .compatible =3D "fsl,vf610-ftm-pwm", .data =3D &vf610_ftm_pwm }, { .compatible =3D "fsl,imx8qm-ftm-pwm", .data =3D &imx8qm_ftm_pwm }, + { .compatible =3D "nxp,s32g2-ftm-pwm", .data =3D &s32g2_ftm_pwm }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); --=20 2.43.0