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[93.89.165.28]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-459dbba5210sm287721715e9.2.2025.08.10.07.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 07:39:17 -0700 (PDT) From: Gabor Juhos Date: Sun, 10 Aug 2025 16:38:51 +0200 Subject: [PATCH 2/2] spi: spi-qpic-snand: remove 'clr*status' members of struct 'qpic_ecc' Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250810-qpic-snand-qpic_ecc-cleanup-v1-2-33a6b2bcbc67@gmail.com> References: <20250810-qpic-snand-qpic_ecc-cleanup-v1-0-33a6b2bcbc67@gmail.com> In-Reply-To: <20250810-qpic-snand-qpic_ecc-cleanup-v1-0-33a6b2bcbc67@gmail.com> To: Mark Brown Cc: Md Sadre Alam , Varadarajan Narayanan , Sricharan Ramabadhran , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.2 In the qcom_spi_ecc_init_ctx_pipelined() function, the 'clrflashstatus' and the 'clrreadstatus' members of the ECC context gets initialized with constant values. Then these values are used by several functions to set the corresponding members in the register cache. Because the values are never modified, change the code to set the those directly in the register cache by the qcom_spi_ecc_init_ctx_pipelined() function, and remove the repetitive code from the other functions to reduce code duplication. Also, remove the respective members from the 'qpic_ecc' structure as those became unused due to the change. No functional changes intended. Signed-off-by: Gabor Juhos --- drivers/spi/spi-qpic-snand.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index bc2158e560be3b0ab1b26882e4de524ecf662d14..01f16f49d4cafa608373a176cd1= bd88bd00d2a99 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -94,8 +94,6 @@ struct qpic_ecc { u32 cfg1_raw; u32 ecc_buf_cfg; u32 ecc_bch_cfg; - u32 clrflashstatus; - u32 clrreadstatus; bool bch_enabled; }; =20 @@ -381,12 +379,12 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nan= d_device *nand) FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw= ); =20 ecc_cfg->ecc_buf_cfg =3D FIELD_PREP(NUM_STEPS_MASK, 0x203); - ecc_cfg->clrflashstatus =3D FS_READY_BSY_N; - ecc_cfg->clrreadstatus =3D 0xc0; =20 conf->step_size =3D ecc_cfg->step_size; conf->strength =3D ecc_cfg->strength; =20 + snandc->regs->clrflashstatus =3D cpu_to_le32(FS_READY_BSY_N); + snandc->regs->clrreadstatus =3D cpu_to_le32(0xc0); snandc->regs->erased_cw_detect_cfg_clr =3D cpu_to_le32(CLR_ERASED_PAGE_DE= T); snandc->regs->erased_cw_detect_cfg_set =3D cpu_to_le32(SET_ERASED_PAGE_DE= T); =20 @@ -598,8 +596,6 @@ static int qcom_spi_read_last_cw(struct qcom_nand_contr= oller *snandc, snandc->regs->cfg0 =3D cpu_to_le32(cfg0); snandc->regs->cfg1 =3D cpu_to_le32(cfg1); snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); - snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); - snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); @@ -733,8 +729,6 @@ static int qcom_spi_read_cw_raw(struct qcom_nand_contro= ller *snandc, u8 *data_bu snandc->regs->cfg0 =3D cpu_to_le32(cfg0); snandc->regs->cfg1 =3D cpu_to_le32(cfg1); snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); - snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); - snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); @@ -849,8 +843,6 @@ static int qcom_spi_read_page_ecc(struct qcom_nand_cont= roller *snandc, snandc->regs->cfg0 =3D cpu_to_le32(cfg0); snandc->regs->cfg1 =3D cpu_to_le32(cfg1); snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); - snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); - snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); @@ -942,8 +934,6 @@ static int qcom_spi_read_page_oob(struct qcom_nand_cont= roller *snandc, snandc->regs->cfg0 =3D cpu_to_le32(cfg0); snandc->regs->cfg1 =3D cpu_to_le32(cfg1); snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); - snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); - snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); @@ -1063,8 +1053,6 @@ static int qcom_spi_program_raw(struct qcom_nand_cont= roller *snandc, snandc->regs->cfg0 =3D cpu_to_le32(cfg0); snandc->regs->cfg1 =3D cpu_to_le32(cfg1); snandc->regs->ecc_bch_cfg =3D cpu_to_le32(ecc_bch_cfg); - snandc->regs->clrflashstatus =3D cpu_to_le32(ecc_cfg->clrflashstatus); - snandc->regs->clrreadstatus =3D cpu_to_le32(ecc_cfg->clrreadstatus); snandc->regs->exec =3D cpu_to_le32(1); =20 qcom_spi_config_page_write(snandc); --=20 2.50.1