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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0ad996459sm42685171cf.46.2025.08.10.15.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 15:46:51 -0700 (PDT) From: Brian Masney Date: Sun, 10 Aug 2025 18:45:35 -0400 Subject: [PATCH v2 7/9] phy: rockchip: phy-rockchip-inno-hdmi: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250810-phy-clk-round-rate-v2-7-9162470bb9f2@redhat.com> References: <20250810-phy-clk-round-rate-v2-0-9162470bb9f2@redhat.com> In-Reply-To: <20250810-phy-clk-round-rate-v2-0-9162470bb9f2@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754865940; l=3209; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=cKQDgyjW9ziRVEOEeZhANbLz60Yx7I/xu3+zURpXhB8=; b=ubxW3dDssQ9yAkb8tdXuvrTvn/pHg2yvGTU+fNLDZ2kHxtV9S6BpsFJwTSIz6e+KtTNUexPkp SQMN9QW7undDFAjxcu/0ARBSNmYy90wYl7KSLg0AAAuddMqm2btJcAi X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 30 ++++++++++++++---------= ---- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-hdmi.c index 8dcc2bb777b5455d21a10f06c5ad842b2ddbc834..1483907413faa5ce1dc8614db05= e6e929410404d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -749,22 +749,23 @@ unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(st= ruct clk_hw *hw, return vco; } =20 -static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { const struct pre_pll_config *cfg =3D pre_pll_cfg_table; =20 - rate =3D (rate / 1000) * 1000; + req->rate =3D (req->rate / 1000) * 1000; =20 for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D rate && !cfg->fracdiv) + if (cfg->pixclock =3D=3D req->rate && !cfg->fracdiv) break; =20 if (cfg->pixclock =3D=3D 0) return -EINVAL; =20 - return cfg->pixclock; + req->rate =3D cfg->pixclock; + + return 0; } =20 static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, @@ -835,7 +836,7 @@ static const struct clk_ops inno_hdmi_phy_rk3228_clk_op= s =3D { .unprepare =3D inno_hdmi_phy_rk3228_clk_unprepare, .is_prepared =3D inno_hdmi_phy_rk3228_clk_is_prepared, .recalc_rate =3D inno_hdmi_phy_rk3228_clk_recalc_rate, - .round_rate =3D inno_hdmi_phy_rk3228_clk_round_rate, + .determine_rate =3D inno_hdmi_phy_rk3228_clk_determine_rate, .set_rate =3D inno_hdmi_phy_rk3228_clk_set_rate, }; =20 @@ -906,22 +907,23 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(st= ruct clk_hw *hw, return inno->pixclock; } =20 -static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { const struct pre_pll_config *cfg =3D pre_pll_cfg_table; =20 - rate =3D (rate / 1000) * 1000; + req->rate =3D (req->rate / 1000) * 1000; =20 for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D rate) + if (cfg->pixclock =3D=3D req->rate) break; =20 if (cfg->pixclock =3D=3D 0) return -EINVAL; =20 - return cfg->pixclock; + req->rate =3D cfg->pixclock; + + return 0; } =20 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, @@ -989,7 +991,7 @@ static const struct clk_ops inno_hdmi_phy_rk3328_clk_op= s =3D { .unprepare =3D inno_hdmi_phy_rk3328_clk_unprepare, .is_prepared =3D inno_hdmi_phy_rk3328_clk_is_prepared, .recalc_rate =3D inno_hdmi_phy_rk3328_clk_recalc_rate, - .round_rate =3D inno_hdmi_phy_rk3328_clk_round_rate, + .determine_rate =3D inno_hdmi_phy_rk3328_clk_determine_rate, .set_rate =3D inno_hdmi_phy_rk3328_clk_set_rate, }; =20 --=20 2.50.1