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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b0ad996459sm42685171cf.46.2025.08.10.15.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 15:46:31 -0700 (PDT) From: Brian Masney Date: Sun, 10 Aug 2025 18:45:33 -0400 Subject: [PATCH v2 5/9] phy: mediatek: phy-mtk-mipi-dsi-mt8173: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250810-phy-clk-round-rate-v2-5-9162470bb9f2@redhat.com> References: <20250810-phy-clk-round-rate-v2-0-9162470bb9f2@redhat.com> In-Reply-To: <20250810-phy-clk-round-rate-v2-0-9162470bb9f2@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754865940; l=1519; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=x3H+bi72Ud0O2ADBCQwtbhpk+18O8IQnZUeD4zYXytc=; b=Ko6nm+pXyNo8X1nQDJr+lVHcu4cXjZr/njvgKDiWI9hUw5g4z0iGWyficBfc/rHylfr1bFBC5 OcjcwnYNCZzC9mq0m1MLk4fjF5rjaP4zt/gCvk1nnxylsB0GMKTpJxJ X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/m= ediatek/phy-mtk-mipi-dsi-mt8173.c index 673cb0f08959e0e4f2b1ade2ebaf796e8b76f8bc..438ff3605d90121b7bfe02b3ddc= a8194437ed9ba 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -237,16 +237,18 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *= hw) mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK); } =20 -static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long ra= te, - unsigned long *prate) +static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clamp_val(rate, 50000000, 1250000000); + req->rate =3D clamp_val(req->rate, 50000000, 1250000000); + + return 0; } =20 static const struct clk_ops mtk_mipi_tx_pll_ops =3D { .prepare =3D mtk_mipi_tx_pll_prepare, .unprepare =3D mtk_mipi_tx_pll_unprepare, - .round_rate =3D mtk_mipi_tx_pll_round_rate, + .determine_rate =3D mtk_mipi_tx_pll_determine_rate, .set_rate =3D mtk_mipi_tx_pll_set_rate, .recalc_rate =3D mtk_mipi_tx_pll_recalc_rate, }; --=20 2.50.1