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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-7077cdd9916sm144266336d6.61.2025.08.10.15.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Aug 2025 15:57:46 -0700 (PDT) From: Brian Masney Date: Sun, 10 Aug 2025 18:57:26 -0400 Subject: [PATCH v2 2/7] drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250810-drm-msm-phy-clk-round-rate-v2-2-0fd1f7979c83@redhat.com> References: <20250810-drm-msm-phy-clk-round-rate-v2-0-0fd1f7979c83@redhat.com> In-Reply-To: <20250810-drm-msm-phy-clk-round-rate-v2-0-0fd1f7979c83@redhat.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754866653; l=3160; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=zgC0RAqMfe4QHFoCK3ImKc6JYhHbtGs2pWeVB9da7xM=; b=g/OyIxfyVmL0j+PhW5RWDXbEs2uOlzP1vLM9nzajU+5emPdyje17xtKS5Qd4HfejxqWdsQWeZ 8ROBSPZGhvzDt9b3VBZA5OUUGLIt5EVJPoH+qM81ctxrdXWei/umj9J X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. The change to use clamp_t() was done manually. Signed-off-by: Brian Masney Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 34 +++++++++++++++-----------= ---- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/m= sm/dsi/phy/dsi_phy_14nm.c index 3a1c8ece6657c988cfb0c26af39b5d145bc576f8..fdefcbd9c2848a1c76414a41b81= 1b29e5fed9ddc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -578,21 +578,19 @@ static void dsi_pll_14nm_vco_unprepare(struct clk_hw = *hw) pll_14nm->phy->pll_on =3D false; } =20 -static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_14nm *pll_14nm =3D to_pll_14nm(hw); =20 - if (rate < pll_14nm->phy->cfg->min_pll_rate) - return pll_14nm->phy->cfg->min_pll_rate; - else if (rate > pll_14nm->phy->cfg->max_pll_rate) - return pll_14nm->phy->cfg->max_pll_rate; - else - return rate; + req->rate =3D clamp_t(unsigned long, req->rate, + pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate); + + return 0; } =20 static const struct clk_ops clk_ops_dsi_pll_14nm_vco =3D { - .round_rate =3D dsi_pll_14nm_clk_round_rate, + .determine_rate =3D dsi_pll_14nm_clk_determine_rate, .set_rate =3D dsi_pll_14nm_vco_set_rate, .recalc_rate =3D dsi_pll_14nm_vco_recalc_rate, .prepare =3D dsi_pll_14nm_vco_prepare, @@ -622,18 +620,20 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate= (struct clk_hw *hw, postdiv->flags, width); } =20 -static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_14nm_postdiv *postdiv =3D to_pll_14nm_postdiv(hw); struct dsi_pll_14nm *pll_14nm =3D postdiv->pll; =20 - DBG("DSI%d PLL parent rate=3D%lu", pll_14nm->phy->id, rate); + DBG("DSI%d PLL parent rate=3D%lu", pll_14nm->phy->id, req->rate); =20 - return divider_round_rate(hw, rate, prate, NULL, - postdiv->width, - postdiv->flags); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + NULL, + postdiv->width, + postdiv->flags); + + return 0; } =20 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long = rate, @@ -680,7 +680,7 @@ static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw = *hw, unsigned long rate, =20 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv =3D { .recalc_rate =3D dsi_pll_14nm_postdiv_recalc_rate, - .round_rate =3D dsi_pll_14nm_postdiv_round_rate, + .determine_rate =3D dsi_pll_14nm_postdiv_determine_rate, .set_rate =3D dsi_pll_14nm_postdiv_set_rate, }; =20 --=20 2.50.1