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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b8ff860acbsm5326759f8f.51.2025.08.08.14.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Aug 2025 14:52:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yoshihiro Shimoda , Geert Uytterhoeven , Magnus Damm , Neil Armstrong Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 4/5] phy: renesas: rcar-gen3-usb2: Add support for RZ/T2H SoC Date: Fri, 8 Aug 2025 22:52:08 +0100 Message-ID: <20250808215209.3692744-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250808215209.3692744-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250808215209.3692744-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add initial support for the Renesas RZ/T2H SoC to the R-Car Gen3 USB2 PHY driver. The RZ/T2H SoC requires configuration of additional hardware-specific bits for proper VBUS level control and OTG operation. Introduce the `vblvl_ctrl` flag in the SoC-specific driver data to enable handling of VBUS level selection logic using `VBCTRL.VBLVL` bits. This is required for managing the VBUS status detection and drive logic based on SoC-specific needs. Signed-off-by: Lad Prabhakar Reviewed-by: Neil Armstrong --- v1->v2: - Included the necessary header files. - Simplified device/host detection in rcar_gen3_check_id() as suggested by Geert. - Added Reviewed-by from Neil. --- drivers/phy/renesas/phy-rcar-gen3-usb2.c | 82 ++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 7 deletions(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas= /phy-rcar-gen3-usb2.c index a37af7d8f2f4..8caef9cb228c 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -9,6 +9,8 @@ * Copyright (C) 2014 Cogent Embedded, Inc. */ =20 +#include +#include #include #include #include @@ -69,13 +71,20 @@ #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 =3D Peripheral mode */ =20 /* OBINTSTA and OBINTEN */ +#define USB2_OBINTSTA_CLEAR GENMASK(31, 0) #define USB2_OBINT_SESSVLDCHG BIT(12) #define USB2_OBINT_IDDIGCHG BIT(11) +#define USB2_OBINT_VBSTAINT BIT(3) #define USB2_OBINT_IDCHG_EN BIT(0) /* RZ/G2L specific */ =20 /* VBCTRL */ +#define USB2_VBCTRL_VBSTA_MASK GENMASK(31, 28) +#define USB2_VBCTRL_VBSTA_DEFAULT 2 +#define USB2_VBCTRL_VBLVL_MASK GENMASK(23, 20) +#define USB2_VBCTRL_VBLVL(m) FIELD_PREP_CONST(USB2_VBCTRL_VBLVL_MASK, (m)) #define USB2_VBCTRL_OCCLREN BIT(16) #define USB2_VBCTRL_DRVVBUSSEL BIT(8) +#define USB2_VBCTRL_SIDDQREL BIT(2) #define USB2_VBCTRL_VBOUT BIT(0) =20 /* LINECTRL1 */ @@ -88,6 +97,7 @@ /* ADPCTRL */ #define USB2_ADPCTRL_OTGSESSVLD BIT(20) #define USB2_ADPCTRL_IDDIG BIT(19) +#define USB2_ADPCTRL_VBUSVALID BIT(18) #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 =3D ID sampling is enabled */ #define USB2_ADPCTRL_DRVVBUS BIT(4) =20 @@ -138,6 +148,7 @@ struct rcar_gen3_phy_drv_data { bool no_adp_ctrl; bool init_bus; bool utmi_ctrl; + bool vblvl_ctrl; u32 obint_enable_bits; }; =20 @@ -201,7 +212,7 @@ static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3= _chan *ch, int vbus) u32 val; =20 dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus); - if (ch->phy_data->no_adp_ctrl) { + if (ch->phy_data->no_adp_ctrl || ch->phy_data->vblvl_ctrl) { if (ch->vbus) regulator_hardware_enable(ch->vbus, vbus); =20 @@ -284,6 +295,16 @@ static void rcar_gen3_init_from_a_peri_to_a_host(struc= t rcar_gen3_chan *ch) =20 static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch) { + if (ch->phy_data->vblvl_ctrl) { + bool vbus_valid; + bool device; + + device =3D !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG); + vbus_valid =3D !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_VBUSVALI= D); + + return !(device && !vbus_valid); + } + if (!ch->uses_otg_pins) return (ch->dr_mode =3D=3D USB_DR_MODE_HOST) ? false : true; =20 @@ -419,11 +440,20 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan = *ch) writel(val, usb2_base + USB2_LINECTRL1); =20 if (!ch->phy_data->no_adp_ctrl) { - val =3D readl(usb2_base + USB2_VBCTRL); - val &=3D ~USB2_VBCTRL_OCCLREN; - writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); - val =3D readl(usb2_base + USB2_ADPCTRL); - writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); + if (ch->phy_data->vblvl_ctrl) { + val =3D readl(usb2_base + USB2_VBCTRL); + val =3D (val & ~USB2_VBCTRL_VBLVL_MASK) | USB2_VBCTRL_VBLVL(2); + writel(val, usb2_base + USB2_VBCTRL); + val =3D readl(usb2_base + USB2_ADPCTRL); + writel(val | USB2_ADPCTRL_IDPULLUP | USB2_ADPCTRL_DRVVBUS, + usb2_base + USB2_ADPCTRL); + } else { + val =3D readl(usb2_base + USB2_VBCTRL); + val &=3D ~USB2_VBCTRL_OCCLREN; + writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); + val =3D readl(usb2_base + USB2_ADPCTRL); + writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); + } } mdelay(20); =20 @@ -433,6 +463,23 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *= ch) rcar_gen3_device_recognition(ch); } =20 +static void rcar_gen3_configure_vblvl_ctrl(struct rcar_gen3_chan *ch) +{ + void __iomem *usb2_base =3D ch->base; + u32 val; + + if (!ch->phy_data->vblvl_ctrl) + return; + + val =3D readl(usb2_base + USB2_VBCTRL); + if ((val & USB2_VBCTRL_VBSTA_MASK) =3D=3D + FIELD_PREP_CONST(USB2_VBCTRL_VBSTA_MASK, USB2_VBCTRL_VBSTA_DEFAULT)) + val &=3D ~USB2_VBCTRL_VBLVL_MASK; + else + val |=3D USB2_VBCTRL_VBLVL(USB2_VBCTRL_VBSTA_DEFAULT); + writel(val, usb2_base + USB2_VBCTRL); +} + static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch) { struct rcar_gen3_chan *ch =3D _ch; @@ -450,8 +497,12 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, voi= d *_ch) status =3D readl(usb2_base + USB2_OBINTSTA); if (status & ch->phy_data->obint_enable_bits) { dev_vdbg(dev, "%s: %08x\n", __func__, status); - writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA); + if (ch->phy_data->vblvl_ctrl) + writel(USB2_OBINTSTA_CLEAR, usb2_base + USB2_OBINTSTA); + else + writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA); rcar_gen3_device_recognition(ch); + rcar_gen3_configure_vblvl_ctrl(ch); ret =3D IRQ_HANDLED; } } @@ -484,6 +535,13 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) if (rphy->int_enable_bits) rcar_gen3_init_otg(channel); =20 + if (channel->phy_data->vblvl_ctrl) { + /* SIDDQ mode release */ + writel(readl(usb2_base + USB2_VBCTRL) | USB2_VBCTRL_SIDDQREL, + usb2_base + USB2_VBCTRL); + udelay(250); + } + if (channel->phy_data->utmi_ctrl) { val =3D readl(usb2_base + USB2_REGEN_CG_CTRL) | USB2_REGEN_CG_CTRL_UPHY_= WEN; writel(val, usb2_base + USB2_REGEN_CG_CTRL); @@ -613,6 +671,12 @@ static const struct rcar_gen3_phy_drv_data rz_g3s_phy_= usb2_data =3D { .obint_enable_bits =3D USB2_OBINT_IDCHG_EN, }; =20 +static const struct rcar_gen3_phy_drv_data rz_t2h_phy_usb2_data =3D { + .phy_usb2_ops =3D &rcar_gen3_phy_usb2_ops, + .vblvl_ctrl =3D true, + .obint_enable_bits =3D USB2_OBINT_IDCHG_EN | USB2_OBINT_VBSTAINT, +}; + static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data =3D { .phy_usb2_ops =3D &rcar_gen3_phy_usb2_ops, .no_adp_ctrl =3D true, @@ -645,6 +709,10 @@ static const struct of_device_id rcar_gen3_phy_usb2_ma= tch_table[] =3D { .compatible =3D "renesas,usb2-phy-r9a09g057", .data =3D &rz_v2h_phy_usb2_data, }, + { + .compatible =3D "renesas,usb2-phy-r9a09g077", + .data =3D &rz_t2h_phy_usb2_data, + }, { .compatible =3D "renesas,rzg2l-usb2-phy", .data =3D &rz_g2l_phy_usb2_data, --=20 2.50.1