From nobody Sun Oct 5 03:40:29 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A5CD2877FC; Fri, 8 Aug 2025 19:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754681775; cv=none; b=jU4Oo7sZW6Rx+0zwHXMm85x/GuYFskcnU6afxFM59xZighTKUCSFqOYXloGDi/dXxMPIFE/QXHc9uteihzWGHsrAtXHbGY6ecSh5M9D8FNoYKMfHUnVrhT8znoRsNT0iKCRsZj7eAryHCwKVwK/Y3tebvXoF+MsTZ0NVyX7ED0s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754681775; c=relaxed/simple; bh=5Gy5tegd6uu1e9KY0y64YIwx/lrqPHX8tSnZWyRsDnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cqaAhMtK7MDbClzzl8JnRly32mdNPbqN9j5KWGO72TLcmR5ZR/tpgGScHoXGQVeCXceC6MSno5bNAJMMKog1JIF6YJWw3zGAaVA97jrgWll8F6lbV97R3zg7+OsTTvieLOLzY6rk6C6A11jFka+YIOeb38kck7OnNsb4XNaSmvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=LWXmok4Y; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="LWXmok4Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754681771; bh=5Gy5tegd6uu1e9KY0y64YIwx/lrqPHX8tSnZWyRsDnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LWXmok4YzSAZh94/u8tkq1ocP4Nml9vnU4JCK5t+r9F5YEXasCVDq3U1vbw4okW1t Vash47t/DuiTV0ov+AOb3UVHPLzqHEniW8yp1TQ2mIxMCe/DXkVIxK3yX1UfzRTyLB DrJZAq3nEG7EmWdH1M9AlB0CVMUDbM9UxgwOtadkAuuFRMSwRpo+JFFP9Lmpe8DwmK h8sVlIKkBENZMG7h/i2unKdQviYYA070G+tP6njfFhaobLXKkYunTeUbHse5obdSkt O+HtaSXm2wq5f2pNbotmpUxtCsFUXl2NyfN5aoBXLXgVXQL0QzJdufffFteRrK1IuL 7MPjrk8Vyg/jQ== Received: from earth.mtl.collabora.ca (mtl.collabora.ca [66.171.169.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 568E717E0DBE; Fri, 8 Aug 2025 21:36:08 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Nicolas Frattaroli , Detlev Casanova , Kever Yang , Shawn Lin , Sebastian Reichel , Cristian Ciocaltea , Dragan Simic , Niklas Cassel , Damon Ding , Emmanuel Gil Peyrot , Alexey Charkov , Patrick Wildt , Chukun Pan , Diederik de Haas , Chris Morgan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 1/2] arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 Date: Fri, 8 Aug 2025 15:36:01 -0400 Message-ID: <20250808193602.142527-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250808193602.142527-1-detlev.casanova@collabora.com> References: <20250808193602.142527-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu381 Video Decoders to the rk3588-base devicetree. The RK3588 based SoCs all embed 2 vdpu381 decoders. This also adds the dedicated IOMMU controllers. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba550..189f07c00089e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 { #iommu-cells =3D <0>; }; =20 + vdec0: video-codec@fdc38100 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_C= A>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec0_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + resets =3D <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVD= EC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + #iommu-cells =3D <0>; + }; + + vdec1: video-codec@fdc40100 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_C= A>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec1_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + resets =3D <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVD= EC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + #iommu-cells =3D <0>; + }; + av1d: video-codec@fdc70000 { compatible =3D "rockchip,rk3588-av1-vpu"; reg =3D <0x0 0xfdc70000 0x0 0x800>; @@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 { ranges =3D <0x0 0x0 0xff001000 0xef000>; #address-cells =3D <1>; #size-cells =3D <1>; + + vdec0_sram: codec-sram@0 { + reg =3D <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg =3D <0x78000 0x77000>; + pool; + }; }; =20 pinctrl: pinctrl { --=20 2.50.1 From nobody Sun Oct 5 03:40:29 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46E2D287510; Fri, 8 Aug 2025 19:36:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754681778; cv=none; b=RVwIjIEA2w58gMKmIJmrhxTde0pnSwITLVyqqs1Uf20S3WsVcELKJsLGVurS7XkZS5/6U9rat3Zsx6ja/tGkhb3MMueoxBClGEPQpUCrqrZikVyQwRulcvUVauPkY2X83ua0K4m0vITmExp514hYWzmBwE9uwcZcOkfnaw1dUFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754681778; c=relaxed/simple; bh=rl0GSEMQipGgM/tHbM+N9H22RJ3YNzoiPPjreDdRxxo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DidlY/vq38LdvJjubhr2fjTyqV46Q3u8bU+jTABdNp/krwfUamVTM/SqpPOs8sdF2vWZWFbJz8QWMdewJw06wR7p1FkO+lBh+o0ZXMybuh4Hrm7qL4yX9hq92hh0kXF32iJn+MIsAx1fESe31lRyCOvSR1I79NJwApuU5kv8YM0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Nx2ejqv+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Nx2ejqv+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754681774; bh=rl0GSEMQipGgM/tHbM+N9H22RJ3YNzoiPPjreDdRxxo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nx2ejqv+Bfbt1EGrmSAFz4ZpoGJ7oheCE8D6NN9AzVTjil8qd5ClVFXIDVwezUsea b63njDfAvxrrS1n37ePH0CyrmchENhAcdHMliqois2H3sbE2+1fZYXTGS8avZMFjwM 7tZtBnkyk3vaXgHiU8kCGE7crvoR7WRTE9ummRwRm6BbvWTS8dmB/BNk8EEHrQIZ2O a8be4es7fKb+RytRn4zftG2u6eZEjzWqcNY+YTwqJ/2cp5P4qwCu0ibVcahAzPTidy mv2H5DqluwwuD2RwN04d+AxrsnP1U+LFJli/ysZhiZ6nYurKE6DAx8myU8IzbN3aRu SZkWGPyM3YE/A== Received: from earth.mtl.collabora.ca (mtl.collabora.ca [66.171.169.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id CC64817E1277; Fri, 8 Aug 2025 21:36:11 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Nicolas Frattaroli , Detlev Casanova , Kever Yang , Shawn Lin , Sebastian Reichel , Cristian Ciocaltea , Dragan Simic , Niklas Cassel , Damon Ding , Emmanuel Gil Peyrot , Alexey Charkov , Patrick Wildt , Chukun Pan , Diederik de Haas , Chris Morgan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 Date: Fri, 8 Aug 2025 15:36:02 -0400 Message-ID: <20250808193602.142527-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250808193602.142527-1-detlev.casanova@collabora.com> References: <20250808193602.142527-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu383 Video Decoder variant to the RK3576 device tree. Also allow using the dedicated SRAM as a pool. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index c3cdae8a54941..d16817526b9f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1139,6 +1139,41 @@ gpu: gpu@27800000 { status =3D "disabled"; }; =20 + vdec: video-codec@27b00100 { + compatible =3D "rockchip,rk3576-vdec"; + reg =3D <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates =3D <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus =3D <&vdec_mmu>; + power-domains =3D <&power RK3576_PD_VDEC>; + resets =3D <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible =3D "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells =3D <0>; + }; + vop: vop@27d00000 { compatible =3D "rockchip,rk3576-vop"; reg =3D <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -2428,6 +2463,7 @@ sram: sram@3ff88000 { /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg =3D <0x0 0x78000>; + pool; }; }; =20 --=20 2.50.1