From nobody Mon Feb 9 01:39:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58CDF27C162 for ; Fri, 8 Aug 2025 14:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661838; cv=none; b=MjQwagdh07nF5gRn0JxDLNXCK2X490443ea7fBhXHE7yE/WB273w8SN588Urz3GcgxYRfKgER7TGzx7V82gGoDy7zIFoY3qmn8r73KaBOC5W92hhSl2Z/QvhIO+GJ9carJaibGE8eAJWLl48uazYhe32y4AsBQOzfwJd1K1jNPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661838; c=relaxed/simple; bh=NIUgvFjTnufpMaUkhepDMTHRYMdG1B9PZQLZLAxkW70=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Vj/v9JuCQeFCYFBnfWMWDhC11CPozeguiqOvbilWg8a/5bKl1Vjgx8YN7oNo+fZKuBLH/QAlLadNx3MK+RMgvvOUd+tU1HYGWRnzk2VROq8IbOh6r42u6Udc9J1u2DXApWpc/EBJYh30FlvAmsBnaXf5BBh+92iub59Gr7ZTj8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XkT+Hxdu; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XkT+Hxdu" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5787P3ng007824 for ; Fri, 8 Aug 2025 14:03:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=cnwUV/QDjexBy5i2zSATpYmuz01jPJJmOp4tvR0Fjy8=; b=Xk T+HxduDoSB2QQmVB7zz54+Mo7dYHn/AApzxrJE1mNG/dPhFcIo2Z6QWFDef6pgrO PTzTqeBGVnzDaFfALKMtniB0lgPPQB2ox0Cc8LYD64IJs89LXZMEbDRS0qIzw2Fz gdBz1CADWa+Q7BmejfEFsB1aJAE0d5BuKoWunBjzLygXVKOkmgo2ZYV/W+vxUZrD 3Ggkzn88o6gx16g+tDTABZYa2sHrkGqFHtFqPG4Rvo5yFN6hUUsN1pyCxke0TSuL rpCEMVrQog1NRx1F9HQaOW96+qY3eZ0TPwcuP4Hx20xe7hF7NRUprG4Fyl/iRXLA EZFEjNHNprdPInLi4Wlw== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48c8u278pp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 08 Aug 2025 14:03:56 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-76b6d359927so1538378b3a.3 for ; Fri, 08 Aug 2025 07:03:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754661835; x=1755266635; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cnwUV/QDjexBy5i2zSATpYmuz01jPJJmOp4tvR0Fjy8=; b=EVKJ/Wk4w96ibfbKuetIZ+N5Y8+ujUtb/8RCPyaT+ZLaYu3BBmXAiGvX6Xw6vqEpyX fCbBnhUMKFZe/7ijflsIjaRNphx+SMzsimv35SA0LuRQ9dwcKBih+8T1uwYEhpVUF0rr Q58h/Q6On1UPrRQEr4LF9exQyqndajuAjomxxLCxQBAUzXOIbDwsS+WVEeXMFSbQ7s3a 70L8SLzxfea4mE6vBvoxUFunNd4E1P6ewLEfRC8WCOxu7ba+6QXVCsdZ8AVhVorB/BEN LKcu7DIqyOWiW40EhBOvCSGZdIn0LwDt0Du8AnSfDUepuUA46ayIz9qEgm9m19abQGKM wD1A== X-Forwarded-Encrypted: i=1; AJvYcCV3xjk0LmZZJwyCohFo4+PxicipzhfA8E1fgsOL3MxEwV11f3eCdm+p50bjOAoa/RuqX6dhGMdzMsgXMls=@vger.kernel.org X-Gm-Message-State: AOJu0YwVLsq/8QCYWDlkucEWWW+qVu3tm4fy9OLgdkE33Lmrg4l/tFsx EdoCZ1EFOMRfkRqW9/SVeKMAd6Ba46JcLaT1LsNXPZWEHZ/HItrZGVi+z4Hms3FueQ78zNb3OPd y3/vrZAQZdOHX+2D3a5Fe/ObfiWWSheqntnqljrgIQHVmC4qmqalmz8Gp81ke+6dhLtg= X-Gm-Gg: ASbGncuFlb+YXWm8TBIQQQXPDMJuI7WxhN9oqLu4FYeiEiFOOKfzQkvGnhoXGeY+CLM MMyv2nu56jugUnQz7xn64ZlCrVtl6uKJxYWxCHOTAYDwcP6oiL4HIHID0QLrlmmk1H8+oR2iWHg uM6oWQ9ifvug6swutHsytWwRT8yehVhH/p+JSy8dCr1K5lIRz47p/OGn7jF87tCl6Utbq9V5dg6 e+SQCxZnLEwLNHBoDwWfJLkHZtDHzK9fjIVjrgcay3D8ZbM4hSNVW8+3gE2ywT7wV13sF+1yh2J gpwAOn7ryTmedAUwqcVUsRpUAmyrE1z28Cf4NuGZzS+Yya54ME+LnUgDOGzwnTLddWsz9MuMCA= = X-Received: by 2002:a05:6a00:23d2:b0:76b:c557:b945 with SMTP id d2e1a72fcca58-76c461f7dfcmr5163483b3a.24.1754661834240; Fri, 08 Aug 2025 07:03:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHTzksWDnpE2o7+ZsFPvW6Wq4obz7S9H+b2kg5hFSWzEbMcyjh4qUMKtT2DtOoa8U5Mt9x6nQ== X-Received: by 2002:a05:6a00:23d2:b0:76b:c557:b945 with SMTP id d2e1a72fcca58-76c461f7dfcmr5163411b3a.24.1754661833734; Fri, 08 Aug 2025 07:03:53 -0700 (PDT) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76c2078afd8sm8595621b3a.117.2025.08.08.07.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Aug 2025 07:03:53 -0700 (PDT) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 1/3] dt-bindings: interconnect: add clocks property to enable QoS on sa8775p Date: Fri, 8 Aug 2025 19:32:58 +0530 Message-Id: <20250808140300.14784-2-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> References: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> X-Proofpoint-GUID: 1br3pG57w0N8FCWoOf8Ss4yRty_DbyuY X-Authority-Analysis: v=2.4 cv=Q/TS452a c=1 sm=1 tr=0 ts=689603cc cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=kq7KVtybw__Sne4F7ZAA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: 1br3pG57w0N8FCWoOf8Ss4yRty_DbyuY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDA5MCBTYWx0ZWRfXzyrMsKcMJbuH QZEiVkOrOhwpYeqcPwhzSyWFLyWhJEFqHEVY3vsLTPBgz/bFTSjZ6STXEnVn7pFXQxN6wTqLaBM UQ76sNCrJOXRWJEWFwMKXPUZgAb2/NwbPGZRwWwAArrSlvla7F1mR8j/saRhz3gVP/A1SRH+rCP SuR1ie8sYOrwuL5KLqz0Ln+j6RaRbDwPz7qFJn+vqYu1qRhS+eVCi3PjgvPXOnFKjiswewAAkAF dXfgpD1lpeChrtM5OUq3cbXffDs6QpnWymuPD8v7qmaYGoPjb83cR8fxTtHCZ1055RqpE6zLBKj Ndy1601ywuUlpF6IYE39S5i62wE6UKsrByj8rzun/d/BMWVr8Q9UHjuw4Z+Hs5neoZ05nqT7bwN W+A7efdB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_04,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1011 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060090 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add reg and clocks properties to enable the clocks required for accessing QoS configuration. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,sa8775p-rpmh.yaml | 78 ++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rp= mh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.= yaml index db19fd5c5708..be3d02fb73a4 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -33,18 +33,94 @@ properties: - qcom,sa8775p-pcie-anoc - qcom,sa8775p-system-noc =20 + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 5 + required: - compatible =20 allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-clk-virt + - qcom,sa8775p-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre UFS CARD AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre1-noc + - qcom,sa8775p-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false =20 unevaluatedProperties: false =20 examples: - | - aggre1_noc: interconnect-aggre1-noc { + #include + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sa8775p-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { compatible =3D "qcom,sa8775p-aggre1-noc"; + reg =3D <0x016c0000 0x18080>; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; }; --=20 2.17.1 From nobody Mon Feb 9 01:39:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E65DE27CB0A for ; Fri, 8 Aug 2025 14:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661845; cv=none; b=RH8M6STmDflWfV1bNIFjk6lDTkw0/065/ou7day3rzgDdREVqs3Ek+RzbUgi7UaKaoR/Ae4Wau/8YmYOuerFjfHHMrLmBJEvA6HyR8ckUD20/SeaXcjURL2nCk0oCN9waCLowwdtJO4nX4eyc6DvGKOWDT0FFabSOI7WD8m9CsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661845; c=relaxed/simple; bh=wRE/A8kPesfCce5pnxjzIZo9ulA7b+2n38Egjqz7cU0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=TMsvT6hXE+FKmenw9rYz6zplDBEbcf03Sc2HkGOUxivROJ1elTh04hMIvFCMMMYpQFdFG/q6lDGtUOFFj1hr7GxDE/WCuYPFhqwMNgfW7lVEhSfLqLbnAUzp9w9cnKdxbO7bzbWCE74p6ZZcnxFp0Z4cTmlQIkYcLkyrtxLf3zg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=fiNKD3/l; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="fiNKD3/l" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5787Gr1x011668 for ; Fri, 8 Aug 2025 14:04:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=X1jUhpus4nUviPIA90y3v3oCHbECaPzX5ramSTBCMdg=; b=fi NKD3/lmRPj5auxTaCcGnBNBdROugdYXHay0udNlXQ6g12GNoB7NZi6hM/qHyWGax 3ah11q5M92OxBJy98N1mNM4Iq+cI7VkAekCER0u2VyayW95cor9GasC+ZAJN+fj2 zUNyPEGbRmW0SJDWpJ3e/enE5mKnsVRDVe57I4W4Qa8gnpVpxPaHwbahcSgckQCw aImpOzz/ElzE8eYN6ijugpDaoq48VG0cnZuFrLOzmRHLJDNRIbzSuOT36Rgidzeb MT5JWA4IZdzDgCvpfsljJF/CO4V7H414e/T5kpjiz1wTft1UteTxetkMKVHqIrLB IzQBxbW/QvExiT6GaN0Q== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48cpvy4yx5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 08 Aug 2025 14:04:02 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-75ab147e0a3so4523535b3a.3 for ; Fri, 08 Aug 2025 07:04:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754661840; x=1755266640; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=X1jUhpus4nUviPIA90y3v3oCHbECaPzX5ramSTBCMdg=; b=J32f98E4G3/e3KGiB02hP/a/aHP6bhk+bXNUUsLd1+GHYmMQlmwiiPhJ3xBAq438w8 tuZk8rfXitm+zgcHQ+vefvQ+n0W8NGusujBOF31nBM1YcMcMx0wWhGGtFNl6FWPMm1Xf nIM5ELQUpwb97cfQs3LHU4yqP1UEd19nGtPPvxe4uOB4aKeQhzu2e1W957x4p4vRW7mK wNU9184+X3ZoPGzZ0l3cjb+C7ekfy2PR6jW/g73SqKr54cc/VwQLJZXRVz25XzAkWmcV 8zso5Ct8KiNnbS26HsWhvh2frsoEUq/1bdAsCNpg0WtfEPd+Tw/w2ITQqBz6apG+ehrr ggzg== X-Forwarded-Encrypted: i=1; AJvYcCWic0z9eB1Fc2Nj3drk6G5kkqIqZyq+M+d5iXH4UGsxYxrhTewvzJgtQO1SPdAbUp0lRSUwwYSSK/djHlM=@vger.kernel.org X-Gm-Message-State: AOJu0Yzhh6N8A5CNDCbCgPiesb/WWad4yndlJKODjwg31ptPpAabpZdh srloJ9WrjJhL16eL0cyk0QsWI/c0Ukt23ZsqnS03ORINzTejCdJVguSc1QPj6x0NUj71e03zsoM rPxfrPYeMFeS+xoDEMFAIskjGd+5avSXJ3j24uRgAIafCz7NldLjaNbv4oldIe2XMHZA= X-Gm-Gg: ASbGncuNQdSl9f2h8wuM2NkJy7dMrXOSjEAnaPFnZbUkHOCVkktcB2DOdyKDBxXrLEZ Vmn2OqQCCQMJsaL52f1QaCnhyBNR5uX1ERTrFFWVaxZxzfMo4zA0uxaKCYiem9V+EPSjRCG8D2e S8wdFLaR1edAg577GK9VMvNCCS/yyDPH1cCeoh7FqT3rishcjzYzR5RvwUph4jyfL2X4o2K2I6/ TvA+354kZ5ZzbtxdkZQDA/DJZHuSQlyXaDg0sgOzEHP8E4LgbG8YGQv8l+IP3WzaAqxFEnGyUvg XyfC6A5lCS64m9QaPrRMeNezXJuyhzmAhq2vauaZB3LjJOQ42+RnORLL/sMW+uva6bzqZq4yDw= = X-Received: by 2002:a05:6a00:3998:b0:76b:d8c8:2533 with SMTP id d2e1a72fcca58-76c461c99e6mr5583161b3a.24.1754661839462; Fri, 08 Aug 2025 07:03:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGmke0SjKcj6jzCrc6Ci/fc/vKhpyG7BqmGupOWkg+VaHH175rZE935035iLs/JYskb+1XZMg== X-Received: by 2002:a05:6a00:3998:b0:76b:d8c8:2533 with SMTP id d2e1a72fcca58-76c461c99e6mr5583090b3a.24.1754661838927; Fri, 08 Aug 2025 07:03:58 -0700 (PDT) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76c2078afd8sm8595621b3a.117.2025.08.08.07.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Aug 2025 07:03:58 -0700 (PDT) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 2/3] interconnect: qcom: sa8775p: enable QoS configuration Date: Fri, 8 Aug 2025 19:32:59 +0530 Message-Id: <20250808140300.14784-3-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> References: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=TJpFS0la c=1 sm=1 tr=0 ts=689603d2 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=I8WKV2cH2hVkXcs4O-MA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: u5GHqY2b3Yoz7YS1Eb_pa6--AkemX3GP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA3MDA0NiBTYWx0ZWRfX1TBgXnZbgZBh lo6N5KTD3NrH5Ml67Wdho1sSTcdrFL0/rMtQJo/ReKID9i4FKYu1ZpEB2WntRqXyV/yyCi9lHG5 z82reDHa7jUa0R4NB2F2sPqx4+Q5pXGSQitN4yY1wy/4flT1BTeyYK8jfYzKc0bYEr5cn6yXqca q6LAqEKZ4B5JXPDJp+vFd1OTvIng98IfDHCaI+xBIgRzb7OSpeIvQ8P5fkGg2eScZ+fRE2Kgcwh u6jXQgUqE+a5w+H0ECInJpFetxYGjRb5esRyJIefMG8f+XpQivCas13PqXai9cj2AKnbb14177K Z3eTXwJrQwo+v9+/R0H1VB4GA2lC+UvG3+hCTovbTzyhFrxbPZA1zHddnRGd+BCPI3NSn0KVNC2 xG4ujqpT X-Proofpoint-ORIG-GUID: u5GHqY2b3Yoz7YS1Eb_pa6--AkemX3GP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_04,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508070046 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Enable QoS configuration for master ports with predefined priority and urgency forwarding. Signed-off-by: Odelu Kukatla --- drivers/interconnect/qcom/sa8775p.c | 439 ++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index 04b4abbf4487..5bf27dbe818d 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -213,6 +213,13 @@ static struct qcom_icc_node qxm_qup3 =3D { .name =3D "qxm_qup3", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -221,6 +228,13 @@ static struct qcom_icc_node xm_emac_0 =3D { .name =3D "xm_emac_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -229,6 +243,13 @@ static struct qcom_icc_node xm_emac_1 =3D { .name =3D "xm_emac_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -237,6 +258,13 @@ static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -245,6 +273,13 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -253,6 +288,13 @@ static struct qcom_icc_node xm_usb2_2 =3D { .name =3D "xm_usb2_2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -261,6 +303,13 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -269,6 +318,13 @@ static struct qcom_icc_node xm_usb3_1 =3D { .name =3D "xm_usb3_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, }; @@ -277,6 +333,13 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -285,6 +348,13 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -293,6 +363,13 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -301,6 +378,13 @@ static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -309,6 +393,13 @@ static struct qcom_icc_node qnm_cnoc_datapath =3D { .name =3D "qnm_cnoc_datapath", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -317,6 +408,13 @@ static struct qcom_icc_node qxm_crypto_0 =3D { .name =3D "qxm_crypto_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -325,6 +423,13 @@ static struct qcom_icc_node qxm_crypto_1 =3D { .name =3D "qxm_crypto_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -333,6 +438,13 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -341,6 +453,13 @@ static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -349,6 +468,13 @@ static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -357,6 +483,13 @@ static struct qcom_icc_node xm_ufs_card =3D { .name =3D "xm_ufs_card", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, }; @@ -461,6 +594,13 @@ static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb4000 }, + .prio_fwd_disable =3D 1, + .prio =3D 1, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -469,6 +609,13 @@ static struct qcom_icc_node alm_pcie_tcu =3D { .name =3D "alm_pcie_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb5000 }, + .prio_fwd_disable =3D 1, + .prio =3D 3, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -477,6 +624,13 @@ static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb6000 }, + .prio_fwd_disable =3D 1, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -494,6 +648,13 @@ static struct qcom_icc_node qnm_cmpnoc0 =3D { .name =3D "qnm_cmpnoc0", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf3000, 0xf4000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -502,6 +663,13 @@ static struct qcom_icc_node qnm_cmpnoc1 =3D { .name =3D "qnm_cmpnoc1", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf5000, 0xf6000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -527,6 +695,13 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xed000, 0xee000 }, + .prio_fwd_disable =3D 1, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -535,6 +710,13 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xef000, 0xf0000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie }, }; @@ -543,6 +725,13 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xf1000, 0xf2000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -552,6 +741,13 @@ static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb8000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc= }, }; @@ -560,6 +756,13 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb9000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_llcc }, }; @@ -568,6 +771,13 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xba000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie }, @@ -620,6 +830,13 @@ static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -628,6 +845,13 @@ static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -636,6 +860,13 @@ static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -644,6 +875,13 @@ static struct qcom_icc_node qnm_mdp0_0 =3D { .name =3D "qnm_mdp0_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa080 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -652,6 +890,13 @@ static struct qcom_icc_node qnm_mdp0_1 =3D { .name =3D "qnm_mdp0_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -660,6 +905,13 @@ static struct qcom_icc_node qnm_mdp1_0 =3D { .name =3D "qnm_mdp1_0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -668,6 +920,13 @@ static struct qcom_icc_node qnm_mdp1_1 =3D { .name =3D "qnm_mdp1_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, }; @@ -692,6 +951,13 @@ static struct qcom_icc_node qnm_video0 =3D { .name =3D "qnm_video0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a100 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -700,6 +966,13 @@ static struct qcom_icc_node qnm_video1 =3D { .name =3D "qnm_video1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a180 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -708,6 +981,13 @@ static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a200 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -716,6 +996,13 @@ static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2a280 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, }; @@ -756,6 +1043,13 @@ static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -764,6 +1058,13 @@ static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_pcie_mem_noc }, }; @@ -772,6 +1073,13 @@ static struct qcom_icc_node qhm_gic =3D { .name =3D "qhm_gic", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -796,6 +1104,13 @@ static struct qcom_icc_node qnm_lpass_noc =3D { .name =3D "qnm_lpass_noc", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio_fwd_disable =3D 0, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, }; @@ -812,6 +1127,13 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -820,6 +1142,13 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio_fwd_disable =3D 1, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D (struct qcom_icc_node *[]) { &qns_gemnoc_gc }, }; @@ -1836,12 +2165,22 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, }; =20 +static const struct regmap_config sa8775p_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x18080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_aggre1_noc =3D { + .config =3D &sa8775p_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { @@ -1864,12 +2203,22 @@ static struct qcom_icc_node * const aggre2_noc_node= s[] =3D { [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, }; =20 +static const struct regmap_config sa8775p_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1b080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_aggre2_noc =3D { + .config =3D &sa8775p_aggre2_noc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), .alloc_dyn_id =3D true, + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { @@ -1995,7 +2344,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_TCU] =3D &xs_sys_tcu_cfg, }; =20 +static const struct regmap_config sa8775p_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x13080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_config_noc =3D { + .config =3D &sa8775p_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -2012,7 +2370,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_GEM_NOC_CFG] =3D &qns_gemnoc, }; =20 +static const struct regmap_config sa8775p_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_dc_noc =3D { + .config =3D &sa8775p_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), .bcms =3D dc_noc_bcms, @@ -2049,7 +2416,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC2] =3D &srvc_sys_gemnoc_2, }; =20 +static const struct regmap_config sa8775p_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xf6080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_gem_noc =3D { + .config =3D &sa8775p_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -2068,7 +2444,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes= [] =3D { [SLAVE_GP_DSP_SAIL_NOC] =3D &qns_gp_dsp_sail_noc, }; =20 +static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_gpdsp_anoc =3D { + .config =3D &sa8775p_gpdsp_anoc_regmap_config, .nodes =3D gpdsp_anoc_nodes, .num_nodes =3D ARRAY_SIZE(gpdsp_anoc_nodes), .bcms =3D gpdsp_anoc_bcms, @@ -2092,7 +2477,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nod= es[] =3D { [SLAVE_SERVICE_LPASS_AG_NOC] =3D &srvc_niu_lpass_agnoc, }; =20 +static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_lpass_ag_noc =3D { + .config =3D &sa8775p_lpass_ag_noc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), .bcms =3D lpass_ag_noc_bcms, @@ -2143,7 +2537,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, }; =20 +static const struct regmap_config sa8775p_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x40000, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_mmss_noc =3D { + .config =3D &sa8775p_mmss_noc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -2164,7 +2567,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[]= =3D { [SLAVE_SERVICE_NSP_NOC] =3D &service_nsp_noc, }; =20 +static const struct regmap_config sa8775p_nspa_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_nspa_noc =3D { + .config =3D &sa8775p_nspa_noc_regmap_config, .nodes =3D nspa_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspa_noc_nodes), .bcms =3D nspa_noc_bcms, @@ -2177,6 +2589,14 @@ static struct qcom_icc_bcm * const nspb_noc_bcms[] = =3D { &bcm_nsb1, }; =20 +static const struct regmap_config sa8775p_nspb_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16080, + .fast_io =3D true, +}; + static struct qcom_icc_node * const nspb_noc_nodes[] =3D { [MASTER_CDSPB_NOC_CFG] =3D &qhm_nspb_noc_config, [MASTER_CDSP_PROC_B] =3D &qxm_nspb, @@ -2186,6 +2606,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sa8775p_nspb_noc =3D { + .config =3D &sa8775p_nspb_noc_regmap_config, .nodes =3D nspb_noc_nodes, .num_nodes =3D ARRAY_SIZE(nspb_noc_nodes), .bcms =3D nspb_noc_bcms, @@ -2203,7 +2624,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[= ] =3D { [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, }; =20 +static const struct regmap_config sa8775p_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xc080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_pcie_anoc =3D { + .config =3D &sa8775p_pcie_anoc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -2232,7 +2662,16 @@ static struct qcom_icc_node * const system_noc_nodes= [] =3D { [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, }; =20 +static const struct regmap_config sa8775p_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x15080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc sa8775p_system_noc =3D { + .config =3D &sa8775p_system_noc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --=20 2.17.1 From nobody Mon Feb 9 01:39:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FC0127F4CE for ; Fri, 8 Aug 2025 14:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661848; cv=none; b=orh8XXnnytZKLy48Awa1scGlfv/xqg27pO0Bo3WJ5Zwt/JHwdIX1VaqqbnYvqcGo7+kFq/Te9fXz4LEu6NvCbUFKRfnXQFW4rhqTqqnJ/6cegeYDjgcdhzxT1fEg6VfgS0qttfP7HozhPQt9b1bc7Zhr3BPMuhXlVdQeHc5h7FI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754661848; c=relaxed/simple; bh=ZcE/MeEUMeGZH7b8eex156Qe1QyWbt01WWmziNtbiYo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=CUIqB+rC+BxeOQi6jSVBas/6tjWKy02ZMX5TsyrKGDUevz/Je7XDExsQcvL7Y1ocsQsEZjKk1makczPbeFq7Sw2G0eDVh4yRWhrZ5N2CsnNPesDOra7LJtrkNUKaVS53mr78PcqjwaRGee+6efivOKQMEe42GWN9vWxmcs4BNTE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ohHUP9ZB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ohHUP9ZB" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 578DhDtK022425 for ; Fri, 8 Aug 2025 14:04:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:date:from:in-reply-to:message-id:references:subject:to; s= qcppdkim1; bh=NyOKCYdO8dRhX3Md2A7GJTuQQJa5hPZwpwoviRAY2wY=; b=oh HUP9ZBpWl90yj/7E65pT15eHepWZjgloKgxZQFrfaD3o7b9iBO9llSt1XWzoAaF7 R7B/c0oEHE5mab3s8LB0eXQyK3DUA8VqIhv/C0cmHpt9JRY0A3/k1hEAwhPV+OxC y9c3Ptb4EfYnpzxLXwyCKnhk04QiPkiyy8LZPadIKvW5XluVU+mC00srULJIm47f WYOOMbFmMRVvs4HSIJFcXwsvWl8+xh0J0Cidu6Zd2Kb03P0we65aDRxN8TEbtszq 6QBBhi/4liR2BGM4Zujj23q971Sd7SZJhHKpD0octitPOs59iEXSJ9JnjnaQS2GK IifOHmm3x4wWhCIiAuAw== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48cs5nchg7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Fri, 08 Aug 2025 14:04:06 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-76bca6c73f3so4386837b3a.1 for ; Fri, 08 Aug 2025 07:04:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754661844; x=1755266644; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NyOKCYdO8dRhX3Md2A7GJTuQQJa5hPZwpwoviRAY2wY=; b=MezwtLG5Ga3We66CqklrCSWq35CRBxRQ4TGXXcfGCcNGyKiFljDvxgCZlBpEeXEj6X cSbNw/LIrLP2tNN16iVZult182J6DOjYfgUmtqcx/t+9Jmk5RzRKPFvm6FPVIziWCGpN 0HpWG+8fcEVMkdyW/AnR7ndm1FenEdNitr0s+AwiaI5I3OLQg/Sv3vrIS74TBVwnxeIn yPNbcd7Yx3sz5uYiwYPaae5scR861DAYdqH6MJdw3PWInyhcjEo5M0MEZtSrGfMHm2Jy JB3peEkiQZAz/NoV1JTtQ06Fu5Tpqzsp2h9TTuRYcn8wR6Ob7gTzhj/OrPXXhClt+HSw w6jQ== X-Forwarded-Encrypted: i=1; AJvYcCVyYNVdzyfpY1QnrKqLEjpXY+6fZRvLvfl3mmA4srpDp1sVVB16zkVSUYmFGov1MjkIR+4duJodK83y78E=@vger.kernel.org X-Gm-Message-State: AOJu0YzC5hb+nxELcAQwy/L+Ul2iZ1OTK3ETZK61TF+Lu4hQYiGJKpCN iRX//2bzQ7KjywbWDqhj5m3jn3EVaatM/SU0ejzSUTfj4vzMy7QaQaHRVxxwgrzpnlDSkjWnzud 8t4JHZuTUUXu6MfKHPZKzwyqy2KcOJ6N/YMWi/nbre2A9EXq0P1Eb8wySbXzaYGLlDB0= X-Gm-Gg: ASbGncuIavNYb6KV5VU0JWGlPhs3QIYK3OhmKJWo24CR8Vt6AZIym9gKugYSzspdd+r VMrLt3JT+q7oFN1le7idDaDCfPRBQTLO20qWnUWhZ+s3mOaeNKWR6X1AYfJKQkR5yUMcxT0ItjM 1DtRpwNwM+G93N0qOUH1zN8aCY/ag1rzR5gr7D2l/uZCC200+WoNnbXBls96tvlpmoffHjQr2U4 7Ko2Juxq4TsdtpKtwXo6RduIdJyMgK9R6PAx5sT05B1DGM1lOADWw2N1DSX9XmgTPCzxdO9LDtd yEdsApOtFXvdEtfur6J8Kki0Iu034ROHUXrUypQtpuvhCF27ZzJxOK9/BIakjNPjC1vh1woLHg= = X-Received: by 2002:a05:6a00:1409:b0:76b:f7af:c47d with SMTP id d2e1a72fcca58-76c460aa949mr4709696b3a.4.1754661844270; Fri, 08 Aug 2025 07:04:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEYzNEZoLYuCQsfE6sjScDxUN0v6Z/1i5E9FkZw7qvQySEK/E4ALZ6kvXwvvo8//QKF944E+Q== X-Received: by 2002:a05:6a00:1409:b0:76b:f7af:c47d with SMTP id d2e1a72fcca58-76c460aa949mr4709633b3a.4.1754661843723; Fri, 08 Aug 2025 07:04:03 -0700 (PDT) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76c2078afd8sm8595621b3a.117.2025.08.08.07.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Aug 2025 07:04:03 -0700 (PDT) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH 3/3] arm64: dts: qcom: sa8775p: Add clocks for QoS configuration Date: Fri, 8 Aug 2025 19:33:00 +0530 Message-Id: <20250808140300.14784-4-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> References: <20250808140300.14784-1-odelu.kukatla@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=Q+XS452a c=1 sm=1 tr=0 ts=689603d6 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=BfUXBPTVPglUz1mEt9YA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: P9ElSucQJ9E2STIy1BwCfM6ClUJiN1uO X-Proofpoint-ORIG-GUID: P9ElSucQJ9E2STIy1BwCfM6ClUJiN1uO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA3MDA2OSBTYWx0ZWRfXwwc2Vo3RfoFL rc0X5VeEaps9NaedAMzDnIhia3GywZvuX51G0THH/glgg/tjgtMOTa0xvNAti6taI37l2imijO+ jFh+njQolOJxI8QvpUhkCc5jBj9kCfjqAyRnUwbXMZSakR8zxVEY4mqcbNcIrYXhy5TeVZP2+S9 F5CeI3ERTa3lVaugOtX3p2AqVVXC6Zk0sKD0vJiuxSb+phbgv+TSFuVSv79QOnVmeotO2ty4jUx uT+cg8wtOg6glwUMhx9mtGO6I/5JAlA11iacZyunm3jpreRwiekgqGjTVrUzODeqGfupqtMbWOl PQf9JWPaBZfFzfMoDeIjf0obWfpWh1zdZG8TpsIGYOGd6qOXw/e87Qn0IaucMrp4abTmhXcBls/ bjJ2GSrN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-08_04,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508070069 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add register addresses and clocks which need to be enabled for configuring QoS on sa8775p SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 163 ++++++++++++++------------ 1 file changed, 91 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9997a29901f5..a24c1ce4384f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -518,90 +518,18 @@ }; }; =20 - aggre1_noc: interconnect-aggre1-noc { - compatible =3D "qcom,sa8775p-aggre1-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible =3D "qcom,sa8775p-aggre2-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible =3D "qcom,sa8775p-clk-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - config_noc: interconnect-config-noc { - compatible =3D "qcom,sa8775p-config-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible =3D "qcom,sa8775p-dc-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible =3D "qcom,sa8775p-gem-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - gpdsp_anoc: interconnect-gpdsp-anoc { - compatible =3D "qcom,sa8775p-gpdsp-anoc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect-lpass-ag-noc { - compatible =3D "qcom,sa8775p-lpass-ag-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible =3D "qcom,sa8775p-mc-virt"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 - mmss_noc: interconnect-mmss-noc { - compatible =3D "qcom,sa8775p-mmss-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible =3D "qcom,sa8775p-nspa-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible =3D "qcom,sa8775p-nspb-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - pcie_anoc: interconnect-pcie-anoc { - compatible =3D "qcom,sa8775p-pcie-anoc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible =3D "qcom,sa8775p-system-noc"; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; - /* Will be updated by the bootloader. */ memory@80000000 { device_type =3D "memory"; @@ -2675,6 +2603,62 @@ reg =3D <0 0x010d2000 0 0x1000>; }; =20 + config_noc: interconnect@14c0000 { + compatible =3D "qcom,sa8775p-config-noc"; + reg =3D <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@01680000 { + compatible =3D "qcom,sa8775p-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,sa8775p-aggre1-noc"; + reg =3D <0x0 0x016c0000 0x0 0x18080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sa8775p-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1b080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + pcie_anoc: interconnect@1760000 { + compatible =3D "qcom,sa8775p-pcie-anoc"; + reg =3D <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible =3D "qcom,sa8775p-gpdsp-anoc"; + reg =3D <0x0 0x01780000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible =3D "qcom,sa8775p-mmss-noc"; + reg =3D <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; @@ -2784,6 +2768,13 @@ }; }; =20 + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,sa8775p-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + stm: stm@4002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x4002000 0x0 0x1000>, @@ -3859,6 +3850,20 @@ status =3D "disabled"; }; =20 + dc_noc: interconnect@90e0000 { + compatible =3D "qcom,sa8775p-dc-noc"; + reg =3D <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible =3D "qcom,sa8775p-gem-noc"; + reg =3D <0x0 0x09100000 0x0 0xf6080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + usb_0: usb@a6f8800 { compatible =3D "qcom,sa8775p-dwc3", "qcom,dwc3"; reg =3D <0 0x0a6f8800 0 0x400>; @@ -6224,6 +6229,13 @@ status =3D "disabled"; }; =20 + nspa_noc: interconnect@260c0000 { + compatible =3D "qcom,sa8775p-nspa-noc"; + reg =3D <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_cdsp0: remoteproc@26300000 { compatible =3D "qcom,sa8775p-cdsp0-pas"; reg =3D <0x0 0x26300000 0x0 0x10000>; @@ -6356,6 +6368,13 @@ }; }; =20 + nspb_noc: interconnect@2a0c0000 { + compatible =3D "qcom,sa8775p-nspb-noc"; + reg =3D <0x0 0x2a0c0000 0x0 0x16080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + remoteproc_cdsp1: remoteproc@2a300000 { compatible =3D "qcom,sa8775p-cdsp1-pas"; reg =3D <0x0 0x2A300000 0x0 0x10000>; --=20 2.17.1