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Each GAMMA IP of this SoC is fully compatible with the ones found in MT8195. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ga= mma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamm= a.yaml index 48542dc7e784..513e51c6d2b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - mediatek,mt8188-disp-gamma + - mediatek,mt8196-disp-gamma - const: mediatek,mt8195-disp-gamma =20 reg: --=20 2.46.0 From nobody Sun Dec 14 02:02:06 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23EC527AC41; Fri, 8 Aug 2025 12:57:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add a compatible string for the DITHER IP found in the MT8196 SoC. Each DITHER IP of this SoC is fully compatible with the ones found in MT8183. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,di= ther.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dit= her.yaml index abaf27916d13..25ef7d0c2a2b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml @@ -30,6 +30,7 @@ properties: - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither + - mediatek,mt8196-disp-dither - mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-dither =20 --=20 2.46.0 From nobody Sun Dec 14 02:02:06 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6440327A903; 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charset="utf-8" Add a compatible string for the CCORR IP found in the MT8196 SoC. Each CCORR IP of this SoC is fully compatible with the ones found in MT8192. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cc= orr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccor= r.yaml index fca8e7bb0cbc..581003aa9b9c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8186-disp-ccorr - mediatek,mt8188-disp-ccorr - mediatek,mt8195-disp-ccorr + - mediatek,mt8196-disp-ccorr - const: mediatek,mt8192-disp-ccorr =20 reg: --=20 2.46.0 From nobody Sun Dec 14 02:02:06 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C54A27B4F7; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Add disp-tdshp hardware description for MediaTek MT8196 SoC Signed-off-by: Jay Liu --- .../display/mediatek/mediatek,disp-tdshp.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,disp-tdshp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,di= sp-tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek= ,disp-tdshp.yaml new file mode 100644 index 000000000000..94aa33a2a5ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdsh= p.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,disp-tdshp.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display 2D sharpness processor + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display 2D sharpness processor, namely TDSHP, provides a + operation used to adjust sharpness in=C2=A0display system. + TDSHP device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. + +properties: + compatible: + items: + - enum: + - mediatek,mt8196-disp-tdshp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + + soc { + #address-cells =3D <2>; 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charset="utf-8" Add CCORR component support for MT8196. CCORR is a hardware module that optimizes the visual effects of images by adjusting the color matrix, enabling features such as night light. The 8196 SoC has two CCORR hardware units, which must be chained together in a fixed order in the display path to display the image correctly. the `mtk_ccorr_ctm_set` API only utilizes one of these units. To prevent the unused CCORR unit from inadvertently taking effect, we need to block it in the mtk_crtc.c. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_crtc.c | 5 ++++- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 ++- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 7 ++++--- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++-- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index bc7527542fdc..6b9cb52e9207 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -859,11 +859,14 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *cr= tc, { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); int i; + bool ctm_set =3D false; =20 if (crtc->state->color_mgmt_changed) for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); - mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); + /* only set ctm once for the pipeline with two CCORR components */ + if (!ctm_set) + ctm_set =3D mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); } mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event); } diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index ac6620e10262..850e3b18da61 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -458,7 +458,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_AAL0] =3D { MTK_DISP_AAL, 0, &ddp_aal }, [DDP_COMPONENT_AAL1] =3D { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] =3D { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] =3D { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_CCORR0] =3D { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_CCORR1] =3D { MTK_DISP_CCORR, 1, &ddp_ccorr }, [DDP_COMPONENT_COLOR0] =3D { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] =3D { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DITHER0] =3D { MTK_DISP_DITHER, 0, &ddp_dither }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 7289b3dcf22f..98a701ac4cde 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -77,7 +77,7 @@ struct mtk_ddp_comp_funcs { struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); void (*bgclr_in_off)(struct device *dev); - void (*ctm_set)(struct device *dev, + bool (*ctm_set)(struct device *dev, struct drm_crtc_state *state); struct device * (*dma_dev_get)(struct device *dev); u32 (*get_blend_modes)(struct device *dev); @@ -254,11 +254,12 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct m= tk_ddp_comp *comp) comp->funcs->bgclr_in_off(comp->dev); } =20 -static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, +static inline bool mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { if (comp->funcs && comp->funcs->ctm_set) - comp->funcs->ctm_set(comp->dev, state); + return comp->funcs->ctm_set(comp->dev, state); + return false; } =20 static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp = *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/me= diatek/mtk_disp_ccorr.c index 10d60d2c2a56..85ba109d6383 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -101,7 +101,7 @@ static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) return r; } =20 -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); struct drm_property_blob *blob =3D state->ctm; @@ -113,7 +113,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_c= rtc_state *state) u32 matrix_bits =3D ccorr->data->matrix_bits; =20 if (!blob) - return; + return false; =20 ctm =3D (struct drm_color_ctm *)blob->data; input =3D ctm->matrix; @@ -131,6 +131,8 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_c= rtc_state *state) &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); + + return true; } =20 static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 679d413bf10b..4203c28c38ce 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -22,7 +22,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state); 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Fri, 08 Aug 2025 20:57:18 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 8 Aug 2025 20:57:15 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 8 Aug 2025 20:57:14 +0800 From: Jay Liu To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Jay Liu , CK Hu Subject: [PATCH v3 6/6] drm/mediatek: Add TDSHP component support for MT8196 Date: Fri, 8 Aug 2025 20:54:01 +0800 Message-ID: <20250808125512.9788-7-jay.liu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250808125512.9788-1-jay.liu@mediatek.com> References: <20250808125512.9788-1-jay.liu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add TDSHP component support for MT8196. TDSHP is a hardware module designed to enhance the sharpness and clarity of displayed images by analyzing and improving edges and fine details in frames. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jay Liu --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 49 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + 3 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 850e3b18da61..c63a12c41215 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -57,6 +57,14 @@ #define POSTMASK_RELAY_MODE BIT(0) #define DISP_REG_POSTMASK_SIZE 0x0030 =20 +#define DISP_REG_TDSHP_CTRL 0x0100 +#define DISP_TDSHP_CTRL_EN BIT(0) +#define DISP_REG_TDSHP_CFG 0x0110 +#define DISP_TDSHP_RELAY_MODE BIT(0) +#define DISP_REG_TDSHP_INPUT_SIZE 0x0120 +#define DISP_REG_TDSHP_OUTPUT_OFFSET 0x0124 +#define DISP_REG_TDSHP_OUTPUT_SIZE 0x0128 + #define DISP_REG_UFO_START 0x0000 #define UFO_BYPASS BIT(2) =20 @@ -261,6 +269,37 @@ static void mtk_postmask_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); } =20 +static void mtk_disp_tdshp_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_OUTPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, + DISP_REG_TDSHP_OUTPUT_OFFSET); + + mtk_ddp_write(cmdq_pkt, DISP_TDSHP_RELAY_MODE, &priv->cmdq_reg, + priv->regs, DISP_REG_TDSHP_CFG); +} + +static void mtk_disp_tdshp_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL); +} + +static void mtk_disp_tdshp_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + writel(0, priv->regs + DISP_REG_TDSHP_CTRL); +} + static void mtk_ufoe_start(struct device *dev) { struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); @@ -268,6 +307,14 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } =20 +static const struct mtk_ddp_comp_funcs ddp_tdshp =3D { + .clk_enable =3D mtk_ddp_clk_enable, + .clk_disable =3D mtk_ddp_clk_disable, + .config =3D mtk_disp_tdshp_config, + .start =3D mtk_disp_tdshp_start, + .stop =3D mtk_disp_tdshp_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_aal =3D { .clk_enable =3D mtk_aal_clk_enable, .clk_disable =3D mtk_aal_clk_disable, @@ -441,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_POSTMASK] =3D "postmask", [MTK_DISP_PWM] =3D "pwm", [MTK_DISP_RDMA] =3D "rdma", + [MTK_DISP_TDSHP] =3D "tdshp", [MTK_DISP_UFOE] =3D "ufoe", [MTK_DISP_WDMA] =3D "wdma", [MTK_DP_INTF] =3D "dp-intf", @@ -496,6 +544,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_RDMA1] =3D { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] =3D { MTK_DISP_RDMA, 2, &ddp_rdma }, [DDP_COMPONENT_RDMA4] =3D { MTK_DISP_RDMA, 4, &ddp_rdma }, + [DDP_COMPONENT_TDSHP0] =3D { MTK_DISP_TDSHP, 0, &ddp_tdshp }, [DDP_COMPONENT_UFOE] =3D { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] =3D { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] =3D { MTK_DISP_WDMA, 1, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 98a701ac4cde..a03fa3385d2f 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, + MTK_DISP_TDSHP, MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index d5e6bab36414..042cf03c7a54 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -812,6 +812,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_RDMA }, { .compatible =3D "mediatek,mt8195-disp-rdma", .data =3D (void *)MTK_DISP_RDMA }, + { .compatible =3D "mediatek,mt8196-disp-tdshp", + .data =3D (void *)MTK_DISP_TDSHP }, { .compatible =3D "mediatek,mt8173-disp-ufoe", .data =3D (void *)MTK_DISP_UFOE }, { .compatible =3D "mediatek,mt8173-disp-wdma", --=20 2.46.0