From nobody Tue Dec 16 08:00:18 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EE85273D74; Fri, 8 Aug 2025 09:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754646276; cv=none; b=rvgv2FCPHqNkztWSzbxN2ykmgZmtWLipWhy+4Ql9YgcsIxdsA+ejJmKAOkMS3FrlNhlgEUs1kqDhLD4Y33XvkCIG6VJ1kzuHTIVfM9yuT1GoPfkJu8abL2AzJhvBIqxi8kxrYx07aNyLXGsw5FfhAVJlkFdEzatUDgWn0Agskz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754646276; c=relaxed/simple; bh=ajJkn2rR1tM7L+hlXIfE6Ac5tEpM02G6+RdV1+gRsGo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XfO8529FYWPK+VtQH3O6/joCwSCViISTlBzSq6d++t0tuYJaCecyEYpCyObA0h9BdM0X8bV+ErTquxb7owmW+BKKs2sNHmeURefOwyAyTGhs8rabdu7he33+mE9tIC6852wawVM4H6Fu6v00Mq2Sn1VfxqVMKkCLtPZESFNPlGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=JybmdVyl; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="JybmdVyl" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id C5AD22093B; Fri, 8 Aug 2025 11:44:32 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id pSeEIdqlRFtF; Fri, 8 Aug 2025 11:44:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1754646272; bh=ajJkn2rR1tM7L+hlXIfE6Ac5tEpM02G6+RdV1+gRsGo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JybmdVylgPRleVDjovbA2Dctq0OezgzR/rAOTF3LYY4tUfpDcdZz7e/VNyoQI0YdV ftwpNXkUC2/xOcLhGTCi/9Otu3cS4fLdd7QXBF+L5kgeQHaxpKOUrxdZRjNoFHxm0n KJfeYKEloOAkMrFkB+s2kTf8QoMCxEZm7IJLd037ypam2RZLHPvvNmaCBZcyBVgUW8 1SgAZVXuUdR4RiNkPtAFH8Isw9EEt5uaxt3rNJypLtxBjnrTnWJojOQqtCv5+/2OMs XfNq+/YMrpzwhz+P0fKIO2MIIzkM4yjLfPsVThzUR+ZH0RqGO2xztKv4YubZCpLAKS 1MWau214tA2dw== From: Yao Zi To: Drew Fustini , Guo Ren , Fu Wei , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Jisheng Zhang Cc: linux-riscv@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yao Zi Subject: [PATCH net v3 2/3] net: stmmac: thead: Get and enable APB clock on initialization Date: Fri, 8 Aug 2025 09:36:55 +0000 Message-ID: <20250808093655.48074-4-ziyao@disroot.org> In-Reply-To: <20250808093655.48074-2-ziyao@disroot.org> References: <20250808093655.48074-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's necessary to adjust the MAC TX clock when the linkspeed changes, but it's noted such adjustment always fails on TH1520 SoC, and reading back from APB glue registers that control clock generation results in garbage, causing broken link. With some testing, it's found a clock must be ungated for access to APB glue registers. Without any consumer, the clock is automatically disabled during late kernel startup. Let's get and enable it if it's described in devicetree. For backward compatibility with older devicetrees, probing won't fail if the APB clock isn't found. In this case, we emit a warning since the link will break if the speed changes. Fixes: 33a1a01e3afa ("net: stmmac: Add glue layer for T-HEAD TH1520 SoC") Signed-off-by: Yao Zi Tested-by: Drew Fustini Reviewed-by: Drew Fustini --- drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-thead.c index c72ee759aae5..f2946bea0bc2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -211,6 +211,7 @@ static int thead_dwmac_probe(struct platform_device *pd= ev) struct stmmac_resources stmmac_res; struct plat_stmmacenet_data *plat; struct thead_dwmac *dwmac; + struct clk *apb_clk; void __iomem *apb; int ret; =20 @@ -224,6 +225,19 @@ static int thead_dwmac_probe(struct platform_device *p= dev) return dev_err_probe(&pdev->dev, PTR_ERR(plat), "dt configuration failed\n"); =20 + /* + * The APB clock is essential for accessing glue registers. However, + * old devicetrees don't describe it correctly. We continue to probe + * and emit a warning if it isn't present. + */ + apb_clk =3D devm_clk_get_enabled(&pdev->dev, "apb"); + if (PTR_ERR(apb_clk) =3D=3D -ENOENT) + dev_warn(&pdev->dev, + "cannot get apb clock, link may break after speed changes\n"); + else if (IS_ERR(apb_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(apb_clk), + "failed to get apb clock\n"); + dwmac =3D devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); if (!dwmac) return -ENOMEM; --=20 2.50.1