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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9B9D7416050B; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 11/12] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Fri, 8 Aug 2025 15:29:28 +0800 Message-ID: <20250808072929.4090694-12-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB86:EE_|KU2PPF1A2CB34C0:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d392f48-e042-48a0-8938-08ddd64d5415 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aWtA30K0zA4f3lve4U99k1FaysfMZYYocY+XQa5UWNL2ELcw6Ps0U+FTgTTz?= =?us-ascii?Q?dsQYrUgr9F1ohzjC5hWL27+doz4umxdjWTHgZuX2Wv3yeKNtDrrDdkAMdYc/?= =?us-ascii?Q?Z2iSuCMohNiJGS34YqnCTRudATFuUlF520DsRkQ+Z5YXkJ0fxnlNx2VMrEzk?= =?us-ascii?Q?foMBoZ1z9Nzi2j7Sz0qoOfaVw49XZngSZIEgEBSdEHgvbdf2tI/YWmnMkhpr?= =?us-ascii?Q?1L5S3O8u9XYTTexJS9xuU7QdCIlRp32FlSB1fh8N1Ki20RpwYy6jHiOOJqdH?= =?us-ascii?Q?O9hqkYfvaIoiwHX/DL3RXJv3ADmrb+Fa6KoWqOgBjxJFzjlrN7C5Kj4GqaVN?= =?us-ascii?Q?Ceh7jq7+JbR6SqsIHfBc19oHzEaaKWU4k0huHLpRuQhgGzFIvVqqRKQxp5c0?= =?us-ascii?Q?/mOQnl0LS3AdNNMgfU89zIyjCuFeFqIvv82m7/bzLBQglh83M6UnNE+TZtjQ?= =?us-ascii?Q?5Aq39Q4wc3g11tmcGF8RtBImIadGChfWMTi+ns4LSvI8KFZT368vpIzSyzEc?= =?us-ascii?Q?kl3RZjvfepSV7vLeD03ymRoMDxbAQLj26doHXABFehgrjH+PtQM2muD4cj44?= =?us-ascii?Q?83bbZvbEh1rr+8Zy01K/zzMqQvCRakOqIT8ZJAaW3Ty2LAwIw5AGfmDHcjg/?= =?us-ascii?Q?oCGPKuI+/Oi8PM2eRaIKZ5rlqCNh8bwqpFm5UIGFoON6jnWxdTfXRPul55Hz?= =?us-ascii?Q?37hGHFuHroU+WPjqJj8TWtIpjMWwzIEks8h9A67iewVzfCMirAW1TDGt/YL0?= =?us-ascii?Q?cJIlVpGKATlJKBHGGhEwfl9hoPqN1cAu8k4/5wHIlwkg8LvQH2IRpWbID3tf?= =?us-ascii?Q?PsnmhIePx2qha6RcLsrHaSwYkxmAEdEHoFxaq3l95ZBZ8a5GoIjcDz+JpOEk?= =?us-ascii?Q?DDeNtz/WIFW/0vpJVwWx4q0F1W7CSWZAafRCtaAWPe9+la0N/3RorvClKWfv?= =?us-ascii?Q?wDjwWBXK9mlKkHySZuY3P48bBC37bbZitp6LnJjPYAys7fEHA2KLHoNg0liB?= =?us-ascii?Q?WJAPwPhfZV2vX+E1217PGvQPO9uEqQTKHVl6ynd7dANX66FpzzTDZQfV2OFT?= =?us-ascii?Q?omcXvoWuDPVXxdVTzImk6I1QZ0RBiTvu6F7g8rnljRPLW1DfnYdDEuFKVT+H?= =?us-ascii?Q?+Ueopq2aI7GrwbtGy48mX+/V65iegorDVnMgZ5LPW+0OQnW25GMGxqvl9dlS?= =?us-ascii?Q?ld0HpWDtjBW8m1Fdr3nPNoNaoV7hA0UZmuFrwl0gZHWmDiN2Z/RPQuUUx42Z?= =?us-ascii?Q?09aJYNOdighGeRD6SyFwYzrW4uvuJ/PtQc92XrhCWdCv+gQwXMR4qcoHsZU3?= =?us-ascii?Q?JIpo+e4wo0zCbjC9DoF2ds9navrluB98YrAP7LN+ttcneHm7tqReeM2jEz8f?= =?us-ascii?Q?Cj7M4M7rBeUt5RWkIZceNQTHsixMRTWPXapmLLfXTxVkV7uThTASgVIyWoj3?= =?us-ascii?Q?3Ul5FxP9TbzKiFp6XYDJOpOfPGmJ2l5FcoLD09Ef5dWhR4mGwOQiX+JdOgSY?= =?us-ascii?Q?EOF0klQKQ7ptYMa/BW2DH5BNgruKkATtY7qh?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.5729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d392f48-e042-48a0-8938-08ddd64d5415 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB86.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KU2PPF1A2CB34C0 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang --- arch/arm64/boot/dts/cix/sky1.dtsi | 121 ++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 7dfe7677e649..04ba80d4fc06 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -288,6 +288,127 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a060040 0x00 0x10000>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060060 0x00 0x10000>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060080 0x00 0x10000>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x30 0x5f>; + device_type =3D "pci"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x3000 &gic_its 0x3000 0x3000>; + status =3D "disabled"; + }; + gic: interrupt-controller@e010000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ --=20 2.49.0