From nobody Sun Oct 5 05:27:11 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023077.outbound.protection.outlook.com [40.107.44.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 458F323AE79; Fri, 8 Aug 2025 07:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638183; cv=fail; b=G/SmERK9y07NjtKbsUbP/cen79fvhNWQTvY2nMBm2+u1ionOVfLGFXVyrTMEgHF5uufNzBd+sblvD2e0aXZTeIw0x2Q1cjvJj22IXqQvnUTlvsKefwN3sbrcj6IhZeYDS8WEXDUc0C6Ott0aLFP+Ui5XMRtFY8ps65eAeWkPtzQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638183; c=relaxed/simple; bh=xVUlZ6Vi0AYHbrHYLt9vTfCi7MWlwWWwm6X2v2pecAI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tT3AWrJ5rTmXWSRPG8c789IyPGKawFYH2wpf0FRwb68mpQiDX4bzys84HJS6P53eRLzVOx3QL/+bKXTw/l9zr4EtifQ+gJuws8n1p3poNia01FSy1kO3iD8z05ur3gj92w0doBHDMYQhUsvTFlEVpl8C1l9z7gkDPXClchEf9pQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xVZpSPxx8zWDDLdBqxZ/MaGYOQXBfocjANCcUcQReHa/G6AH6R1QsqVoQ/kUbtjOQ3qIgthTrKde/EUrJ81c4ASwpiwMMNi7QwP4mWAIkNugFkVShpKtgtngbD3i/misXcYdp079XSh7OjsZmYqxqM/pQAESUCCuYgNk1XafC4RtEH+VmSP1mII7eba8yxpRHHGDA7oBDJv2rM4DTgVXOp+2thCS+0+jpF3lI2R1UzgRIdLLcZenu3X7l3OASiW7SkISQM4VbNYk5E2vHcWOzPTb9y5zuSQ6vRiNmbmUtRuDNaV8klB3wzwB6Gm51g57xRRJGmcWAsaRs6O+jcPwOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PI/gcpSQKtFzdzPCfIIeov4K0rz1nrHrEJI2eQIYTi8=; b=GzJvuq0Ng4I9iYvF6M9kTLBHCT4dBkwdhdG7t4CJfnSZBpCZVhoefWUs/cNpjFgXy1dHUL38OHSuzW6ngEqKmw6UBt4r5NJDL86dd3SmT/0GIGWI2Jgj7MJ9iSzJ79sTfLCYSSZB0dSq/gRWP8rEKR0EVqVZ4mY8WjYvXf1vgrUK/RqPG31KUGYga1O0kGSRIXrc9VrMj8ea6D/MapiObWeUMGGvRMN82iQHgJPi65HM7EyoIAf/PAyGKH9H8yhFoSUZOCFJ8AUkgYm4Lv9PEFambGKL2gkQIjw7SnDuIwQgHAdFWxP1g7ipVn4J63hJsa/F47a78MRWzydC8vL0Rg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from OS7PR01CA0137.jpnprd01.prod.outlook.com (2603:1096:604:25c::6) by SG2PR06MB5261.apcprd06.prod.outlook.com (2603:1096:4:1d8::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:34 +0000 Received: from OSA0EPF000000CC.apcprd02.prod.outlook.com (2603:1096:604:25c:cafe::a9) by OS7PR01CA0137.outlook.office365.com (2603:1096:604:25c::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000CC.mail.protection.outlook.com (10.167.240.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:33 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 115B04115DE3; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 01/12] PCI: cadence: Split PCIe controller header file Date: Fri, 8 Aug 2025 15:29:18 +0800 Message-ID: <20250808072929.4090694-2-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CC:EE_|SG2PR06MB5261:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f8c2cdd-8aa8-4856-d4c7-08ddd64d5226 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?PCbngRztRRBhhkdJbGgpv5NnCKVUif7LJVW4rqkU1nofh6P/zb6GLhFpGggX?= =?us-ascii?Q?fcBWFVCWydYcqiFHGH8AtFv9eM+vLyOVm34yA4H9xx74SHKFkO6r22I/kij0?= =?us-ascii?Q?sbXlWn68Usc2HX0hEepDH1OXbGDn/bEvAja4VSmWjv0tsQzdsp4gcXX0qJJj?= =?us-ascii?Q?O+AzdaJ4S/a9nUm+B1OhGjCF2NvaPDKjt+wq6tgDMJh3kDYbhJP31GdPhs7C?= =?us-ascii?Q?4iMYbEMtxJPt2IvHz6oJeFe0DYbfnvOb4Sm+yuaJM4/alwhiTnQU4Bh6jAYV?= =?us-ascii?Q?6NdSoLHToHpJAUpqu31/u22kAz48jataTrUDv3m+C7Bx5a52fX+r1/yxtJ/m?= =?us-ascii?Q?CalvXHQBQLvfbqfQA7ZFTn6dK38nioidRHWIveJB8zQwrNGsvmBmRt59QAJT?= =?us-ascii?Q?to9TqCEExhdvXcbAusxI15nhnslofqtZ6nDoT/iBG3d5q62+Rd2sTqV5WlTO?= =?us-ascii?Q?CJROOuv//RuGupkegOvCz0Kaqq/Rdb/qTa8vrkbhKWS/+EFlNqLXg4OPSN7R?= =?us-ascii?Q?be4OErFfxFii9foIbPdR5c5+p5hocRI5Xkx/qK5WAyb3KsvVduwjgasswN+P?= =?us-ascii?Q?pts/5kjiqaIXcKc8nSQqtGkSxjpTu9F1Wkgxup6lK8EH5oeLBMFaEzB4aCQA?= =?us-ascii?Q?uQ7vgqpSEZ7C5zhujY4TI98DVcMMVn1FazpPmwucR+vC49p6UcmCrI2uyXia?= =?us-ascii?Q?ARQQmb1mdE2JThrmz9kPokYGrTChmDxuOC1GPs2E5CPLVOxTqkUFISF6TqTe?= =?us-ascii?Q?K9jcvNlG3k4AfcYH+YUdfzB8aSC8bvddN5It8TYP84bZCJuuyLxt0MdFMqkH?= =?us-ascii?Q?1QFe6NLg0uHzQ5B256r2G516rYh4gSEcD9DkIaikC/ubmgLAlc3XDAHt1E/u?= =?us-ascii?Q?zCVe4d/MCg7eAiPs7z4TpAze5uNgNZK1qO1ChIdWcnRI7M87JWKkT3qj7XQd?= =?us-ascii?Q?m5QKOd1SxfV/lbcCFog2Orpo6+JQt5rL1/Ene+vvxSJH1pqu3acFX2tO2WOT?= =?us-ascii?Q?7bun1sjXJz+keMhbQfNz3T/73viW+IvXVMk8xYbWdOqyiZAF7lp9GTzXhSZA?= =?us-ascii?Q?n0+ASs47wJkqUvDg4u36AYkcfUV6xQcKAqZV/eSra0GMSnl+5dxlPL9IDBai?= =?us-ascii?Q?cCCIBOBBzQHrqGO0phO2dS0jk9TZ/Bl4xqIeDH+ugnCuOMiSQxvJxFV0KFNQ?= =?us-ascii?Q?A0df/KPgJd8MfbLU76y9EapNMazbeOWkym6fPo653rdVeBbXNu9LXT50EmBe?= =?us-ascii?Q?ilmU0R7qAFYXiejp8mGn45XPzYDGLaCZ3fMzhEAKNGDFdUJIflO2eEf9fscu?= =?us-ascii?Q?g0c7C/SuvAmdLUvHIrjSG0Wpo8eDli8m4UiI0uqoHxu+vLrggYUIkh0HdAFP?= =?us-ascii?Q?nHSlj94ypp/Lek8o7Btru5vBJKt06cwyxj3p52RNuHs08eAXMY5eX3rKsftQ?= =?us-ascii?Q?uCxUqaMqDST+evoiJ2yqCa/mcg+iqtQW8Wc/DtqiCZywnZGWtBR5Dh8LmhmO?= =?us-ascii?Q?DaoABr4txz5WPqJRITeVEmbTSsCdUB0klZ5w?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:33.3118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f8c2cdd-8aa8-4856-d4c7-08ddd64d5226 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CC.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB5261 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe header file by moving the Legacy(LGA) controller register definitions to a separate header file for support of next generation PCIe controller architecture. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-lga-regs.h | 228 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 226 +---------------- 2 files changed, 229 insertions(+), 225 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h new file mode 100644 index 000000000000..0e88beb77292 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_LGA_REGS_H +#define _PCIE_CADENCE_LGA_REGS_H + +#include + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +/* Local Management Registers */ +#define CDNS_PCIE_LM_BASE 0x00100000 + +/* Vendor ID Register */ +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +/* Root Port Requester ID Register */ +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +#define CDNS_PCIE_LM_RP_RID_(rid) \ + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) + +/* Endpoint Bus and Device Number Register */ +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 + +/* Endpoint Function f BAR b Configuration Registers */ +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 2) << ((bar) * 8)) + +/* PTM Control Register */ +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) + */ +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 +#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 +#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 + +/* Endpoint PF Registers */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* Root Port Registers (PCI configuration space for the root port function= ) */ +#define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 + +/* Address Translation Registers */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + +#define CDNS_PCIE_RP_MAX_IB 0x3 +#define CDNS_PCIE_MAX_OB 32 + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) + +/* Normal/Vendor specific message access: offset inside some outbound regi= on */ +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +#define CDNS_PCIE_MSG_NO_DATA BIT(16) + +#endif /* _PCIE_CADENCE_LGA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 1d81c4bf6c6d..79df86117fde 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,213 +10,7 @@ #include #include #include - -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - -/* - * Local Management Registers - */ -#define CDNS_PCIE_LM_BASE 0x00100000 - -/* Vendor ID Register */ -#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -#define CDNS_PCIE_LM_ID_VENDOR(vid) \ - (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ - (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) - -/* Root Port Requester ID Register */ -#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -#define CDNS_PCIE_LM_RP_RID_(rid) \ - (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) - -/* Endpoint Bus and Device Number Register */ -#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) -#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 - -/* Endpoint Function f BAR b Configuration Registers */ -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ - (GENMASK(4, 0) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ - (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ - (GENMASK(7, 5) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ - (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) - -/* Endpoint Function Configuration Register */ -#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) - -/* Root Complex BAR Configuration Register */ -#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ - (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ - (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ - (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ - (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) - -/* BAR control values applicable to both Endpoint Function and Root Comple= x */ -#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 - -#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ - (((aperture) - 2) << ((bar) * 8)) - -/* PTM Control Register */ -#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) -#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) - -/* - * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) - */ -#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) - -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - -/* - * Endpoint PF Registers - */ -#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) - -/* - * Root Port Registers (PCI configuration space for the root port function) - */ -#define CDNS_PCIE_RP_BASE 0x00200000 -#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 - -/* - * Address Translation Registers - */ -#define CDNS_PCIE_AT_BASE 0x00400000 - -/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ - (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ - (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) - -/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) - -/* Region r Outbound PCIe Descriptor Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ - (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd -/* Bit 23 MUST be set in RC mode. */ -#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ - (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) - -/* Region r Outbound PCIe Descriptor Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ - (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ - ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) - -/* Region r AXI Region Base Address Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) - -/* Region r AXI Region Base Address Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) - -/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ - (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ - (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) - -/* AXI link down register */ -#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) - -/* LTSSM Capabilities register */ -#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x005= 4) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ - (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ - CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) +#include "pcie-cadence-lga-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -225,29 +19,11 @@ enum cdns_pcie_rp_bar { RP_NO_BAR }; =20 -#define CDNS_PCIE_RP_MAX_IB 0x3 -#define CDNS_PCIE_MAX_OB 32 - struct cdns_pcie_rp_ib_bar { u64 size; bool free; }; =20 -/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ -#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ - (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) -#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ - (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) - -/* Normal/Vendor specific message access: offset inside some outbound regi= on */ -#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) -#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ - (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) -#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) -#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ - (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) -#define CDNS_PCIE_MSG_DATA BIT(16) - struct cdns_pcie; =20 struct cdns_pcie_ops { --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022135.outbound.protection.outlook.com [40.107.75.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D03A723ABB3; Fri, 8 Aug 2025 07:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.75.135 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; cv=fail; b=KiFI9df5hOQi7ORNRYjXlut0L7PX1v1isvO4031HBScRUeqYoMX2nze78QnCkqwCbkQrbGN9fUYjbpZpfqh4akHWm+zBCrgXJbYnBeOUko106urwlIwnwHEdmVa0YJfZN8XzsGGbTvCH2oRWUBvpWd9HZfruUXIcSxTbfRjJm5M= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; c=relaxed/simple; bh=AfBhRDhH3OUOoYa+fX3Gy5cSvwlmm0/ztPrDnPce7HA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sQGy/FRghXJPNcIGrnJjZJGWUTmlpWoanq/Y01damcB+QkBjMiERDg+kL2iO2+wuwWe7hswSF3H6CGBlk3575RT4BVSclqzCykJUi8clyt85qVFF+igY+X0Aedk87EhVby6ZYN6wCG/CSd1CQEGWsj4OeVk066/sMyIa0iR8MKg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.75.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TOP14eUGCWG/2n3IRaPasQCKeAem60BiO1SZbGrpVNVNvu517wrhwYIr7BfQaEawBHzGpfXJ931uFGKbodaq3qmgva3FBH0/4m1316IxVJLIRmU0q0rU1TLpwcSwMrs5QznkFZM2ii1/wExA6buHpY2xtNtjpC0tXc95wu5zB/EpKK2jmWEyd/B2xgx4aMHAkXPBtgiuZaDcxbFZeBtNAOEnBkwOb+z0/7eHmisnFDbBmUU7QuElgdL3oHCtsfYKnrApe/Tjp67zwLCulYAWdSNsOYKLUnZBwHDbY+rqMKaHNzh/uUzjZPz463kuzX4wHm8F4n4sfi88fx+wMr0JEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jitA6Da6DdhOoT7YPgw0hk/3aLBZWa4inW8aWj9rbtE=; b=F9VQNHkeXKvh/rZRzS56nM64HKyQ1amQAyiD9RAJiQ4h5q5F2mf5y5DaRAb0h/anSh7W0K/9YTlbILdusAIlfJI60PMUHU0ECv/8SvytjARk+IYi9iqA4jKGAH5I0QIjYGQ7xf+rCk/aWm0X6FhGlix3Ustd4R0TxFdfWT6Qp0CuNrn3wM2SjuFNXe/cSdz4uDJaHSQgp3HzgV7d5hDE2Wp+Pk1YEVGejQgQs7A3e0X06xzfMjGPcPiw9MQgT+eZhaypwp2ikIVWBIxXmy7ZHYewROp/2QyRvdjvjJWq76cl0SK2cbv7c1CwkU2bnkamZbg08J52f27uUhEIzjN91g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SG2PR02CA0038.apcprd02.prod.outlook.com (2603:1096:3:18::26) by TYZPR06MB5906.apcprd06.prod.outlook.com (2603:1096:400:333::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.15; Fri, 8 Aug 2025 07:29:34 +0000 Received: from SG2PEPF000B66CA.apcprd03.prod.outlook.com (2603:1096:3:18:cafe::bc) by SG2PR02CA0038.outlook.office365.com (2603:1096:3:18::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.18 via Frontend Transport; Fri, 8 Aug 2025 07:29:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CA.mail.protection.outlook.com (10.167.240.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:33 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 21DF04115DE4; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 02/12] PCI: cadence: Add register definitions for HPA(High Perf Architecture) Date: Fri, 8 Aug 2025 15:29:19 +0800 Message-ID: <20250808072929.4090694-3-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|TYZPR06MB5906:EE_ X-MS-Office365-Filtering-Correlation-Id: a470966b-c387-456d-c207-08ddd64d5226 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fRbSoylWNeNkre/BcBlvEqNLydcDKC9IdcIRM+//CWsqbd8+q6khUOvlGBep?= =?us-ascii?Q?DQFe8JnnHEuWje+f8NY/iGJR4tPYAkbMNG0V+WbTgFYmv2GsUKxESfCbA+fu?= =?us-ascii?Q?v+tCkJgFgl8hK8gUyrviXaA+Og6sV7ojZb1I27OWylcUq2OGCYR7caaqo+g6?= =?us-ascii?Q?3wh6HvE8607NxyvAeX6+lvAEwWfxMn8tlhW6zb6sGvGrNld/LlwiQNTIklX4?= =?us-ascii?Q?4FUIn09kCWCC4HAZ7F2+tliH8jrZuQoQrGGE1tLXtURWUc1GeQrNQdVbx9aI?= =?us-ascii?Q?seK//8jYf1rd7sLgLE4vsq55loniTC/swZ94/aoHiAkajlxVdUSUbEZA3Ral?= =?us-ascii?Q?MHz5LOdfyz8Zsm3w8w1A8arbaosNhsfEJU7QkF6BI+vwb7FK+EQiIdZR6wUC?= =?us-ascii?Q?US0nYeGzNE5HCEKNMxak6zS+ISPB1Pyf11Qfa8aVzOWyhMzk6GUPVsDEn36S?= =?us-ascii?Q?siJ+492dpcyfEJ8u8my6/kNX2rfJz5uepPGLLmsM05fbOON3rxeoV9HD6IIr?= =?us-ascii?Q?bkeem1E7Sx0QdhyavglbXmUXph/pc1cSfhhbjTaho24MtVpP1KsQrEbAr8r6?= =?us-ascii?Q?rtRmbFOIeoLWykNJeYojzJCLXd84URFOtpJCwi5TDSgcgPBANnQCNWnFVWQj?= =?us-ascii?Q?9G1Vvdyq05WHA1gjCj3G9PLZM8z0TGT/eeZ4WPmF3PHOE+m3ufnGXVG1pdZI?= =?us-ascii?Q?MBhQHIs6QEBx64k8mQJSIDV7v5PO+XE+hoS54oSX0xzFxtycyXyrWNgXqjx4?= =?us-ascii?Q?4ZvkVaVc7VmP2FJFNS0RPT1T2IMcZIeJ9Ljsvw87JElxWSH+XDEub71xfk06?= =?us-ascii?Q?DgZVRZ1N2dUfnaimta8KMJP1bnszzbyqZfBLT9ILvY45cDqmnwJ2FkVv2912?= =?us-ascii?Q?Ek7sfxgOTu8ANMKf5U+UP0oDwDKskIVNJvqAQTcFLiy0E0mblD4VCB18xVIj?= =?us-ascii?Q?VJUl3d7Zay+VwXqPI7FCSRerEVac4N9gCkuM540gpBGe17+l/68PsS3H67s2?= =?us-ascii?Q?IS7d5OGA/8HVsHvsFGwl040XC0WPakbpBQOxQlMZaVAUUyaoQPiv0kzwQbw6?= =?us-ascii?Q?mR4O8GZ4phwKc3aHH3RH0MtuvXXAV3Xop1HplSv2D48Ugh+cXNKxPyZv0iO4?= =?us-ascii?Q?NB+MQgozw9kGR8IRBQrDRUhaB8ItljqGI4wBQPXBaPcX+SC8l2T13tui7dOY?= =?us-ascii?Q?rNikcALPaERzzVUgRYP7eTXHNKOOUkldS1IGv/k0wZDtFB8Z29JwwzCEL8zn?= =?us-ascii?Q?ZkvvGuBdxFGp6mk7NVRDwKNo8SHQ/7pwCTs2ehqBlFVuAdc2emrHbT6LiU6o?= =?us-ascii?Q?Du4XKvZ9jyoJOBXvcKj774Um9MTP45CGIrNtQVpD/zWFKq/j9VkWYhenNYEl?= =?us-ascii?Q?hTeETlgwJgQ4/1P/fF33is5JUG+Vw9k8cxulcOpYGIRtMDLFWCs1rvKaCTY2?= =?us-ascii?Q?mWDe7E5nLVrOB1b9y2a4m7DmXc6r8So1MWT+w+7NW27nzEuIkg7467gd+w7V?= =?us-ascii?Q?MpFTJjFHM4ogXuhItOd3C/wpB0qk0G6kCdUH?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:33.3680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a470966b-c387-456d-c207-08ddd64d5226 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB5906 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add the register offsets and register definitions for HPA(High Performance architecture) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-hpa-regs.h | 212 ++++++++++++++++++ .../controller/cadence/pcie-cadence-plat.c | 4 - drivers/pci/controller/cadence/pcie-cadence.h | 121 ++++++++-- 3 files changed, 320 insertions(+), 17 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-hpa-regs.h new file mode 100644 index 000000000000..016144e2df81 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HPA_REGS_H +#define _PCIE_CADENCE_HPA_REGS_H + +#include +#include +#include +#include +#include + +/* + * HPA (High Performance Architecture) PCIe controller register + */ +#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x01020000 +/* + * Address Translation Registers(HPA) + */ +#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 +#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 +/* + * Root port register base address + */ +#define CDNS_PCIE_HPA_RP_BASE 0x0 + +#define CDNS_PCIE_HPA_LM_ID 0x1420 + +/* + * Endpoint Function BARs(HPA) Configuration Registers + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ + (GENMASK(9, 4) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTU= RE_MASK(b))) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ + (GENMASK(3, 0) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)= )) + +/* + * Endpoint Function Configuration Register + */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 + +/* + * Root Complex BAR Configuration Register + */ +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) + +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD + +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 7) << ((bar) * 10)) + +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Root Port Registers PCI config space(HPA) for root port function + */ +#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 + +/* + * Region r Outbound AXI to PCIe Address Translation Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) + +/* + * Region r Outbound AXI to PCIe Address Translation Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) = & 0x1F) * 0x0080) + +/* + * Region r Outbound PCIe Descriptor Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) + +/* + * Region r Outbound PCIe Descriptor Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) = * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) + +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) + +/* + * Region r AXI Region Base Address Register 0 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1)) + +/* + * Region r AXI Region Base Address Register 1 + */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F)= * 0x0080) + +/* + * Root Port BAR Inbound PCIe to AXI Address Translation Register + */ +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x000= 8)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) = * 0x0008)) + +/* + * AXI link down register + */ +#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 + +/* + * Physical Layer Configuration Register 0 + * This register contains the parameters required for functional setup + * of Physical Layer. + */ +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ + FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) + +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 + +#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 +#define CDNS_PCIE_HPA_MAX_OB 15 + +/* + * Endpoint Function BAR Inbound PCIe to AXI Address Translation Register(= HPA) + */ +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0040) + = ((bar) * 0x0008)) +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x00= 40) + ((bar) * 0x0008)) + +#endif /* _PCIE_CADENCE_HPA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index 0456845dabb9..e09f23427313 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -22,10 +22,6 @@ struct cdns_plat_pcie { struct cdns_pcie *pcie; }; =20 -struct cdns_plat_pcie_of_data { - bool is_rc; -}; - static const struct of_device_id cdns_plat_pcie_of_match[]; =20 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 79df86117fde..8048bef215d0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,7 +10,9 @@ #include #include #include +#include #include "pcie-cadence-lga-regs.h" +#include "pcie-cadence-hpa-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -25,6 +27,20 @@ struct cdns_pcie_rp_ib_bar { }; =20 struct cdns_pcie; +struct cdns_pcie_rc; + +enum cdns_pcie_reg_bank { + REG_BANK_RP, + REG_BANK_IP_REG, + REG_BANK_IP_CFG_CTRL_REG, + REG_BANK_AXI_MASTER_COMMON, + REG_BANK_AXI_MASTER, + REG_BANK_AXI_SLAVE, + REG_BANK_AXI_HLS, + REG_BANK_AXI_RAS, + REG_BANK_AXI_DTI, + REG_BANKS_MAX, +}; =20 struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); @@ -33,6 +49,30 @@ struct cdns_pcie_ops { u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 +/** + * struct cdns_plat_pcie_of_data - Register bank offset for a platform + * @is_rc: controller is a RC + * @ip_reg_bank_offset: ip register bank start offset + * @ip_cfg_ctrl_reg_offset: ip config control register start offset + * @axi_mstr_common_offset: AXI master common register start offset + * @axi_slave_offset: AXI slave start offset + * @axi_master_offset: AXI master start offset + * @axi_hls_offset: AXI HLS offset start + * @axi_ras_offset: AXI RAS offset + * @axi_dti_offset: AXI DTI offset + */ +struct cdns_plat_pcie_of_data { + u32 is_rc:1; + u32 ip_reg_bank_offset; + u32 ip_cfg_ctrl_reg_offset; + u32 axi_mstr_common_offset; + u32 axi_slave_offset; + u32 axi_master_offset; + u32 axi_hls_offset; + u32 axi_ras_offset; + u32 axi_dti_offset; +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -44,16 +84,18 @@ struct cdns_pcie_ops { * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC */ struct cdns_pcie { - void __iomem *reg_base; - struct resource *mem_res; - struct device *dev; - bool is_rc; - int phy_count; - struct phy **phy; - struct device_link **link; - const struct cdns_pcie_ops *ops; + void __iomem *reg_base; + struct resource *mem_res; + struct device *dev; + bool is_rc; + int phy_count; + struct phy **phy; + struct device_link **link; + const struct cdns_pcie_ops *ops; + const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; }; =20 /** @@ -131,6 +173,40 @@ struct cdns_pcie_ep { unsigned int quirk_disable_flr:1; }; =20 +static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_p= cie_reg_bank bank) +{ + u32 offset =3D 0x0; + + switch (bank) { + case REG_BANK_IP_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; + break; + case REG_BANK_IP_CFG_CTRL_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; + break; + case REG_BANK_AXI_MASTER_COMMON: + offset =3D pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; + break; + case REG_BANK_AXI_MASTER: + offset =3D pcie->cdns_pcie_reg_offsets->axi_master_offset; + break; + case REG_BANK_AXI_SLAVE: + offset =3D pcie->cdns_pcie_reg_offsets->axi_slave_offset; + break; + case REG_BANK_AXI_HLS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_hls_offset; + break; + case REG_BANK_AXI_RAS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_ras_offset; + break; + case REG_BANK_AXI_DTI: + offset =3D pcie->cdns_pcie_reg_offsets->axi_dti_offset; + break; + default: + break; + }; + return offset; +} =20 /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 v= alue) @@ -143,6 +219,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg, + u32 value) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + return readl(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); @@ -313,19 +410,17 @@ static inline void cdns_pcie_ep_disable(struct cdns_p= cie_ep *ep) #endif =20 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); - void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size); - void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, u64 cpu_addr); - void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); void cdns_pcie_disable_phy(struct cdns_pcie *pcie); -int cdns_pcie_enable_phy(struct cdns_pcie *pcie); -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +int cdns_pcie_enable_phy(struct cdns_pcie *pcie); +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); + extern const struct dev_pm_ops cdns_pcie_pm_ops; =20 #endif /* _PCIE_CADENCE_H */ --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022096.outbound.protection.outlook.com [40.107.75.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9657E23B615; Fri, 8 Aug 2025 07:29:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.75.96 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638184; cv=fail; b=uUGld/I8Jd+KE0j9nHsal3sO/2kKL3S8FHYlzHxl5NPe3Et/1sfQLgxT6AEdBiaSPv1PUOAPnVqZeR8fP4Z+zj/QtGTS16YAdjZRKlT4WHD71NqAZx4g6GiNNn7V7ADegxvnly4HYQlHK9Akj/b3HZl8ejLqjBQfEoqAQrdSpg8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638184; c=relaxed/simple; bh=7rvUFDamz8HgP62nF0S/2Mxt/EC0mf99sR7hVEylujk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EiBOeN9JjMBEvw4kjaRm8zgHbq8eB/SMTOzqwtjzo6StBOMz6ZbZn9eJxYrwOCohDmd2h3WGh5uY8ByBvzk/hJoNbLOAOgNVq7Ygh/e3gTWZBzKmIV/988Bmuld2KLsx4kikIPN348P/Ly1tS9c+i2SYuCcuRr0+Ky8JIrhi93A= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.75.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=elRbPVES+v4BpYG9h7Puj8QenI/5TchwV5ElRCa4VAqFQhV31cln+Zh5xAnBnRVmZz8OrxTpoRQfPru8XpbaTpl8aYFYTnPaZMf2f1bzXvAMFDXFXMf+0GVvppgdMqn0WCR4jQCkfSe3RieuDWMBtzEfgRivBebm50PFZpLGRRhbKS1u1+6Z3F5ZgNQLN7mCrfQah+t0q6EmjKNfMJ1jR7E5mMh2CG5m+ksRPQgY1clfNGwQKp9rsMoLEO029w5PHnvevzQxkMmLvzMg+7+rSW2qicKY0J4opCPyuzUV53TrNtY6kfspj4jQd1yl4IkVrEdKdXdZQaiRlBxSYOy65g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=naL0piV24y6eY+H9xJzknvSkcY0cLCnsx9zgk5U+zrY=; b=ebv1kPfEB4rcWx9IIQ3e636f4rX3FVgqCUj345ilLlBS9TmBfzz6f1fkXWJZWtysOu6LTNKRBGUftBlhotX07/gfLmi5JghWX7TWT+72NxyLz0o0kuZqS5LGrmR2osw5zUFWbCr+FTkG3UNdwq1UO/jkHBK2rcsh863UeBebr9Dxj1p4PkENoBBNcXn676Y3PnGrqtS75CpQjkI1a9X/ybUwi/BDMELfl5At9eC4cykQivb4wN+XTtHsb4pXPW7NuX3URq3Qt8P7KKru+gQuxRIggtzCJGMs2njriBeOfUFx1iIH9Ok17dEcb2cmzzczM5Y2UnQDxKTOUCew5tUCcw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TYCP286CA0367.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:79::14) by PUZPR06MB5539.apcprd06.prod.outlook.com (2603:1096:301:e9::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:36 +0000 Received: from TY2PEPF0000AB8A.apcprd03.prod.outlook.com (2603:1096:405:79:cafe::e) by TYCP286CA0367.outlook.office365.com (2603:1096:405:79::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB8A.mail.protection.outlook.com (10.167.253.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:34 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 286694126FFD; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 03/12] PCI: cadence: Split PCIe EP support into common and specific functions Date: Fri, 8 Aug 2025 15:29:20 +0800 Message-ID: <20250808072929.4090694-4-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|PUZPR06MB5539:EE_ X-MS-Office365-Filtering-Correlation-Id: da94f69f-5bea-4665-e89d-08ddd64d52cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6XO7O8vKBho15g95WZ7mdffWV07hFgOlHKxsheCp96hJ4xp9tf5dwAhwZsen?= =?us-ascii?Q?4u7SGz3qMnoEbVfgbHk8Lbdm+J6PTT1DL63MVD71z+bZ24TTBkv+OnJHXKUU?= =?us-ascii?Q?Rlq4p6HTSFkGye8esjqqBbutLuZfMXAsO9JymKm/7tdms0Ttvv/YEVda0Eef?= =?us-ascii?Q?NmrHCgVocki4+hLIC+dTc4/KSTJJIp4Ae7aVZowGWPoTQWHBGJXnsJQHWHAx?= =?us-ascii?Q?7np9EVGKHtRZ6/6zJ7jv3bkhHoJ/bfUTho+gJRQixJyC90N5LhaLcoDF8/KL?= =?us-ascii?Q?Oxg2Z3ATMppTHs/Z1Bsb6rFnD9ktJPpSyU9TjjrH3Au29vApT97brHxvEU+R?= =?us-ascii?Q?gFpuXg4ZmvtNSve6aUHUm1KQS2IVbi6w7tz7i1QVN08HxnydWf9v2czifvHp?= =?us-ascii?Q?JDa+rnzP09+lpRY6Ru2gac6u6om0D17NEcwg8WPzxP7I7FsgJu9hOPr9Ur+x?= =?us-ascii?Q?VzvHNXo1rlUGb+tfgK3pcV7t1iUOGhQ4D5WC4Mr7snwvOwOc+O4C766TbyKz?= =?us-ascii?Q?GvZNGHTdf1qv9xK8AITxWOsf2mDuJt2jLh3kqNDKNsx6fj8clwfaYSkcoJ+0?= =?us-ascii?Q?niNaTO6aonEBMR2PDm9dUVVsZbjN0ubb/Q/9f3wWEEJdYbKLEfQ31Q3kZZR1?= =?us-ascii?Q?KHep9Ce7GPJfQos8KppMHnVNUB6EUHUUljJ2Hpc1dUTRyUX6knrKq+3vjwVr?= =?us-ascii?Q?mSjAWp5B37AW3xHPk+Z/b8iGqxiGYZkqHYrrE/8dC6RfNolwEF+uQhR7G0WH?= =?us-ascii?Q?cP7kvkw3v2LNWpHjGJpaR1OJD1nz3R6Vd34Vo43NPvH3CMX+8lKen9eTEZtL?= =?us-ascii?Q?TRMjgFTc7tGJpEQHk1NXBrfhu/U7Uz1ajSesPAthNN3GSMA5swRbHtsqfB8f?= =?us-ascii?Q?n20/WVBiX1OEib9BjNaUsv7eY6+ep8URsgRbKLHD73JyConY/eeMgGFVX1HK?= =?us-ascii?Q?OWtN5wRjLEVfWOaVxNNIFVPUUXHMhdqxVnkOu8RldyNdJPEOI4+MOAFHT1I3?= =?us-ascii?Q?oQICZUSEvGb8VPYNvA8X7549yo8JyokisUO6AFB0U6gFPdqkOdwALi2tczHF?= =?us-ascii?Q?8hJKvCBLIH3wZP4Ar2Mg2rrC1Zap+2VECtR+FQUgEwQKYgDPXN6h3ZJV1kho?= =?us-ascii?Q?unPEg9BiZqhfrqht8PgeGGwnPLX4JO/MIMPP9jou7LKax/TaH/LgjYQL3H4z?= =?us-ascii?Q?nGJJmjUneYGMOGfUnGJeTdAJx9ULAGi1jGJjoAGn/iZdp1vNps3YQNMVFHCy?= =?us-ascii?Q?ctpRHA/zwqnGf3WTT4gezBBYgNFVx+xknJQD8ORlNupFs3CdC3a1n+3TOJNT?= =?us-ascii?Q?4j5jw8VfscK1LSPdAVhRvmzKQ9Pd6Tov1GgkZ/E75S47QkvuTrHS06NvNSNf?= =?us-ascii?Q?uGY0a79VmTHnFLrA9YbOwqCfOc+4/eYa2hL3CLabrmsCsRDzw35fhhQDL/vA?= =?us-ascii?Q?qnklHsPN++SGYRluc4ZS2HStQMOuD/kiZKHgRL7cKnc2UXEg+QPR1kAsO14C?= =?us-ascii?Q?Rjl/HCAVu9/o0KsFD5Mi020xK64KnoHbXSQd?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:34.2393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da94f69f-5bea-4665-e89d-08ddd64d52cc X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5539 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller EP functionality into common library functions and functions for legacy PCIe EP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-ep-common.c | 240 +++++++++++++++++ .../cadence/pcie-cadence-ep-common.h | 36 +++ .../pci/controller/cadence/pcie-cadence-ep.c | 243 +----------------- 4 files changed, 283 insertions(+), 238 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 9bac5fb2f13d..80c1c4be7e80 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.c b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.c new file mode 100644 index 000000000000..cf5be3b3c981 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver common +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + u32 first_vf_offset, stride; + + if (vfn =3D=3D 0) + return fn; + + first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); + stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); + fn =3D fn + first_vf_offset + ((vfn - 1) * stride); + + return fn; +} + +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u32 reg; + + if (vfn > 1) { + dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); + return -EINVAL; + } else if (vfn =3D=3D 1) { + reg =3D cap + PCI_SRIOV_VF_DID; + cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); + return 0; + } + + cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, + hdr->subclass_code | hdr->baseclass_code << 8); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, + hdr->cache_line_size); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); + + /* + * Vendor ID can only be modified from function 0, all other functions + * use the same vendor ID as function 0. + */ + if (fn =3D=3D 0) { + /* Update the vendor IDs. */ + u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | + CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); + + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + return 0; +} + +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* + * Set the Multiple Message Capable bitfield into the Message Control + * register. + */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); + flags |=3D PCI_MSI_FLAGS_64BIT; + flags &=3D ~PCI_MSI_FLAGS_MASKBIT; + cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); + + return 0; +} + +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Validate that the MSI feature is actually enabled. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* + * Get the Multiple Message Enable bitfield from the Message Control + * register. + */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + + return mme; +} + +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &=3D PCI_MSIX_FLAGS_QSIZE; + + return val; +} + +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &=3D ~PCI_MSIX_FLAGS_QSIZE; + val |=3D interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSI-X BAR and offset */ + reg =3D cap + PCI_MSIX_TABLE; + val =3D offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSI-X BAR */ + reg =3D cap + PCI_MSIX_PBA; + val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} + +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u64 pci_addr, pci_addr_mask =3D 0xff; + u16 flags, mme, data, data_mask; + u8 msi_count; + int ret; + int i; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + for (i =3D 0; i < interrupt_num; i++) { + ret =3D epc->ops->map_addr(epc, fn, vfn, addr, + pci_addr & ~pci_addr_mask, + entry_size); + if (ret) + return ret; + addr =3D addr + entry_size; + } + + *msi_data =3D data; + *msi_addr_offset =3D pci_addr & pci_addr_mask; + + return 0; +} + +static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 65536, +}; + +static const struct pci_epc_features cdns_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 256, +}; + +const struct pci_epc_features* +cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + if (!vfunc_no) + return &cdns_pcie_epc_features; + + return &cdns_pcie_epc_vf_features; +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h new file mode 100644 index 000000000000..a91084bdedd5 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_EP_COMMON_H_ +#define _PCIE_CADENCE_EP_COMMON_H_ + +#include +#include +#include +#include +#include "../../pci.h" + +#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn); +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr); +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc); +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn); +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset); +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset); +const struct pci_epc_features *cdns_pcie_ep_get_features(struct pci_epc *e= pc, + u8 func_no, + u8 vfunc_no); + +#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 77c5a19b2ab1..83204efaea3f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -13,68 +13,7 @@ #include =20 #include "pcie-cadence.h" -#include "../../pci.h" - -#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 - -static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) -{ - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - u32 first_vf_offset, stride; - - if (vfn =3D=3D 0) - return fn; - - first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); - stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); - fn =3D fn + first_vf_offset + ((vfn - 1) * stride); - - return fn; -} - -static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, - struct pci_epf_header *hdr) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u32 reg; - - if (vfn > 1) { - dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); - return -EINVAL; - } else if (vfn =3D=3D 1) { - reg =3D cap + PCI_SRIOV_VF_DID; - cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); - return 0; - } - - cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, - hdr->subclass_code | hdr->baseclass_code << 8); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, - hdr->cache_line_size); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); - - /* - * Vendor ID can only be modified from function 0, all other functions - * use the same vendor ID as function 0. - */ - if (fn =3D=3D 0) { - /* Update the vendor IDs. */ - u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | - CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); - - cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); - } - - return 0; -} +#include "pcie-cadence-ep-common.h" =20 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_bar *epf_bar) @@ -222,100 +161,6 @@ static void cdns_pcie_ep_unmap_addr(struct pci_epc *e= pc, u8 fn, u8 vfn, clear_bit(r, &ep->ob_region_map); } =20 -static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_= irqs) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* - * Set the Multiple Message Capable bitfield into the Message Control - * register. - */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); - flags |=3D PCI_MSI_FLAGS_64BIT; - flags &=3D ~PCI_MSI_FLAGS_MASKBIT; - cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); - - return 0; -} - -static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags, mme; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Validate that the MSI feature is actually enabled. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* - * Get the Multiple Message Enable bitfield from the Message Control - * register. - */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - - return 1 << mme; -} - -static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc= _no) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); - if (!(val & PCI_MSIX_FLAGS_ENABLE)) - return -EINVAL; - - val &=3D PCI_MSIX_FLAGS_QSIZE; - - return val + 1; -} - -static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, - u16 nr_irqs, enum pci_barno bir, u32 offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); - val &=3D ~PCI_MSIX_FLAGS_QSIZE; - val |=3D nr_irqs - 1; /* encoded as N-1 */ - cdns_pcie_ep_fn_writew(pcie, fn, reg, val); - - /* Set MSI-X BAR and offset */ - reg =3D cap + PCI_MSIX_TABLE; - val =3D offset | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - /* Set PBA BAR and offset. BAR must match MSI-X BAR */ - reg =3D cap + PCI_MSIX_PBA; - val =3D (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - return 0; -} - static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 in= tx, bool is_asserted) { @@ -426,59 +271,6 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_= ep *ep, u8 fn, u8 vfn, return 0; } =20 -static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, - phys_addr_t addr, u8 interrupt_num, - u32 entry_size, u32 *msi_data, - u32 *msi_addr_offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u64 pci_addr, pci_addr_mask =3D 0xff; - u16 flags, mme, data, data_mask; - u8 msi_count; - int ret; - int i; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Check whether the MSI feature has been enabled by the PCI host. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* Get the number of enabled MSIs */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - msi_count =3D 1 << mme; - if (!interrupt_num || interrupt_num > msi_count) - return -EINVAL; - - /* Compute the data value to be written. */ - data_mask =3D msi_count - 1; - data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); - data =3D data & ~data_mask; - - /* Get the PCI address where to write the data into. */ - pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); - pci_addr <<=3D 32; - pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); - pci_addr &=3D GENMASK_ULL(63, 2); - - for (i =3D 0; i < interrupt_num; i++) { - ret =3D cdns_pcie_ep_map_addr(epc, fn, vfn, addr, - pci_addr & ~pci_addr_mask, - entry_size); - if (ret) - return ret; - addr =3D addr + entry_size; - } - - *msi_data =3D data; - *msi_addr_offset =3D pci_addr & pci_addr_mask; - - return 0; -} - static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { @@ -589,12 +381,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; =20 value =3D cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); value &=3D ~PCI_EXP_DEVCAP_FLR; cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); } } =20 @@ -607,29 +399,6 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) return 0; } =20 -static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 65536, -}; - -static const struct pci_epc_features cdns_pcie_epc_features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D true, - .align =3D 256, -}; - -static const struct pci_epc_features* -cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) -{ - if (!vfunc_no) - return &cdns_pcie_epc_features; - - return &cdns_pcie_epc_vf_features; -} - static const struct pci_epc_ops cdns_pcie_epc_ops =3D { .write_header =3D cdns_pcie_ep_write_header, .set_bar =3D cdns_pcie_ep_set_bar, @@ -759,7 +528,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) =20 return 0; =20 - free_epc_mem: +free_epc_mem: pci_epc_mem_exit(epc); =20 return ret; --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023135.outbound.protection.outlook.com [52.101.127.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DD5623AB8A; Fri, 8 Aug 2025 07:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.127.135 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; cv=fail; b=WY5dHg6sGn+DzYV9ZAnA0FfoyN6hl9S47Ef5jMKhnef9P189Cz4dkyntdNppGrQle1UWfDa8eOLisGMj8vGxbCmdvsk41r+uhF07SGArbXS4sMYgutNB136o39RLJNivfoQ2q39zRz7/maPSv2gWvjyGnQW1V5lFGsLPtuA7BxI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; c=relaxed/simple; bh=X7Lpiv5jtNGgVxNkHhKfRHwVdrK/5rII97ijF9qMoSo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g/dHdlF6KPuWUbbHuHuMraTbejhndMyvFp+eRPRJJztYA7fF7tYVWrTR541ERFK7RigSQ7bnIvTc57t3cHVkEYy3EJczgpOL/bMQIqKOvC7tgeAwnO1PgJ2zeSMS6a7WdF8Tm52blwAKyiyQyrKARE5dq1WYcYJu1UFg2ukPUQQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.127.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=B0k+1F9A+6/QuuG2Q9UKhWFz1lsUoRfqvNHJFoAOL/djGalBsm4/Yp1eAiTJ+5BclkHUcBSL4D5eNVJ8pUZ425DJkVeMpKTSC8n7aX0O16uYHAi3tFIEJQXTFb9+z1JZrjcN8QBmjOiHRIvFBwY4vWC/1bnnZqz/ZkgmyNOoMwpLCpIX/00g4jrR6+yUOCVZaRYq84vTzEcKoBihQteYya19ZHmdT45QfECaiDMNp71Hv3lQ6lug9UIFyXsYfyS95hxSCxeiCUkryl72iswIFKcng/tE3xggOt3zT90S2Cqf4SMGXRTdwjkrhFlt7gQKhA1KrIA6F0MG+bIlZyCJnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/srJqq/+EOYVSwVA3sS9gpmnbAUWhYUbj86GblsBUGc=; b=y/q7Gx4f9L2fN5zdIlu+l62pfogJ3OJ590o1rpx4mkIU7l99C0yfTU6fJt9+dIjb6XUeX9u9r3N3IsnPUCVSliWJfrFH3FCmYxlJzisqkfxjdLbvFuc8IR5MSC4edbE8rJg/XqbRVhCQ1T6jomeeHZvRPgz7suPEq4DTjLZzgWUvc2S/LdbzKJCBllXdiCpa097zRebBiYMMHpR4xT3K1SB0xWTfDfGb16HizHPlRa3/bG7/C8Bd5/2CP5ykEyA8EljXwZohLms4MkXdKy3fwFPT4FoaoikgcZYYrXWnjeojWc2+57DIWH0YUeVY+GVdoOp2aMjtQGiqnoT/ENvcQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SI2PR02CA0007.apcprd02.prod.outlook.com (2603:1096:4:194::23) by SEYPR06MB6430.apcprd06.prod.outlook.com (2603:1096:101:16a::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:34 +0000 Received: from SG2PEPF000B66C9.apcprd03.prod.outlook.com (2603:1096:4:194:cafe::b4) by SI2PR02CA0007.outlook.office365.com (2603:1096:4:194::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.14 via Frontend Transport; Fri, 8 Aug 2025 07:29:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66C9.mail.protection.outlook.com (10.167.240.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:32 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 396C84143A8D; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 04/12] PCI: cadence: Split PCIe RP support into common and specific functions Date: Fri, 8 Aug 2025 15:29:21 +0800 Message-ID: <20250808072929.4090694-5-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66C9:EE_|SEYPR06MB6430:EE_ X-MS-Office365-Filtering-Correlation-Id: 91c3a0e9-5c67-48d2-2697-08ddd64d51f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700013|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DFj5nIJXmrcsbU2a0PHJRBCH1DOAOMOg2jvFltxZG5iUmkK/etcpkq3ENrFK?= =?us-ascii?Q?6pja8BCcIDg6nkKNFCkaJ1SpeJ6jNqSC0tu7aH73ne3tvPIXz9mwFfHYAlL+?= =?us-ascii?Q?6w/3WnawN+fZGWPvRe3VBV1RGnMaLgP6tY7gJcuxfgGoSqf2jbWG+rgT/c1h?= =?us-ascii?Q?uGvsdyGjiT2QlsKBd51DUmKA7H4Z3nZ0JvHN9TzKddtMAhH/7m9WEjUoejR9?= =?us-ascii?Q?LWvacSmG+TECEp8Rky8iqTm69GQ+LZV596SAsZB6fytsibSEiQRZ0ivI6N9r?= =?us-ascii?Q?yxq71f1FJrBe1N3P5XvNBCr7CbYZCEXIto6rdjdSY/OauTSrW/XVY/wwaA3J?= =?us-ascii?Q?uV0sQN/T/MB6mYxvHlaiDXtfWvDLw9qcxUs1gD8DIIlVBLRhCh3AWjBtYNOx?= =?us-ascii?Q?8OpPJf99sC59rRsfoAmtCjdnQkOvkJKgZSd7rOI0ooBwkhUokwhNT04xzCLJ?= =?us-ascii?Q?7JGxSDg26fUyT92pHWyPgVMZuJQ5TpZDhzWO+Y3kD8eHcjlj8/jV9a1K+Gnu?= =?us-ascii?Q?yNjAYeqeoPK5QAI/3/tGMxJZ1KQ1x3U9qyMrXtmmYnVTjtOLu2v33dksBpXk?= =?us-ascii?Q?CNgFdKltcIUIlsfjeMSzuAiBum78PjCZqCeEtuVJDGQ4oYtj2o2XcIS9SKjs?= =?us-ascii?Q?0uawO5RKVL3xj6MAcy6x1s+D3XBUPFUDmSTJoaLujmETkHcnwKulcJG2qXjH?= =?us-ascii?Q?O0SWYmnPxL4O02LYeUGL94O3VdK+fhxUrsJkQ+GHzYFrvNHLBtmpRqgm33vI?= =?us-ascii?Q?7ujlUMfnrkRzkjizd5NHiVeYrhKgLiX85J1JYk+uQld3CPLnuvr+pveIdONi?= =?us-ascii?Q?/37GvR4/TnDJcoJ4sujmAaZqIOtTtr07iPOfXvGAqJmj2Ml1Yg6HcOacBwmt?= =?us-ascii?Q?STosEZUq1UNYT8Stg3YNDsYwGXJBPyUWfWNMvNJ0Y1Fb2BRUYumyGk2RlJ1o?= =?us-ascii?Q?XsOK01kc42U3SPvW2S6cLukcz6ayLoKR0K9wD3t2dMDaFXf++nHnwJG6+m9e?= =?us-ascii?Q?8lnymjGWxmmzsO7d6rrIfyCWHdgb/vuGxlgKYEvKXYKZPHa6Hi3z5bwmpxdb?= =?us-ascii?Q?WzDpPO27T0cOl5P4NbKoTgW2qzZqkbb1ApXS+j1MTuaQg7ysYa5lc0GAkCnn?= =?us-ascii?Q?v7L9kjbTs5IZX8nQwL6L8lWNGvsbJqebwuBghqFfBPuqnLe6Vpj3TqM/MmLr?= =?us-ascii?Q?4oehcHsUjKx+Aye1zuYWERQ3EMyX+k1pb97U392TqEVIFeFETZgISCuMGT7d?= =?us-ascii?Q?8quyLH4XwrC2rWZEBdmeQH9wyg0ZvIs5pjcKCHIgac9zRVooadyMaYD+Ugrd?= =?us-ascii?Q?VpYJVkkrgyEWJdh0DRJ7oQE2WpLXZt0uHFITKI7j/24Xlrd87A1H/rse1AO1?= =?us-ascii?Q?0sup1y4LuMlVVM/LK6u88XWklUWH7ZyQGK9elwQ6zMPIgvelZzCDHITWW15p?= =?us-ascii?Q?WLEjgaBwqKuwbAXm894q0u6noPRqRphzjtCF3FLAW4oOtLZcphtfei1JrsRa?= =?us-ascii?Q?l76cQe8mIU+yOO98yaiTZHb914FZHra6saRw?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700013)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:32.9858 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91c3a0e9-5c67-48d2-2697-08ddd64d51f3 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB6430 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe controller RP functionality into common functions and functions for legacy PCIe RP controller. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 8 + drivers/pci/controller/cadence/Makefile | 4 +- .../cadence/pcie-cadence-ep-common.h | 8 +- .../cadence/pcie-cadence-host-common.c | 169 ++++++++++++++++++ .../cadence/pcie-cadence-host-common.h | 25 +++ .../controller/cadence/pcie-cadence-host.c | 156 +--------------- 6 files changed, 210 insertions(+), 160 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .h diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 666e16b6367f..a1caf154888d 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -6,17 +6,25 @@ menu "Cadence-based PCIe controllers" config PCIE_CADENCE tristate =20 +config PCIE_CADENCE_EP_COMMON + bool + +config PCIE_CADENCE_HOST_COMMON + bool + config PCIE_CADENCE_HOST tristate depends on OF select IRQ_DOMAIN select PCIE_CADENCE + select PCIE_CADENCE_HOST_COMMON =20 config PCIE_CADENCE_EP tristate depends on OF depends on PCI_ENDPOINT select PCIE_CADENCE + select PCIE_CADENCE_EP_COMMON =20 config PCIE_CADENCE_PLAT bool diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 80c1c4be7e80..0440ac6aba5d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o +obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h index a91084bdedd5..9cfd0cfa7459 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ // Copyright (c) 2017 Cadence -// Cadence PCIe Endpoint controller driver. +// Cadence PCIe Endpoint controller driver // Author: Manikandan K Pillai =20 -#ifndef _PCIE_CADENCE_EP_COMMON_H_ -#define _PCIE_CADENCE_EP_COMMON_H_ +#ifndef _PCIE_CADENCE_EP_COMMON_H +#define _PCIE_CADENCE_EP_COMMON_H =20 #include #include @@ -33,4 +33,4 @@ const struct pci_epc_features *cdns_pcie_ep_get_features(= struct pci_epc *epc, u8 func_no, u8 vfunc_no); =20 -#endif /* _PCIE_CADENCE_EP_COMMON_H_ */ +#endif /* _PCIE_CADENCE_EP_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c new file mode 100644 index 000000000000..21264247951e --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define LINK_RETRAIN_TIMEOUT HZ + +u64 bar_max_size[] =3D { + [RP_BAR0] =3D _ULL(128 * SZ_2G), + [RP_BAR1] =3D SZ_2G, + [RP_NO_BAR] =3D _BITULL(63), +}; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +{ + u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + unsigned long end_jiffies; + u16 lnk_stat; + + /* Wait for link training to complete. Exit after timeout. */ + end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; + do { + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + usleep_range(0, 1000); + } while (time_before(jiffies, end_jiffies)); + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} + +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + +int cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret =3D 0; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl =3D cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |=3D PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret =3D cdns_pcie_host_training_complete(pcie); + if (ret) + return ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + } + return ret; +} + +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size <=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] < bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size >=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] > bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} + +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b) +{ + struct resource_entry *entry1, *entry2; + + entry1 =3D container_of(a, struct resource_entry, node); + entry2 =3D container_of(b, struct resource_entry, node); + + return resource_size(entry2->res) - resource_size(entry1->res); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.h new file mode 100644 index 000000000000..f8eae2e963d8 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HOST_COMMON_H +#define _PCIE_CADENCE_HOST_COMMON_H + +#include +#include + +extern u64 bar_max_size[]; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_retrain(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b); + +#endif /* _PCIE_CADENCE_HOST_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 59a4631de79f..bfdd0f200cfb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,14 +12,7 @@ #include =20 #include "pcie-cadence.h" - -#define LINK_RETRAIN_TIMEOUT HZ - -static u64 bar_max_size[] =3D { - [RP_BAR0] =3D _ULL(128 * SZ_2G), - [RP_BAR1] =3D SZ_2G, - [RP_NO_BAR] =3D _BITULL(63), -}; +#include "pcie-cadence-host-common.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -{ - u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - unsigned long end_jiffies; - u16 lnk_stat; - - /* Wait for link training to complete. Exit after timeout. */ - end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; - do { - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - break; - usleep_range(0, 1000); - } while (time_before(jiffies, end_jiffies)); - - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - return 0; - - return -ETIMEDOUT; -} - -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev =3D pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - -static int cdns_pcie_retrain(struct cdns_pcie *pcie) -{ - u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - u16 lnk_stat, lnk_ctl; - int ret =3D 0; - - /* - * Set retrain bit if current speed is 2.5 GB/s, - * but the PCIe root port support is > 2.5 GB/s. - */ - - lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + - PCI_EXP_LNKCAP)); - if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) - return ret; - - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { - lnk_ctl =3D cdns_pcie_rp_readw(pcie, - pcie_cap_off + PCI_EXP_LNKCTL); - lnk_ctl |=3D PCI_EXP_LNKCTL_RL; - cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, - lnk_ctl); - - ret =3D cdns_pcie_host_training_complete(pcie); - if (ret) - return ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - } - return ret; -} - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) { u32 val; @@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct c= dns_pcie *pcie) cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL= _PTMRSEN); } =20 -static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) -{ - struct cdns_pcie *pcie =3D &rc->pcie; - int ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - - /* - * Retrain link for Gen2 training defect - * if quirk flag is set. - */ - if (!ret && rc->quirk_retrain_flag) - ret =3D cdns_pcie_retrain(pcie); - - return ret; -} - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; @@ -290,54 +195,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pc= ie_rc *rc, return 0; } =20 -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size <=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] < bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size >=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] > bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, struct resource_entry *entry) { @@ -410,17 +267,6 @@ static int cdns_pcie_host_bar_config(struct cdns_pcie_= rc *rc, return 0; } =20 -static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_hea= d *a, - const struct list_head *b) -{ - struct resource_entry *entry1, *entry2; - - entry1 =3D container_of(a, struct resource_entry, node); - entry2 =3D container_of(b, struct resource_entry, node); - - return resource_size(entry2->res) - resource_size(entry1->res); -} - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023106.outbound.protection.outlook.com [52.101.127.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A918D25229D; Fri, 8 Aug 2025 07:29:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.127.106 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638186; cv=fail; b=LUmxtxvut4aSIMl+nkJ8kB3Q1vNASxLIyVPxyHCjcIypesu0YKzAWV1ct0zsFsYHp+a2bcl4mvPUdesX2i2Pyom0UcfgyjqYLlWwcUlux8YoiW0PHY93nudyTzNBzk0Mlwsj1rcXxseify7JkXO6t4v8/mZ3NvVTUNnU/w5urlc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638186; c=relaxed/simple; bh=7BELHzqkhXvAQNh69pfQa8evyvK+gemxPF41GgRNJ+Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a5O90m23GCcJtQEGIM3rmhSLzrFjKDhnEKU4UpPaLkDZW95pdwHlk1e5YGOHpTHib+4cFd/bKD5r6ShGc9Gw2Dxn56ryjjgHft2nnMUz8oXgc7cgPnBqttQP0BEHj+5qn2A/+c9xz/TGZrvwm6Wh5KisAOaNb9d/ALujwgA3Z5g= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.127.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OHYvNdpBJZmUEiUZgwBvjH/n+jx90O5WGvxkvSx4r5O1uQRQFRrMnJcGR+MJtZV6ajxSIvMvff+wIRdT6GCrcsbMzqhTu1xwACwt7c8eQib/PijgVgfZM8qb08jxLL3fEH2Beay2vs9pmJQwQJ2Q1Gjp1AGGemmm8FDXrK7eUUJO5o17HrrajvlUfjmQwNFxD8W87Mc+pPIsU5zwuvtVR6YjEj/oGsCGtUjQ0qUjgd5215Oz7PkRggH6Wg5+vu0E+A5VWTkUpwYugcBqHMTpdJkc+jHJFMPvpKbl8VLqu+qcy9jxxz6vlLRJfb3vi1x8Rg++5nP4tjADUH1mx290Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2qN+Up9kIATMmuh6cmk47JBfVdWrE5lK20Tk1ip3bYo=; b=AjTsAYguKR++JOG9cv8FKJBtOwOzGiwBVVaPL9MCM+WOGlWAfbLo90UeKMuo8jUKb+sHp0kV8fYldEeH7AOYjW4rKMj0an0x7EtLkvJB4jeBYmLbOO0suby1wh5X0F8rcgm/MmgmQUSseLbLvfxLYK2sKTQvjQNNZna53POrrpaiLQ8pzVtxrR92Gm59hcyEoSLYBNVSH2i5E5ZS4uq8cLysapeFrHw1CZ2k96qpp26xaAv9okAjLisL57dtVzOsjIHJbTQPMHyeyMrcvwoNRss4pxsJvSO1minNWHI3/PYlnNBhpbXPpQcZP33d25zu3WWs+G/9rmoMNzeJcTJ5/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TYCP286CA0363.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:79::10) by SI2PR06MB5386.apcprd06.prod.outlook.com (2603:1096:4:1ed::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.16; Fri, 8 Aug 2025 07:29:36 +0000 Received: from TY2PEPF0000AB8A.apcprd03.prod.outlook.com (2603:1096:405:79:cafe::32) by TYCP286CA0363.outlook.office365.com (2603:1096:405:79::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB8A.mail.protection.outlook.com (10.167.253.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:35 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 4B61541604E0; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 05/12] PCI: cadence: Split the common functions for PCIe controller support Date: Fri, 8 Aug 2025 15:29:22 +0800 Message-ID: <20250808072929.4090694-6-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|SI2PR06MB5386:EE_ X-MS-Office365-Filtering-Correlation-Id: 95a17d84-f384-48af-b7e7-08ddd64d53e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8Tvp8HxG0nXTaqCcnjxJYzwulPSWAmYWpW3gYwpXXBhY3XLiSqC6iQhr6Bi3?= =?us-ascii?Q?0xKWd98eEw0xTnao9wUk8re711EF8/DZceLHLLD009n6qMsM2/Vmgkcn61+8?= =?us-ascii?Q?HV2jhGTOOcXRzw87/zyl75NaOSBKJnZekVMcfd36BEVqsPTd6EHhjdUQjWVL?= =?us-ascii?Q?X4MYSlCP8NUFuTqxcRAmMKkqosPyXSOFlswsCuHx5ZzkuwQBCTDotg5AwkE+?= =?us-ascii?Q?jtFeSNOAuhJss7iwnIh1FU9tRMwASW+fYpnHtakUubf+UzZaKdOPxJtfG4Ho?= =?us-ascii?Q?6d3VClDcYViN1IDIXIl9h1QeyHZu1Md1y/2foLbEGsOuBR0UIyH7FROruVsE?= =?us-ascii?Q?WAR5S3ihdGSljsYYnr4CNC1HEx2as/LQz+ZFbjIwUHkmY48yPBBrr9XoCjtC?= =?us-ascii?Q?hE/GqdEN4w2sOJQNTLHvBwiuS/91zjt2Aip5Tej4mDbkV/H98XUwmlmpkHg7?= =?us-ascii?Q?djvHlNLtEQ1fYbCdYZsmAxRGXjbAdBMSNO6q/DAwBOkuIiCHHLVYXlvEONfV?= =?us-ascii?Q?RI8aPPpwfY0kasDufjEKAXFTZHG/1Vlrm2FfpBZmoSG7+nMocJdJ1s5j4adU?= =?us-ascii?Q?y3d9TImAvcYeyJXZntN8vXPH2dwBL3aScibQ8PxuLVqZnv5aJ+JOPCgGVx5W?= =?us-ascii?Q?mxQbrFZWHJmUGA34wkfEllSxRk/tUz4TblnuI021z71sNoF8D54LmPJOXNHH?= =?us-ascii?Q?FijD7WY4ugjnC7IvCBgRqOzqaKwCWNt7ThKtipDKcJL4qb4ewjHYtXlxdKcu?= =?us-ascii?Q?Ub1kdlKWN9H5aRgv+HGJZILDe2+5cPotXBOfAa9WvRBYgPl8cOoF9yR94pl5?= =?us-ascii?Q?NEzXjF0XgY8b2/HIyvQPd9ZkVxt7+y7rd4rIpSXMU59gZXrjYT7jGpDJC++8?= =?us-ascii?Q?yNTs08joKr/6row7WGTclVuPh3rZDON5UBkqgSCW3FoP/e0fLZmcu1R5wWrZ?= =?us-ascii?Q?PABUkmlHjjlI5k/LBOm91CaEg3WMMQFpaOD64xbjq21CasGc0M1ZQhoefidL?= =?us-ascii?Q?AroQE/GFCCv9rrjflyxAABikiWF2sQmjPm7qdR4TGxy5L6O8ZWtcRXjXlOjA?= =?us-ascii?Q?SC/A8/IgGqlStvZF/brCVcmLn/CVUnIvxbAvX103Wwa+6fbEfKXQV+8FEK6X?= =?us-ascii?Q?4S/2jeXPuzeXb8FDG0GzM1lbXoIvHkvBPVK/ydCuxF8XQUpTnWuJoUVIWfp3?= =?us-ascii?Q?hMlyGti90cCatW7Z6eO4Z+C1jRJIlSMguUqNm338ihzDhNIaMBzDQYZJGa9A?= =?us-ascii?Q?NyRabyc9l5+pOAhqDeY4vNsePVh9LmND/b41G9PdZDR8/mH1QTnyjzA8mtPw?= =?us-ascii?Q?SaYmFPtg7BJKGWWhO0OW+T8/1+xe1nTLRI+JfjiNVa5Kmp0tVNw3L02evtV8?= =?us-ascii?Q?qu/mAOkWAEH2r6GUvCBPBEDDReKmIF4NM4LnIchfgnJ2NnG9qxhYU22scq+i?= =?us-ascii?Q?rsl+QnhJLasFe5XZq9zd2szzNnqUTBf8wTubfpim7eAeec9JURiJVA8Tiu2y?= =?us-ascii?Q?F65fYDnT9gQBvUc16r0Q2+KsYcTNuiH+hgHf?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:35.9120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95a17d84-f384-48af-b7e7-08ddd64d53e2 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2PR06MB5386 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Separate the functions for platform specific tasks and common library tasks into different files. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../controller/cadence/pcie-cadence-common.c | 138 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 128 ---------------- 3 files changed, 139 insertions(+), 129 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-common.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 0440ac6aba5d..3fe5dd2bbd5b 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-common.c b/drivers= /pci/controller/cadence/pcie-cadence-common.c new file mode 100644 index 000000000000..90e2b008774f --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-common.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +void cdns_pcie_disable_phy(struct cdns_pcie *pcie) +{ + int i =3D pcie->phy_count; + + while (i--) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } +} +EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); + +int cdns_pcie_enable_phy(struct cdns_pcie *pcie) +{ + int ret; + int i; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret =3D phy_power_on(pcie->phy[i]); + if (ret < 0) { + phy_exit(pcie->phy[i]); + goto err_phy; + } + } + + return 0; + +err_phy: + while (--i >=3D 0) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); + +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) +{ + struct device_node *np =3D dev->of_node; + int phy_count; + struct phy **phy; + struct device_link **link; + int i; + int ret; + const char *name; + + phy_count =3D of_property_count_strings(np, "phy-names"); + if (phy_count < 1) { + dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); + pcie->phy_count =3D 0; + return 0; + } + + phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i =3D 0; i < phy_count; i++) { + of_property_read_string_index(np, "phy-names", i, &name); + phy[i] =3D devm_phy_get(dev, name); + if (IS_ERR(phy[i])) { + ret =3D PTR_ERR(phy[i]); + goto err_phy; + } + link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + devm_phy_put(dev, phy[i]); + ret =3D -EINVAL; + goto err_phy; + } + } + + pcie->phy_count =3D phy_count; + pcie->phy =3D phy; + pcie->link =3D link; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) + goto err_phy; + + return 0; + +err_phy: + while (--i >=3D 0) { + device_link_del(link[i]); + devm_phy_put(dev, phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); + +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +const struct dev_pm_ops cdns_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; +EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 70a19573440e..51c9bc4eb174 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -152,134 +152,6 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie= *pcie, u32 r) } EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region); =20 -void cdns_pcie_disable_phy(struct cdns_pcie *pcie) -{ - int i =3D pcie->phy_count; - - while (i--) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } -} -EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); - -int cdns_pcie_enable_phy(struct cdns_pcie *pcie) -{ - int ret; - int i; - - for (i =3D 0; i < pcie->phy_count; i++) { - ret =3D phy_init(pcie->phy[i]); - if (ret < 0) - goto err_phy; - - ret =3D phy_power_on(pcie->phy[i]); - if (ret < 0) { - phy_exit(pcie->phy[i]); - goto err_phy; - } - } - - return 0; - -err_phy: - while (--i >=3D 0) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); - -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) -{ - struct device_node *np =3D dev->of_node; - int phy_count; - struct phy **phy; - struct device_link **link; - int i; - int ret; - const char *name; - - phy_count =3D of_property_count_strings(np, "phy-names"); - if (phy_count < 1) { - dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); - pcie->phy_count =3D 0; - return 0; - } - - phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); - if (!link) - return -ENOMEM; - - for (i =3D 0; i < phy_count; i++) { - of_property_read_string_index(np, "phy-names", i, &name); - phy[i] =3D devm_phy_get(dev, name); - if (IS_ERR(phy[i])) { - ret =3D PTR_ERR(phy[i]); - goto err_phy; - } - link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); - if (!link[i]) { - devm_phy_put(dev, phy[i]); - ret =3D -EINVAL; - goto err_phy; - } - } - - pcie->phy_count =3D phy_count; - pcie->phy =3D phy; - pcie->link =3D link; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) - goto err_phy; - - return 0; - -err_phy: - while (--i >=3D 0) { - device_link_del(link[i]); - devm_phy_put(dev, phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); - -static int cdns_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - - cdns_pcie_disable_phy(pcie); - - return 0; -} - -static int cdns_pcie_resume_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); - int ret; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) { - dev_err(dev, "failed to enable PHY\n"); - return ret; - } - - return 0; -} - -const struct dev_pm_ops cdns_pcie_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, - cdns_pcie_resume_noirq) -}; - MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Cadence PCIe controller driver"); MODULE_AUTHOR("Cyrille Pitchen "); --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023130.outbound.protection.outlook.com [40.107.44.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 605C123B62C; Fri, 8 Aug 2025 07:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.130 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638185; cv=fail; b=NtXvX1tv3ZFlag1Hfyf18Q5UBeJvz377vJMAg2JdGlkazXAEZm+3zmj4kO6qH42SG93Jpnte20fDg1oC6HJ0A5EabRtGrqS0JJoAckxLkr4XVF/2dwS0wpuyEhUeK/+NbvzPDKn5Ss3FrlMBqlU7Pa0pkKnvLUpzRZBhCUCIs2g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638185; c=relaxed/simple; bh=A7tZhdw52YoguH3DLtGr+NNZsyU56np4kI1XubEEK0I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eXiHXQemCQ8pOYLOaGBYF26VpEgnJJQQBHH4w21fHU50cmuLJ+qVAgAZC7k9yM2P+B6DaKds8jFtM3mmq1JIHhvAKpWK2tyJw1jBiwOcrBkW1/OvmDWy3HCdBNWP7fxoNeKh1p6q3+7q5Lv+YAmiDDrPhg27XYSbhGbAIUh4Jtg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Fm37u7c5UkgGnMH7AGz1frv0qhrXuFbvrxRGfbLKtILX119FRxe9f14wj1/58Rlf2ADo2omXF0HrGj6almJiE1nvEDLMYx5L1mWMS/5dFJ8oxlgIwTdt0dqPP14+OKMSTzFFYTkEJZIKgAxM9SvxPj7gYZRUu+KXOXxcQTau9smcE6W1Ukgxq5giF4Ln1JOhL11RHRlr/ToDRhXwDcsgxb0+e1ccPWUaoN9j4o0CK/JXZIf9WWLUhL2zlYQ0g4LbkL8jOsUUkEnPh6IXHSm79UUD5hiap8jXcgEQPouprRtS7YKn4H55olRfc2VyTbbCwx4Fpjgrl+UIfOJNZIMDMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OZV0o1VNVnOjg4wFUbU/ECQaigTHNd5oQy+h+nZU7G4=; b=qKfbuokdcfW0sI/UmGDLl1RiAdiYQBUR7cTG/VNt1bobn8Kb55sysB2mxYnGZ+5++SX5jb9wqtVNMOJ7HyVTikF97eg/a5Y6JS3T8RFWqDMuTSPlS3zupCyC6OpA9gDDf/or1p5+jghIuhEHL7Y8vHcKcs+CW4qQF2yPGMmVDiWr1aQVECQXMXqzTNA9MCnFsS/exRuHRZpFW8QU8Pr6ExzBuBdeIZlmWUd0hBaUZrfSOUpAsIJcd+WeO9skFn7J+IZASNk2O+fAM+xCm5p9qUBfm/Dtarc5/8h8RDBiFYAg/uFbfpi+0lyY8OSElzpd4ylWcIh2AA64t38Pg5UCbw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SG2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:3:18::25) by TYSPR06MB6443.apcprd06.prod.outlook.com (2603:1096:400:480::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:36 +0000 Received: from SG2PEPF000B66CA.apcprd03.prod.outlook.com (2603:1096:3:18:cafe::c0) by SG2PR02CA0037.outlook.office365.com (2603:1096:3:18::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CA.mail.protection.outlook.com (10.167.240.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:35 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 5E25441604E6; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 06/12] PCI: cadence: Add support for High Performance Arch(HPA) controller Date: Fri, 8 Aug 2025 15:29:23 +0800 Message-ID: <20250808072929.4090694-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|TYSPR06MB6443:EE_ X-MS-Office365-Filtering-Correlation-Id: daebad85-088d-41db-486c-08ddd64d539d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?r7/5Q5lau4OEG4WIiyXl8qzfj0DPLnAKeLc23l41r01m0e18Rp0UTSK6tfXD?= =?us-ascii?Q?1uD7MLTHuIahOrST2C5/neoeUUNpTMDQj8xY+KtmChpz1aDuaUii6yvYNV0B?= =?us-ascii?Q?0CLqXGRg0siGI9KCCNMrxyYsAp9YPbjjGB1e+bVS+EWrUXAlh2X3V1QPnH2L?= =?us-ascii?Q?TIiWqLLj3kuuUz2xv2cAUcw1FTyX1ZzQ/ipwCO6dDOS8MGCrRROuC64NmaBQ?= =?us-ascii?Q?ZBqPWmkEAfjiIFLt9xsoSXIbsGL+VfhIpwSA3AYrvytZPQ7mIAO/no36FqkP?= =?us-ascii?Q?xRzplr+woS3eM8faAhnskzlfmUfTNVHuuKe7YeHNHSnCXhL5qflDxdtqB4MY?= =?us-ascii?Q?0VuQ6qyNChf478loAo7uoV055ia4pBCaKK9Fy4ME3LLH6+gazFK1o83Aa+W+?= =?us-ascii?Q?x63IgGUCegMbcO7L5UaG82zFpfYMdPjKASme0FZnP2jVKayTCBBNb0l3PCor?= =?us-ascii?Q?/C3CFLlw6C4U3orim4gNeEsyhPpl++Ft0ABT/x9p8u7SMozD6pR3FUf6L1Jp?= =?us-ascii?Q?OQL1rZO/1HpJ2pJDrz9rOzpcGGy/kZwIX9DjJdARTXGadu1adMXRzn8OObKL?= =?us-ascii?Q?FBTXlSJaLHIn0K40u0vqrOWHgd9PERm1nH/UYCn66CLPrIJxi2kAFEzQZA/2?= =?us-ascii?Q?ZVVPQpbXN0SEuF9CmVL9LI2D8vIlaq4NKb74pFPH/rPXgcUT2kwOJoMkSWeU?= =?us-ascii?Q?fxhhiihDACaJVZ2sRRJFXPAPUOcF7nszb/g8r1afkf76E9Iv9OOsDywlQxO/?= =?us-ascii?Q?h53fez8CvnB1aywH8ske59pe2h0ZCLgiAQrmA1qyJ3P5Ef2Q6YSFXBYO1VHS?= =?us-ascii?Q?buAg9f6Gi0VY6JL8oYt3dOzgMN0qB/YsFSEUg1lJLxsEus3bsRq/Npfjfhl9?= =?us-ascii?Q?d0h7pC02rH3AC58Wp4RjExLh4J67XxSB02yYHfr8mbmUfBaFO7N6/6zjvoe4?= =?us-ascii?Q?aSbMSp/DljU6K07cSsDsZj29hIirzzAXDU2Mh7B9az1/BKGrEWCHwXJ++Ecl?= =?us-ascii?Q?jYPtcuD+gci4L1IW1WWX//rTbyQQ7xJ1/TrE2G+uieNUSp6ii55IBOV9qlAh?= =?us-ascii?Q?Ds8Sm+sHUO1zKk/zG0y7gm1A6zgTTnSXQ5TBIViCMge+rnw0vHdHLM8CDHto?= =?us-ascii?Q?raJPfCw9YfkPky7+o/z4pVDetVB70MOSner34CSh5Xg930zvA/FnuTxUYTOx?= =?us-ascii?Q?DUYmPaogNJcWSMyS81a864KYeaxa8gKszGJy/BOiyMKqlOuBBxoGB6pYuzqG?= =?us-ascii?Q?1Z9CZMuEpQVyQf8K3LNNjk2k5u0R34MqQoji9q8HbkJdSrFpf0f9E8KRyjBr?= =?us-ascii?Q?nZYrmlZuesWjjsKMPWxMI3v8Ha62PvhhmsKwe96DahEwKwv38bFTTcLphOsG?= =?us-ascii?Q?iYHsNn41iFZFuyrk80rQ1LR/modalScaqXI4vm4srkZM7K/DtNEEVu6uR8aZ?= =?us-ascii?Q?L15b6zlHe6SttUuAQbyoYtl+1UW412zDpCBJzyFpnyP4YFz3VHW/ECtmOKFo?= =?us-ascii?Q?Bwa7A0jDLzDwkWNSywA1Xoxxchcd5BkrdVkf?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:35.6494 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: daebad85-088d-41db-486c-08ddd64d539d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6443 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence PCIe RP and EP configuration for High Performance Architecture(HPA) controllers. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 6 +- .../controller/cadence/pcie-cadence-ep-hpa.c | 523 ++++++++++++++++ .../cadence/pcie-cadence-host-hpa.c | 576 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-hpa.c | 199 ++++++ .../controller/cadence/pcie-cadence-plat.c | 19 +- drivers/pci/controller/cadence/pcie-cadence.c | 10 + drivers/pci/controller/cadence/pcie-cadence.h | 89 ++- 7 files changed, 1407 insertions(+), 15 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 3fe5dd2bbd5b..e2df24ff4c33 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o pcie-= cadence-hpa.o obj-$(CONFIG_PCIE_CADENCE_EP_COMMON) +=3D pcie-cadence-ep-common.o obj-$(CONFIG_PCIE_CADENCE_HOST_COMMON) +=3D pcie-cadence-host-common.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o pcie-cadence-host= -hpa.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-cadence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c b/drivers= /pci/controller/cadence/pcie-cadence-ep-hpa.c new file mode 100644 index 000000000000..5d769a460d76 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +static int cdns_pcie_hpa_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u64 pci_addr, size_t size) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + r =3D find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); + if (r >=3D ep->max_regions - 1) { + dev_err(&epc->dev, "no free outbound region\n"); + return -EINVAL; + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, = size); + + set_bit(r, &ep->ob_region_map); + ep->ob_addr[r] =3D addr; + + return 0; +} + +static void cdns_pcie_hpa_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + for (r =3D 0; r < ep->max_regions - 1; r++) + if (ep->ob_addr[r] =3D=3D addr) + break; + + if (r =3D=3D ep->max_regions - 1) + return; + + cdns_pcie_hpa_reset_outbound_region(pcie, r); + + ep->ob_addr[r] =3D 0; + clear_bit(r, &ep->ob_region_map); +} + +static void cdns_pcie_hpa_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u= 8 intx, + bool is_asserted) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + unsigned long flags; + u32 offset; + u16 status; + u8 msg_code; + + intx &=3D 3; + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, ep->irq= _phys_addr); + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; + ep->irq_pci_fn =3D fn; + } + + if (is_asserted) { + ep->irq_pending |=3D BIT(intx); + msg_code =3D PCIE_MSG_CODE_ASSERT_INTA + intx; + } else { + ep->irq_pending &=3D ~BIT(intx); + msg_code =3D PCIE_MSG_CODE_DEASSERT_INTA + intx; + } + + spin_lock_irqsave(&ep->lock, flags); + status =3D cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); + if (((status & PCI_STATUS_INTERRUPT) !=3D 0) ^ (ep->irq_pending !=3D 0)) { + status ^=3D PCI_STATUS_INTERRUPT; + cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); + } + spin_unlock_irqrestore(&ep->lock, flags); + + offset =3D CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); + writel(0, ep->irq_cpu_addr + offset); +} + +static int cdns_pcie_hpa_ep_send_intx_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u8 intx) +{ + u16 cmd; + + cmd =3D cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); + if (cmd & PCI_COMMAND_INTX_DISABLE) + return -EINVAL; + + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, true); + + /* The mdelay() value was taken from dra7xx_pcie_raise_intx_irq() */ + mdelay(1); + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, false); + return 0; +} + +static int cdns_pcie_hpa_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u= 8 vfn, + u8 interrupt_num) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask =3D 0xff; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D (data & ~data_mask) | ((interrupt_num - 1) & data_mask); + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr !=3D (pci_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + pci_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (pci_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u16 interrupt_num) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg; + struct cdns_pcie *pcie =3D &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask =3D 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + epf =3D &ep->epf[fn]; + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI-X feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg =3D cap + PCI_MSIX_TABLE; + tbl_offset =3D cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir =3D FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); + tbl_offset &=3D PCI_MSIX_TABLE_OFFSET; + + msix_tbl =3D epf->epf_bar[bir]->addr + tbl_offset; + msg_addr =3D msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data =3D msix_tbl[(interrupt_num - 1)].msg_data; + + /* Set the outbound region if needed. */ + if (ep->irq_pci_addr !=3D (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn) { + /* First region was reserved for IRQ writes. */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, + unsigned int type, u16 interrupt_num) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + + switch (type) { + case PCI_IRQ_INTX: + if (vfn > 0) { + dev_err(dev, "Cannot raise INTX interrupts for VF\n"); + return -EINVAL; + } + return cdns_pcie_hpa_ep_send_intx_irq(ep, fn, vfn, 0); + + case PCI_IRQ_MSI: + return cdns_pcie_hpa_ep_send_msi_irq(ep, fn, vfn, interrupt_num); + + case PCI_IRQ_MSIX: + return cdns_pcie_hpa_ep_send_msix_irq(ep, fn, vfn, interrupt_num); + + default: + break; + } + + return -EINVAL; +} + +static int cdns_pcie_hpa_ep_start(struct pci_epc *epc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + int max_epfs =3D sizeof(epc->function_num_map) * 8; + int ret, epf, last_fn; + u32 reg, value; + + /* + * BIT(0) is hardwired to 1, hence function 0 is always enabled + * and can't be disabled anyway. + */ + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_LM_EP_FUNC_CFG, epc->function_num_map); + + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. Clear Next Function Number field for the last + * function used. + */ + last_fn =3D find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg =3D CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value =3D cdns_pcie_readl(pcie, reg); + value &=3D ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + + if (ep->quirk_disable_flr) { + for (epf =3D 0; epf < max_epfs; epf++) { + if (!(epc->function_num_map & BIT(epf))) + continue; + + value =3D cdns_pcie_ep_fn_readl(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); + value &=3D ~PCI_EXP_DEVCAP_FLR; + cdns_pcie_ep_fn_writel(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); + } + } + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + return 0; +} + +static int cdns_pcie_hpa_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + dma_addr_t bar_phys =3D epf_bar->phys_addr; + enum pci_barno bar =3D epf_bar->barno; + int flags =3D epf_bar->flags; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz =3D max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); + + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + sz =3D 1ULL << fls64(sz - 1); + + /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + aperture =3D ilog2(sz) - 7; + + if ((flags & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch =3D !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits =3D !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS; + } + + addr0 =3D lower_32_bits(bar_phys); + addr1 =3D upper_32_bits(bar_phys); + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), addr1); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D epf_bar; + + return 0; +} + +static void cdns_pcie_hpa_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + enum pci_barno bar =3D epf_bar->barno; + u32 reg, cfg, b, ctrl; + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D NULL; +} + +static const struct pci_epc_ops cdns_pcie_hpa_epc_ops =3D { + .write_header =3D cdns_pcie_ep_write_header, + .set_bar =3D cdns_pcie_hpa_ep_set_bar, + .clear_bar =3D cdns_pcie_hpa_ep_clear_bar, + .map_addr =3D cdns_pcie_hpa_ep_map_addr, + .unmap_addr =3D cdns_pcie_hpa_ep_unmap_addr, + .set_msi =3D cdns_pcie_ep_set_msi, + .get_msi =3D cdns_pcie_ep_get_msi, + .set_msix =3D cdns_pcie_ep_set_msix, + .get_msix =3D cdns_pcie_ep_get_msix, + .raise_irq =3D cdns_pcie_hpa_ep_raise_irq, + .map_msi_irq =3D cdns_pcie_ep_map_msi_irq, + .start =3D cdns_pcie_hpa_ep_start, + .get_features =3D cdns_pcie_ep_get_features, +}; + +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + struct device *dev =3D ep->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; + struct cdns_pcie *pcie =3D &ep->pcie; + struct cdns_pcie_epf *epf; + struct resource *res; + struct pci_epc *epc; + int ret; + int i; + + pcie->is_rc =3D false; + + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); + if (!res) { + dev_err(dev, "missing \"mem\"\n"); + return -EINVAL; + } + pcie->mem_res =3D res; + + ep->max_regions =3D CDNS_PCIE_MAX_OB; + of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); + + ep->ob_addr =3D devm_kcalloc(dev, + ep->max_regions, sizeof(*ep->ob_addr), + GFP_KERNEL); + if (!ep->ob_addr) + return -ENOMEM; + + epc =3D devm_pci_epc_create(dev, &cdns_pcie_hpa_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + return PTR_ERR(epc); + } + + epc_set_drvdata(epc, ep); + + if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) + epc->max_functions =3D 1; + + ep->epf =3D devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + + epc->max_vfs =3D devm_kcalloc(dev, epc->max_functions, + sizeof(*epc->max_vfs), GFP_KERNEL); + if (!epc->max_vfs) + return -ENOMEM; + + ret =3D of_property_read_u8_array(np, "max-virtual-functions", + epc->max_vfs, epc->max_functions); + if (ret =3D=3D 0) { + for (i =3D 0; i < epc->max_functions; i++) { + epf =3D &ep->epf[i]; + if (epc->max_vfs[i] =3D=3D 0) + continue; + epf->epf =3D devm_kcalloc(dev, epc->max_vfs[i], + sizeof(*ep->epf), GFP_KERNEL); + if (!epf->epf) + return -ENOMEM; + } + } + + ret =3D pci_epc_mem_init(epc, pcie->mem_res->start, + resource_size(pcie->mem_res), PAGE_SIZE); + if (ret < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + return ret; + } + + ep->irq_cpu_addr =3D pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, + SZ_128K); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + ret =3D -ENOMEM; + goto free_epc_mem; + } + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; + /* Reserve region 0 for IRQs */ + set_bit(0, &ep->ob_region_map); + + if (ep->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&ep->pcie); + + spin_lock_init(&ep->lock); + + pci_epc_init_notify(epc); + + return 0; + + free_epc_mem: + pci_epc_mem_exit(epc); + + return ret; +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c new file mode 100644 index 000000000000..5b2b69f9efd9 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +static u8 bar_aperture_mask[] =3D { + [RP_BAR0] =3D 0x1F, + [RP_BAR1] =3D 0xF, +}; + +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc =3D pci_host_bridge_priv(bridge); + struct cdns_pcie *pcie =3D &rc->pcie; + unsigned int busn =3D bus->number; + u32 addr0, desc0, desc1, ctrl0; + u32 regval; + + if (pci_is_root_bus(bus)) { + /* + * Only the root port (devfn =3D=3D 0) is connected to this bus. + * All other PCI devices are behind some bridge hence on another + * bus. + */ + if (devfn) + return NULL; + + return pcie->reg_base + (where & 0xfff); + } + + /* Clear AXI link-down status */ + regval =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT= _LINKDOWN); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, + (regval & ~GENMASK(0, 0))); + + desc1 =3D 0; + ctrl0 =3D 0; + + /* Update Output registers for AXI region 0. */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); + + desc1 =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); + desc1 &=3D ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + + if (busn =3D=3D bridge->busnr + 1) + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); + + return rc->cfg_base + (where & 0xfff); +} + +int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + return -ETIMEDOUT; +} + +int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} + +static struct pci_ops cdns_pcie_hpa_host_ops =3D { + .map_bus =3D cdns_pci_hpa_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + +static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_C= TRL); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, + val | CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN); +} + +static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, + enum cdns_pcie_rp_bar bar, + u64 cpu_addr, u64 size, + unsigned long flags) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 addr0, addr1, aperture, value; + + if (!rc->avail_ib_bar[bar]) + return -EBUSY; + + rc->avail_ib_bar[bar] =3D false; + + aperture =3D ilog2(size); + addr0 =3D CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); + + if (bar =3D=3D RP_NO_BAR) + return 0; + + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_H= PA_LM_RC_BAR_CFG); + value &=3D ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); + if (size + cpu_addr >=3D SZ_4G) { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); + } else { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); + } + + value |=3D HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_= BAR_CFG, value); + + return 0; +} + +static int cdns_pcie_hpa_host_bar_config(struct cdns_pcie_rc *rc, + struct resource_entry *entry) +{ + u64 cpu_addr, pci_addr, size, winsize; + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + enum cdns_pcie_rp_bar bar; + unsigned long flags; + int ret; + + cpu_addr =3D entry->res->start; + pci_addr =3D entry->res->start - entry->offset; + flags =3D entry->res->flags; + size =3D resource_size(entry->res); + + if (entry->offset) { + dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", + pci_addr, cpu_addr); + return -EINVAL; + } + + while (size > 0) { + /* + * Try to find a minimum BAR whose size is greater than + * or equal to the remaining resource_entry size. This will + * fail if the size of each of the available BARs is less than + * the remaining resource_entry size. + * If a minimum BAR is found, IB ATU will be configured and + * exited. + */ + bar =3D cdns_pcie_host_find_min_bar(rc, size); + if (bar !=3D RP_BAR_UNDEFINED) { + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, + size, flags); + if (ret) + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + /* + * If the control reaches here, it would mean the remaining + * resource_entry size cannot be fitted in a single BAR. So we + * find a maximum BAR whose size is less than or equal to the + * remaining resource_entry size and split the resource entry + * so that part of resource entry is fitted inside the maximum + * BAR. The remaining size would be fitted during the next + * iteration of the loop. + * If a maximum BAR is not found, there is no way we can fit + * this resource_entry, so we error out. + */ + bar =3D cdns_pcie_host_find_max_bar(rc, size); + if (bar =3D=3D RP_BAR_UNDEFINED) { + dev_err(dev, "No free BAR to map cpu_addr %llx\n", + cpu_addr); + return -EINVAL; + } + + winsize =3D bar_max_size[bar]; + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, winsize, fla= gs); + if (ret) { + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + size -=3D winsize; + cpu_addr +=3D winsize; + } + + return 0; +} + +static int cdns_pcie_hpa_host_map_dma_ranges(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + struct device_node *np =3D dev->of_node; + struct pci_host_bridge *bridge; + struct resource_entry *entry; + u32 no_bar_nbits =3D 32; + int err; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + if (list_empty(&bridge->dma_ranges)) { + of_property_read_u32(np, "cdns,no-bar-match-nbits", + &no_bar_nbits); + err =3D cdns_pcie_hpa_host_bar_ib_config(rc, RP_NO_BAR, 0x0, + (u64)1 << no_bar_nbits, 0); + if (err) + dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); + return err; + } + + list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + err =3D cdns_pcie_hpa_host_bar_config(rc, entry); + if (err) { + dev_err(dev, "Fail to configure IB using dma-ranges\n"); + return err; + } + } + + return 0; +} + +static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, ctrl; + + /* + * Set the root complex BAR configuration register: + * - disable both BAR0 and BAR1. + * - enable Prefetchable Memory Base and Limit registers in type 1 + * config space (64 bits). + * - enable IO Base and Limit registers in type 1 config + * space (32 bits). + */ + + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + value =3D CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, + CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); + + if (rc->vendor_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + + if (rc->device_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); + + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + + return 0; +} + +static void cdns_pcie_hpa_create_region_for_ecam(struct cdns_pcie_rc *rc) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, root_port_req_id_reg, pcie_bus_number_reg; + u32 ecam_addr_0, region_size_0, request_id_0; + int busnr =3D 0, secbus =3D 0, subbus =3D 0; + struct resource_entry *entry; + resource_size_t size; + u32 axi_address_low; + int nbits; + u64 sz; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) { + busnr =3D entry->res->start; + secbus =3D (busnr < 0xff) ? (busnr + 1) : 0xff; + subbus =3D entry->res->end; + } + size =3D resource_size(cfg_res); + sz =3D 1ULL << fls64(size - 1); + nbits =3D ilog2(sz); + if (nbits < 8) + nbits =3D 8; + + root_port_req_id_reg =3D ((busnr & 0xff) << 8); + pcie_bus_number_reg =3D ((subbus & 0xff) << 16) | ((secbus & 0xff) << 8) | + (busnr & 0xff); + ecam_addr_0 =3D cfg_res->start; + region_size_0 =3D nbits - 1; + request_id_0 =3D ((busnr & 0xff) << 8); + +#define CDNS_PCIE_HPA_TAG_MANAGEMENT (0x0) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x200000); + + /* Taking slave err as OKAY */ +#define CDNS_PCIE_HPA_SLAVE_RESP (0x100) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_SLAVE_RESP, + 0x0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_SLAVE_RESP + 0x4, 0x0); + + /* Program the register "i_root_port_req_id_reg" with RP's BDF */ +#define I_ROOT_PORT_REQ_ID_REG (0x141c) + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, I_ROOT_PORT_REQ_ID_REG, + root_port_req_id_reg); + + /** + * Program the register "i_pcie_bus_numbers" with Primary(RP's bus number= ), + * secondary and subordinate bus numbers + */ +#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) + cdns_pcie_hpa_writel(pcie, REG_BANK_RP, I_PCIE_BUS_NUMBERS, + pcie_bus_number_reg); + + /* Program the register "lm_hal_sbsa_ctrl[0]" to enable the sbsa */ +#define LM_HAL_SBSA_CTRL (0x1170) + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL); + value |=3D BIT(0); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL, value); + + /* Program region[0] for ECAM */ + axi_address_low =3D (ecam_addr_0 & 0xfff00000) | region_size_0; + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), + axi_address_low); + + /* rc0-high-axi-address */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), 0x0); + /* Type-1 CFG */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), + (request_id_0 << 16)); + + /* All AXI bits pass through PCIe */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), 0x1b); + /* PCIe address-high */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); +} + +static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct resource_entry *entry; + u64 cpu_addr =3D cfg_res->start; + u32 addr0, addr1, desc1; + int busnr =3D 0; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all. + */ + addr1 =3D 0; + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); +} + +static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc= *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource_entry *entry; + int r =3D 0, busnr =3D 0; + + if (rc->ecam_support_flag) + cdns_pcie_hpa_create_region_for_ecam(rc); + else + cdns_pcie_hpa_create_region_for_cfg(rc); + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + r++; + if (pcie->msg_res) + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, + pcie->msg_res->start); + + r++; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res =3D entry->res; + u64 pci_addr =3D res->start - entry->offset; + + if (resource_type(res) =3D=3D IORESOURCE_IO) + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); + else + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + false, + res->start, + pci_addr, + resource_size(res)); + + r++; + } + + if (rc->no_inbound_flag) + return 0; + else + return cdns_pcie_hpa_host_map_dma_ranges(rc); +} + +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) +{ + int err; + + err =3D cdns_pcie_hpa_host_init_root_port(rc); + if (err) + return err; + + return cdns_pcie_hpa_host_init_address_translation(rc); +} + +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D rc->pcie.dev; + int ret; + + if (rc->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); + + cdns_pcie_hpa_host_enable_ptm_response(pcie); + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret =3D cdns_pcie_host_start_link(rc); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + + return ret; +} + +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + struct device *dev =3D rc->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct pci_host_bridge *bridge; + enum cdns_pcie_rp_bar bar; + struct cdns_pcie *pcie; + struct resource *res; + int ret; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + pcie =3D &rc->pcie; + pcie->is_rc =3D true; + + if (!pcie->reg_base) { + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + } + + /* ECAM config space is remapped at glue layer */ + if (!rc->cfg_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + rc->cfg_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(rc->cfg_base)) + return PTR_ERR(rc->cfg_base); + rc->cfg_res =3D res; + } + + ret =3D cdns_pcie_hpa_host_link_setup(rc); + if (ret) + return ret; + + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) + rc->avail_ib_bar[bar] =3D true; + + ret =3D cdns_pcie_hpa_host_init(rc); + if (ret) + return ret; + + if (!bridge->ops) + bridge->ops =3D &cdns_pcie_hpa_host_ops; + + return pci_host_probe(bridge); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pc= i/controller/cadence/pcie-cadence-hpa.c new file mode 100644 index 000000000000..7982b40dcfe6 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_DBG_STS_REG0); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} + +int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val |=3D CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); + return 0; +} + +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val &=3D ~CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); +} + +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) +{ + u32 delay =3D 0x3; + u32 ltssm_control_cap; + + /* + * Set the LTSSM Detect Quiet state min. delay to 2ms. + */ + ltssm_control_cap =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0); + ltssm_control_cap =3D ((ltssm_control_cap & + ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); +} + +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size) +{ + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + u64 sz =3D 1ULL << fls64(size - 1); + int nbits =3D ilog2(sz); + u32 addr0, addr1, desc0, desc1, ctrl0; + + if (nbits < 8) + nbits =3D 8; + + /* Set the PCI address */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | + (lower_32_bits(pci_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(pci_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); + + /* Set the PCIe header descriptor */ + if (is_io) + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; + else + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * Whether Bit [26] is set or not inside DESC0 register of the outbound + * PCIe descriptor, the PCI function number must be set into + * Bits [31:24] of DESC1 anyway. + * + * In Root Complex mode, the function number is always 0 but in Endpoint + * mode, the PCIe controller may support more than one function. This + * function number needs to be set properly into the outbound PCIe + * descriptor. + * + * Besides, setting Bit [26] is mandatory when in Root Complex mode: + * then the driver must provide the bus, resp. device, number in + * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function + * number, the device number is always 0 in Root Complex mode. + * + * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence + * the PCIe controller will use the captured values for the bus and + * device numbers. + */ + if (pcie->is_rc) { + /* The device and function numbers are always 0. */ + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + /* + * Use captured values for bus and device numbers but still + * need to set the function number. + */ + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} + +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr) +{ + u32 addr0, addr1, desc0, desc1, ctrl0; + + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * See cdns_pcie_set_outbound_region() comments above. + */ + if (pcie->is_rc) { + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} + +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r) +{ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), 0); +} diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index e09f23427313..882c4aef7ac5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -12,8 +12,6 @@ #include #include "pcie-cadence.h" =20 -#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF - /** * struct cdns_plat_pcie - private data for this PCIe platform driver * @pcie: Cadence PCIe controller @@ -24,13 +22,8 @@ struct cdns_plat_pcie { =20 static const struct of_device_id cdns_plat_pcie_of_match[]; =20 -static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) -{ - return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; -} - static const struct cdns_pcie_ops cdns_plat_ops =3D { - .cpu_addr_fixup =3D cdns_plat_cpu_addr_fixup, + .link_up =3D cdns_pcie_linkup, }; =20 static int cdns_plat_pcie_probe(struct platform_device *pdev) @@ -68,6 +61,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) rc =3D pci_host_bridge_priv(bridge); rc->pcie.dev =3D dev; rc->pcie.ops =3D &cdns_plat_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offsets pointer */ + rc->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &rc->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); @@ -95,6 +93,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) =20 ep->pcie.dev =3D dev; ep->pcie.ops =3D &cdns_plat_ops; + ep->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offset pointer */ + ep->pcie.cdns_pcie_reg_offsets =3D data; + cdns_plat_pcie->pcie =3D &ep->pcie; =20 ret =3D cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 51c9bc4eb174..f86a44efc510 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -9,6 +9,16 @@ =20 #include "pcie-cadence.h" =20 +bool cdns_pcie_linkup(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay =3D 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 8048bef215d0..ee002f0d8a1b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -29,6 +29,26 @@ struct cdns_pcie_rp_ib_bar { struct cdns_pcie; struct cdns_pcie_rc; =20 +enum cdns_pcie_msg_routing { + /* Route to Root Complex */ + MSG_ROUTING_TO_RC, + + /* Use Address Routing */ + MSG_ROUTING_BY_ADDR, + + /* Use ID Routing */ + MSG_ROUTING_BY_ID, + + /* Route as Broadcast Message from Root Complex */ + MSG_ROUTING_BCAST, + + /* Local message; terminate at receiver (INTx messages) */ + MSG_ROUTING_LOCAL, + + /* Gather & route to Root Complex (PME_TO_Ack message) */ + MSG_ROUTING_GATHER, +}; + enum cdns_pcie_reg_bank { REG_BANK_RP, REG_BANK_IP_REG, @@ -43,9 +63,9 @@ enum cdns_pcie_reg_bank { }; =20 struct cdns_pcie_ops { - int (*start_link)(struct cdns_pcie *pcie); - void (*stop_link)(struct cdns_pcie *pcie); - bool (*link_up)(struct cdns_pcie *pcie); + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 @@ -77,6 +97,7 @@ struct cdns_plat_pcie_of_data { * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI ac= cesses + * @msg_res: Region for send message to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoi= nt. * @phy_count: number of supported PHY devices @@ -89,6 +110,7 @@ struct cdns_plat_pcie_of_data { struct cdns_pcie { void __iomem *reg_base; struct resource *mem_res; + struct resource *msg_res; struct device *dev; bool is_rc; int phy_count; @@ -111,6 +133,7 @@ struct cdns_pcie { * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_support_flag: Whether the ECAM flag is supported */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -121,6 +144,8 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; unsigned int quirk_retrain_flag:1; unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_support_flag:1; + unsigned int no_inbound_flag:1; }; =20 /** @@ -304,6 +329,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie = *pcie, u32 reg) return cdns_pcie_read_sz(addr, 0x2); } =20 +static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); +} + +static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, + u32 reg, u16 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); +} + +static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) @@ -368,6 +416,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); #else static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) { @@ -384,6 +433,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pci= e_rc *rc) return 0; } =20 +static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + return 0; +} + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) { } @@ -398,17 +452,25 @@ static inline void __iomem *cdns_pci_map_bus(struct p= ci_bus *bus, unsigned int d #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); #else static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) { return 0; } =20 +static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + return 0; +} + static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) { } #endif - +bool cdns_pcie_linkup(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, u32 r, bool is_io, @@ -421,6 +483,25 @@ void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); =20 +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size); +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr); +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r); +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); +int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc); + +int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie); +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie); +bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); + extern const struct dev_pm_ops cdns_pcie_pm_ops; =20 #endif /* _PCIE_CADENCE_H */ --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023118.outbound.protection.outlook.com [40.107.44.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46B5C274B36; Fri, 8 Aug 2025 07:29:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.118 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638187; cv=fail; b=pHcHkzcplrt5NU2StmdDrr/4g9ocZjVe7e9OtS04pBZdJHnjZsUvfyZnwN5EBK8af2YXahsCSL/k3XSefNhrYWuiYaD+dV4llyF7+jVLx/1CiywwBHe/fXeGkKas2E4aoWLy0mRn+hSXkFJ/40uhW/OmLwV/YxTC9qok/OKJtjg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638187; c=relaxed/simple; bh=3Dpjhv0CDATpofkzuwFYLCPacvPU+iTj+31f2ewK8r0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pKkZ+taZn2z/5SMJQtoCs4A769cmZ9NjjVwjNYo00BMRZtmGsHd5QZAzbsdxDSTC9D7XlUePHrrN8cOamFdNI0i5uPZL41tlY2vxYoqwDy9Gy64IRvEFah1Hph/ELK4cEomaQr7eIr8JeZWsD5uzRVAOGx2fY6TPb5aa9CHS71E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j7zdZWwNEZadJaMR132P7/mhHa2iZc8BGAGb84cp1/zUz+uXzfD+zD6gh5ShqO9lLF5HseL6AGtGReqfDohrzmSxQRTl9trnBc2JkHyKlR2FnJ8e/JCCWw8y87HDwFIAqihN0th0KwhdRqXhEYEB/4ntKPYg7kCkF0eM1SbiS60ZLLM4VZ0T+CNzZKk8g1UNcxV8dgLFPdr/71MySMwCQECPqzWvaRO6VaGE961VivZbRktspNhxb7TR5igtP2SNyMEOi4TrTjOtOnTjhWM8qoGlYUKZWiEm7oAXqE0lg3vmKl5rwQbvJULtNnOAfnycuYMikPE41k5I+v1mKRhYnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7oWY1ZeY8wffb3fZMVrjm0d+W4QBizzKrdcwJMlq2do=; b=LZp9bEz5fYbzUcTs8xCx74P83PNMywsH2wRyL6joM7/mGtbQV10z9dkrJiI5iA+vr9/79m9b98ULIO6boNUuBtBvkUlxVUYzgCBWsB9gDJ6j8mdp9rlnnJBbtExuFulgxOTpcUlwrR4iofIlFqxi9rE4IQqOZdFqMT7GFtVukkGBKnBnSAdc25hsYTTFKzP0P0FRjUkOUg4WzL4FPtnetX6XhSUn84jofJcqQ9j3Bjf7YDdcf9CfHVbHhrxhAsoGTJm1uP90+pYUPNnrBOFlYKcyAXPveE4cYrot52afRcXUw7q/QRzQEyYBW/1J8Z6uf0ZGbT+ttp57VZP+9fHX8A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TYAPR01CA0132.jpnprd01.prod.outlook.com (2603:1096:404:2d::24) by OS8PR06MB7323.apcprd06.prod.outlook.com (2603:1096:604:28a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.15; Fri, 8 Aug 2025 07:29:37 +0000 Received: from OSA0EPF000000C8.apcprd02.prod.outlook.com (2603:1096:404:2d:cafe::13) by TYAPR01CA0132.outlook.office365.com (2603:1096:404:2d::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C8.mail.protection.outlook.com (10.167.240.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 70B4841604E7; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 07/12] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings Date: Fri, 8 Aug 2025 15:29:24 +0800 Message-ID: <20250808072929.4090694-8-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C8:EE_|OS8PR06MB7323:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a76413e-2c56-44ad-9e69-08ddd64d5405 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OrvNv55IGZHjNFKqLtSJGEZfHmdxYI/z/ivsIy9104LSeSoS9lPZI3LuImGq?= =?us-ascii?Q?vw8rZ1mLN3ZB6NHKZW+LPHCaK66IRTo8f0OElO6svEonlRAGO9PA2wit1FWw?= =?us-ascii?Q?7HreA05j+cp8e5BLFWwRL758mmYdzMeRkqRN9mIGaGRmu1xIESUilvjc5jXf?= =?us-ascii?Q?GBOdfhIVXCMEpdXg0K5Ds5uXOrWQ3egN3B8EqMBuaqfszVWPLfGsSWoE+cR+?= =?us-ascii?Q?eoo1kZPIrVVQKKjRidpaW8AnFD+miq8UuUoQ3+YpPNxabsOOrSHlX8pyriST?= =?us-ascii?Q?1VUM9q9amZle4X49OIFf6yuXA8APtCIerBNpVJJIahWFYZQG4fsoXzDvzcGI?= =?us-ascii?Q?uPy7eaR6s3vuShG7YkQaIHUW+XvWHg5jYW5b0nhdinV+x3S30k/ug1Pxph2+?= =?us-ascii?Q?BkRZ2yNhipEastrUnKdkiODSoLVDTnzicnvwgpG5cJBMobGiJaUwFovvcwcj?= =?us-ascii?Q?u1wLn6rUVrXIBWFgM+OmdsvpGbKVCpfZyfdu+Edy8kiqXSl8mAQAMfWy5k5c?= =?us-ascii?Q?hVFbefe04OdZpMWuhu3rzMHjJIEg45GXaKt0m985dD1YDc7VVlvL/8quCRSt?= =?us-ascii?Q?CoaABh7IQdvFm36CROukxwHTN+B41Wj0oymZhOLxHOSE1a/46/79rKZz6gSq?= =?us-ascii?Q?gedTXPO6YLBSfvFqGlu9PlPFwjJPRjU4RAkvSEj69BGkG+frqrr/tYnmIy0B?= =?us-ascii?Q?xbl2gbpkKhHMBRj20KjCi3KmM+g8U3hMcA/2/Qjz4uK5st2dXhxV0UqOM+QC?= =?us-ascii?Q?9m4XU3TMZ2Jxm/imy1U7yN27umJx1TAAny4+Vurj9PXgbIlCGi3gCRDzfoh6?= =?us-ascii?Q?wRzxKiQNJ4ikCpuxnMqKdeN97wy4cndHZ7tU5S06a8gVdc0fsRZleq55Ywc2?= =?us-ascii?Q?J+K/1vtLpBxXBvQ74Nv2mgNCKa5xIck95advC12pZnaKnpDB7r9v8hzdPpt8?= =?us-ascii?Q?DRSTt1uANxpMGX4kdXjBNDkXX0JHSvd6YNarhFKNrsr/9iFIFyyO74AFR3cs?= =?us-ascii?Q?UAURzLVNRlGJdltSzG801bUCWmtZ78ZbrfLWcbM1MjC5ZAXDAMm2NFqSl3Z2?= =?us-ascii?Q?OCPaup94UzLnZEgQ18cK+VMpv9iMyyvYTfwuubO1qShl8tapjxfGLbS09b9R?= =?us-ascii?Q?V0EV8g/TOa3Z90LZQUHNDctuofKPar8F9O8B2aEdVihaouyk/Z4cS2/vruds?= =?us-ascii?Q?HVQ1Q/n1RYzV7zV2rH7y+ZDtA/TM5so2s5VSuThGQ2jjTKwRPNAwBpF+FQbb?= =?us-ascii?Q?aelSXzVAgei7bnpMsAlK+IrfecIZgU/G/HA4+Nc5T8w8A3sapy4SG31h+y1P?= =?us-ascii?Q?q+R9jb7YuYMrzh7JrK5yosiyVu3JTvYijXKXDCV0mWHaTRQbfBRa++zZX1Z/?= =?us-ascii?Q?XZjyJoZ78yLJpjjiyPat3Ul1AvB5Whn31iY0DA/6CEXWO+j2eAw8J3ra7tlE?= =?us-ascii?Q?nt56M1cgqB20SXWRyEq5QfyXt1PSxrrJ8dZT/y0BvrEsdEHsQfPQmg=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.4848 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a76413e-2c56-44ad-9e69-08ddd64d5405 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS8PR06MB7323 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Document the bindings for CIX Sky1 PCIe Controller configured in root complex mode with five root port. Supports 4 INTx, MSI and MSI-x interrupts from the ARM GICv3 controller. Signed-off-by: Hans Zhang --- .../bindings/pci/cix,sky1-pcie-host.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cix,sky1-pcie-hos= t.yaml diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml = b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 000000000000..5aef69ac14b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + oneOf: + - const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: ECAM registers. + - description: Remote CIX System Unit registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: cfg + - const: rcsu + - const: msg + +required: + - compatible + - ranges + - bus-range + - device_type + - interrupt-map + - interrupt-map-mask + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x0010= 0000>, + <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe000= 00>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x000000= 00>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIG= H 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH = 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH = 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH = 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + }; --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023118.outbound.protection.outlook.com [40.107.44.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DAD1274B4F; Fri, 8 Aug 2025 07:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.118 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638187; cv=fail; b=Kuhbekh2UrmvafZ4QKWiC/hNwFZQjBSPbXDmB+xvmJxPFm9zgHrWboVIQbyV9g6LesNCyfIa57ta/dwTqZwIjcs9s5oCjR2cR9u6ODN34hYlAKnTwnaLDIkEQ84zJ+20JX+Qx0ibiIOLFbXUyz4znUfeD8lNqiHPfpqdGba3o9E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638187; c=relaxed/simple; bh=G5eOl/Xm3GP9bTaLZSi9myToHoyTJVqJ7DYrdSEslFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IxmeTK+IOOmbSbiAZn/96T/NWf0mRjS2v1s84zepU71tw8q1rEs0dwnPORX1YTPsO+xLa7djbuz0iDdXAD+zV2dfQtJLf+bAJE+piBGQR+v1RAWomCB3gvm3Mrc5uaxm62hF+gcZP9xS7VkxE1yTyVFJO/Tygrc2lfHu0+lub1g= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=O7IlKJ1nU7RQifJeLjDLNf5N2DuoKDQ27qDgyxRGrcCo0L8TKIRZXVclkOaMTTrpzvCcfN0fCsJRNsrStLNIA29cmtIMsq5IyOnpM+gDLow5ReyJ1BADKI/zZbV+G57yGW901ls/K8tFh1c83MmGGp41S+6pITivosP/tyU5tEV37HiQaEcyW0fSm5ENoJJYpHTn7jPKDA5+EMokTPjOo5DFj0fkkb25PgMWJmNptcvniENbY+fRxnclnTJiyzWRP/CfE3xZn0aDHc/TYqSkk0OzAJJuFh8HTT9Lt6bbZoMKrEn6JZqMPLrsYDvy8JEMN0u/ZDjmqZ6BZjrkE01zqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=G8BToPZxjTD4L5jPzzFAljpwlBxu60t0OjqLNMwJZRo=; b=rPGwV5zsiHZbbnJX+CRsjWrQxCFYIDQ2uVPc4wQuu+zMfd/G0UFbwtnMtufsQRP64qpVrATwn4A5alcdmtUOXjb/c+HE9d5Ko0xD0f3YcjVtH9j5w32F4/3IeySqDXQuygbf2w4p8Py6tTQ49l3hYi8pl78ZQdeAAKt3Jd2Fom/ws3Y6N01cq1jikO4QJLswL02Fl80RCvPPjoo8MvbN9Q4KcCWyWx6XiHgXMiebLm9n0STKE/2YIlFJ66iY4yRv7r6rWVhXU+HB1Y2mGITVJ0CfEmgEnBc3q1nuJuggXYQHyrfYBrETmDnD0Qh3aP1ChcTVgotcEShP9zyZtywKMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SI2PR04CA0018.apcprd04.prod.outlook.com (2603:1096:4:197::9) by TYSPR06MB7298.apcprd06.prod.outlook.com (2603:1096:405:95::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:38 +0000 Received: from SG2PEPF000B66CE.apcprd03.prod.outlook.com (2603:1096:4:197:cafe::12) by SI2PR04CA0018.outlook.office365.com (2603:1096:4:197::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.15 via Frontend Transport; Fri, 8 Aug 2025 07:29:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CE.mail.protection.outlook.com (10.167.240.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:35 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 80ED341604EB; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 08/12] PCI: Add Cix Technology Vendor and Device ID Date: Fri, 8 Aug 2025 15:29:25 +0800 Message-ID: <20250808072929.4090694-9-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CE:EE_|TYSPR06MB7298:EE_ X-MS-Office365-Filtering-Correlation-Id: b95a6e39-a0f6-431c-f21c-08ddd64d53a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yhb31YvH0aedVX6J1CuEwKv9NFhYfKjYyH8hQHhpHXDsLEje1ubv/2L7mULL?= =?us-ascii?Q?vI2nr7uAYXCEvlO7AYZaFN+4k/Be8aSM8MAjWTEHZz8lMmzQjewed1LQbTCA?= =?us-ascii?Q?a+1Vnd/SfGMbvBOQI6Qj1u5qtbRmHMlyDI1QPHo2q7K4huqAO/6eOHSH8e+I?= =?us-ascii?Q?obXv33F2YsmHkWHO61tHmdCq1x2ncqLn5CWKb2bVMWY2gS+AFk/our/QrwTx?= =?us-ascii?Q?+0TC//DPU1zKg022IAgknD7ex+d6CNeEVyIyiKJFiwBYuYyUAZklC2kDa6Zd?= =?us-ascii?Q?zSiI0CZFpY81tc9O5uHAELD5edW+GNCF7364GuXBtZdjcl2VFdOJA5WFa7H/?= =?us-ascii?Q?+Q93cVjTH2hlEOR7GgAdlq2PXX1zgaCKcsgcbsDaSXbbpnMLgrW3D14QkHzV?= =?us-ascii?Q?yg7VdzZhH7licn31QL+wn3Xu4PcGDmEXO990b5Ubkk4nTNckU2WU1+MXB/yx?= =?us-ascii?Q?y/uP9Ynq8GPWMrAS87y7fqphwlB2dkkT6dh3U/xRM9epc1No11IYWb9W3kz0?= =?us-ascii?Q?RPSnn4n5KQSXs0FqvJONE5dsZVLU03xtoHuid3a6WaAv27awqDCODe0Xu5oD?= =?us-ascii?Q?+MhvSKPwYgpAspmm6l1jtqPsxIaQCh8Ntas3fg/qvQi/hcbrkNIEChcsW7nC?= =?us-ascii?Q?yqI8aXAtV5bizjlK1XN1W99O/3cmbB3WHGA8OVsKa1laFRNZov6MPt8BxHPK?= =?us-ascii?Q?grCjSRQlaaZSGJskVgmKoUbxFNd38tndFFZDzlEvTfU4YyFgT5mfbP4zbFLi?= =?us-ascii?Q?Pam3tEvSCK376D1HF9Gh8VwVCoQGrEBV3ADtvPxESYyggH2jGnqTCTg1Kf4L?= =?us-ascii?Q?2LycVO/N6kdJhmiMyxRCtpkah92UjSzY9YDrQOVv7hhvqsu5sp49ZMiIE6/M?= =?us-ascii?Q?lolHP8DWLHb2g6Qt/0BXcBoxnYQKefMr2jN1DOFW6yw4ieLci0PfqV9o1yfX?= =?us-ascii?Q?z0MktyzlocfPPMGUujyVfnu/aaQ6vMODz5XnG4LxNgdSmjWaVmkGLbSYCqZP?= =?us-ascii?Q?SlkR+X6rBsXDGwmUF252wIn+hsMRNcaytowjvKo+d2ubISDWj2CCI+omx8Fi?= =?us-ascii?Q?by7+U2bmOJy9CyPD3p/1SwMeHblqMlJyeYPcS6/JUvK3ZtIBGQA4CkrspK4t?= =?us-ascii?Q?cyjMTFpmpb9tmvt++KUv0721DdmE40I+nsl61oXVPK4CZZZlGWFLxOnxlt4/?= =?us-ascii?Q?ytqDBuMDQ5ATXXyPNrhWl7GHGqnMqv5deLmkZRXpWbGNoH7cXV0OAdvQ5Wy6?= =?us-ascii?Q?hkx4z5ePXHtv950tktSIyB+Dtp+b9JGm5q4EqlmMGXB+733vV2ZQghZCKe8Q?= =?us-ascii?Q?1iUoUgnunwzv1IQCO2WLEqQQ9XQ4EBTfjRlw0o1Mzvl4pklUVVdnEC02f+qa?= =?us-ascii?Q?FDKyvPIFrnzW3sa/Wu4YRHtSMzAvqNn8wAE3AIpNopvPbp0YnBOjJUI4/1V2?= =?us-ascii?Q?v/V5bJX273dC29d6l90wfrYaHEmr7W/cpz7FfOKCOGe0YlSEg5GPciCRAqT1?= =?us-ascii?Q?C1C9i1wfms7RlvXdHwb86krOrKa3BzDz7AYS?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:35.9093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b95a6e39-a0f6-431c-f21c-08ddd64d53a9 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CE.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB7298 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add Cixtech P1 (internal name sky1) as a vendor and device ID for PCI devices. This ID will be used by the CIX Sky1 PCIe host controller driver. Signed-off-by: Hans Zhang --- include/linux/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 92ffc4373f6d..24b04d085920 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2631,6 +2631,9 @@ =20 #define PCI_VENDOR_ID_CXL 0x1e98 =20 +#define PCI_VENDOR_ID_CIX 0x1f6c +#define PCI_DEVICE_ID_CIX_SKY1 0x0001 + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from TYPPR03CU001.outbound.protection.outlook.com (mail-japaneastazon11022133.outbound.protection.outlook.com [52.101.126.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F12A23BCF3; Fri, 8 Aug 2025 07:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.126.133 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638183; cv=fail; b=RqAJG2QdIIWqhHPWh5O9y4YvzNRSl8Dv47YQ4OtKHid/5JY3zX5U6sppA65EjaLwTSRPGl9jJj3D6kRYuI2NmbWFvDnljQyAB4TPWGToS0TqDMymuuoR2gZtppaqUEdVKlnHmJ1byMWOjJwUrzMC6Renokw1VtSo8CHW6qwjS+o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638183; c=relaxed/simple; bh=n+p5K9xZBkIg0LprP+KO3+LWcRCWNTVMpKGnakFLFa0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T5uGxViO4WvpF3QJwOjWCPLGpDcJiFYBkNGrHIODWeQd/vN1XHZnn43dUdJNmc0B7EESjxLzH4O114xplFrhwDOCZNKdEc4Azes57bdaztx8SaB3QATU7xzORqJul2xx1PdbI99xA/meK9JSKtNS6VWEQrk8nMYZNIYcGYQV/v4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.126.133 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KnppBnlTPvmblon4Su8oRp+gJzVN/JL3KaXLggjXg0pTRbK3966LZBHftaDn2vvsDJqNP6XBHh/sBXyfjOJUCmNVOoWPEoK32nIlpTSSzKhMRnQm8OzyA4cj8uSEnaRWkNeRjrSNc1ZMw0rMv9O7MHOw+2p9vrShy5NW6sUALNTrthHSnOQ8N4vhifyhO7oj11/PMzKUyIYUfIk28LMXkTaXCXs0y4bGgnboHKh5eEQPu/XU0AIeUemzBZsiXn7lntPZbPtFP1SfiFDMUmbkMo7mFKN2aAIzNbw9knWckzhg5X4wIrqsNGAfQgnGb2JlrrMerh6X+1bCuB23VYdGYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JOYyEUsbYuZACLAgTS1s/upq1lcvPWv9zXckizdwNwY=; b=BJGozPwKwZEmxKtzfj37KNozNt5afzCUHQmkAq2zlcMaaPnzJ8a8+GZbPA8t030AH+37nDBlRVh7ErqZTMnM+W5j3io7OYiCD1Id3ZrHjY9wbdOuIs14Jl8EUs+5TOTcNIhGmqoOq2NOdrVi9SX/SXxITW9KVqQh/SSNugG8RVsSblrzVvx7/Uuo8zz9gHhUL96gLdDlIG+SM4YZi7IQECKdiQvRF7vOUkl4NDYPBM4+Ax301emZ1h3X27UXKOczCyUGIPiUem9HP/jxWszy7YKUX5dlZUqA3pwCVd0MJRwTZ0WPERNCTIzaiQ5Z5o+3Th3gWLDc1DTArNeLhmcSew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SGXP274CA0015.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::27) by PS1PPF3AA5DA295.apcprd06.prod.outlook.com (2603:1096:308::24b) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.14; Fri, 8 Aug 2025 07:29:37 +0000 Received: from SG2PEPF000B66D0.apcprd03.prod.outlook.com (2603:1096:4:b8:cafe::ea) by SGXP274CA0015.outlook.office365.com (2603:1096:4:b8::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.16 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66D0.mail.protection.outlook.com (10.167.240.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 912714160508; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 09/12] PCI: sky1: Add PCIe host support for CIX Sky1 Date: Fri, 8 Aug 2025 15:29:26 +0800 Message-ID: <20250808072929.4090694-10-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66D0:EE_|PS1PPF3AA5DA295:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f6dab27-c15a-45a2-35e2-08ddd64d53c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?XrAP3hfsRjeLLWDxOQwo74dPKFLEO/czC8ZHuu36NLO7Sr1GezmgneBNdA8n?= =?us-ascii?Q?9owNG0bJyRRV4HaZFxdu7CKhgymxSCFbCu6ElxcWKFH6FOLbFmfbx9OWmlRf?= =?us-ascii?Q?ziG1JpxEJFG5o6PXS9Ed4Aol81IHi/ZZ9S563Ve6dIFTBI76x+VE1iOr+rgG?= =?us-ascii?Q?2XoJlgSzR7SAqf6GpFcGht/1DWNtJ0+UgaYy9yup2jicesazHuqon4V9uppE?= =?us-ascii?Q?JzKDHtVQtIOL485V/FgfKornCyxz+OuvdnaFD1onSMjeQCeiGGNL0nV6nxYv?= =?us-ascii?Q?Lq0Sni4vXj67FpuDqlS8BMf5QBP3pTHIvJjjsxF/yDPg7FS65UfYqUPiBh5t?= =?us-ascii?Q?T7sjdSmdDIbW5OVEl6YhNctJh7lFFwcTAd2ucPlD3nOfs3aqdpKp4jt0X6w7?= =?us-ascii?Q?8tgfHmPQsK05s80p0BaibuoKakRuLYOTzGqAn/y4FPkYdi7jieANrgeNCHq2?= =?us-ascii?Q?MV15mUDZoryjZqpJKZ9jj37O8m2bLCAFN7Eu54ADYFrYXgPKXNttJsRQWdqh?= =?us-ascii?Q?2Da3p2IgM+KJO0O0bhxE3X6uvelIDODT50qCd34l4ZQR7A2fYA9LQMVAYbbI?= =?us-ascii?Q?8fZ8gEd0OUg8vuuxLT2W1EvKW+Mw9TeFz+hJpTaymoPkN4rnfohB6qa1vR0b?= =?us-ascii?Q?s4PbcFLD+BUnlhmRgZCg7+KztsN6BKYESpko56YGhmrRbqM++UnZumj4VvFq?= =?us-ascii?Q?niXST8hEy2FC/RsV96AHwaG6OynQKkLmpdTSdkpTXwDP7lzrY3Wvpg0kFbbv?= =?us-ascii?Q?CleC5vcCvBLsRxC9bV6UKw2hlNgayl3BPAiF2kmkdT6HUmkSRAA8h8WVqW0n?= =?us-ascii?Q?xBtE2QUiOxFZgKyh2UZaWC5WkvTXtXhH3lufiNsza9I+vkBjUHgeTrOAQ7d4?= =?us-ascii?Q?l1O+QJ5/6sm5/qbqCpBG7aePWIJ6WdGaa1tjHtTJryxKnHx/sc+wVa8h4C0v?= =?us-ascii?Q?eJdn++Ubiao24mGoMetRYFjBhqgtVrLW5Zhh4MZRTs3Vz2Rvoj62dnyLetvS?= =?us-ascii?Q?FoZkFxmhCJGzD5GH9+FcLKah88ShAvLxBT53oTld9UdPPAzKI+7oI+uetr93?= =?us-ascii?Q?rjvDf7MqIPcFsdKR+M2YdEfV4+2EVgzal0YpWGjSlhlcQf+6VE5pQnPj1mXP?= =?us-ascii?Q?HH3IkQV0tZD2yKeV16jKC5YjIT0YQB/pgbr8kOKuHM9Pt2nfzkp8T8FTP816?= =?us-ascii?Q?JUu4FBjb9/p5gbDQRiRsIp0h8SiC3OashQUXJ+1Kew9mKoWwFMqP3fBMQP1h?= =?us-ascii?Q?BRGvjJh6FZ5mqgfD3CYN565f6cPoqW6GmWJv4moTc8pd4RaKT/92kM2695ar?= =?us-ascii?Q?7GO87mz5WiOusSwugykNooJhLI5ezphYRXrOmnpb81KI7CzfFyYQr4BHdykJ?= =?us-ascii?Q?mfXpCP700pmcOYvmOcdNV14x3XpDdNQDTijz+S4blxWkQRnTPjjGTd+8kdfy?= =?us-ascii?Q?4B/VDMWPfOrx+TvoA6/dPZK0du58T+gj7IGkhxbCIu1Ca7Qtn814MtdZrkR5?= =?us-ascii?Q?AOdifRpabpf8qR2WSKBjJkQTGL+0r7yfkjp/?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.0933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f6dab27-c15a-45a2-35e2-08ddd64d53c6 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66D0.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PS1PPF3AA5DA295 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence PCIe core. Supports MSI/MSI-x via GICv3, Single Virtual Channel, Single Function. Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 12 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-sky1.c | 292 ++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/pci/controller/cadence/pci-sky1.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index a1caf154888d..be52f31c5371 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -75,4 +75,16 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + +config PCI_SKY1_HOST + tristate "CIX SKY1 PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the CIX SKY1 PCIe platform + controller in host mode. CIX SKY1 PCIe controller uses Cadence HPA(High + Performance Architecture IP[Second generation of cadence PCIe IP]) + + This driver requires Cadence PCIe core infrastructure (PCIE_CADENCE_HOS= T) + and hardware platform adaptation layer to function. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e2df24ff4c33..c8af7486036b 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o pc= ie-cadence-host-hpa.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o pcie-cadence-ep-hpa.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o +obj-$(CONFIG_PCI_SKY1_HOST) +=3D pci-sky1.o diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c new file mode 100644 index 000000000000..290bff8bf151 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe controller driver for CIX's sky1 SoCs + * + * Author: Hans Zhang + */ + +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define STRAP_REG(n) ((n) * 0x04) +#define STATUS_REG(n) ((n) * 0x04) + +#define RCSU_STRAP_REG 0x300 +#define RCSU_STATUS_REG 0x400 + +#define SKY1_IP_REG_BANK_OFFSET 0x1000 +#define SKY1_IP_CFG_CTRL_REG_BANK_OFFSET 0x4c00 +#define SKY1_IP_AXI_MASTER_COMMON_OFFSET 0xf000 +#define SKY1_AXI_SLAVE_OFFSET 0x9000 +#define SKY1_AXI_MASTER_OFFSET 0xb000 +#define SKY1_AXI_HLS_REGISTERS_OFFSET 0xc000 +#define SKY1_AXI_RAS_REGISTERS_OFFSET 0xe000 +#define SKY1_DTI_REGISTERS_OFFSET 0xd000 + +#define IP_REG_I_DBG_STS_0 0x420 + +#define LINK_TRAINING_ENABLE BIT(0) +#define LINK_COMPLETE BIT(0) + +enum cix_soc_type { + CIX_SKY1, +}; + +struct sky1_pcie_data { + struct cdns_plat_pcie_of_data reg_off; + enum cix_soc_type soc_type; +}; + +struct sky1_pcie { + struct device *dev; + const struct sky1_pcie_data *data; + struct cdns_pcie *cdns_pcie; + struct cdns_pcie_rc *cdns_pcie_rc; + + struct resource *cfg_res; + struct resource *msg_res; + struct pci_config_window *cfg; + void __iomem *rcsu_base; + void __iomem *strap_base; + void __iomem *status_base; + void __iomem *reg_base; + void __iomem *cfg_base; + void __iomem *msg_base; +}; + +static void sky1_pcie_clear_and_set_dword(void __iomem *addr, u32 clear, + u32 set) +{ + u32 val; + + val =3D readl(addr); + val &=3D ~clear; + val |=3D set; + writel(val, addr); +} + +static void sky1_pcie_init_bases(struct sky1_pcie *pcie) +{ + pcie->strap_base =3D pcie->rcsu_base + RCSU_STRAP_REG; + pcie->status_base =3D pcie->rcsu_base + RCSU_STATUS_REG; +} + +static int sky1_pcie_parse_mem(struct sky1_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct resource *res; + void __iomem *base; + int ret =3D 0; + + base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(base)) { + dev_err(dev, "Parse \"reg\" resource err\n"); + return PTR_ERR(base); + } + pcie->reg_base =3D base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (!res) { + dev_err(dev, "Parse \"cfg\" resource err\n"); + return -ENXIO; + } + pcie->cfg_res =3D res; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcsu"); + if (!res) { + dev_err(dev, "Parse \"rcsu\" resource err\n"); + return -ENXIO; + } + pcie->rcsu_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->rcsu_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); + if (!res) { + dev_err(dev, "Parse \"msg\" resource err\n"); + return -ENXIO; + } + pcie->msg_res =3D res; + pcie->msg_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!pcie->msg_base) { + dev_err(dev, "ioremap failed for resource %pR\n", res); + return -ENOMEM; + } + + return ret; +} + +static int sky1_pcie_parse_property(struct platform_device *pdev, + struct sky1_pcie *pcie) +{ + int ret =3D 0; + + ret =3D sky1_pcie_parse_mem(pcie); + if (ret < 0) + return ret; + + sky1_pcie_init_bases(pcie); + + return ret; +} + +static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + 0, LINK_TRAINING_ENABLE); + + return 0; +} + +static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + + sky1_pcie_clear_and_set_dword(pcie->strap_base + STRAP_REG(1), + LINK_TRAINING_ENABLE, 0); +} + + +static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG, + IP_REG_I_DBG_STS_0); + return val & LINK_COMPLETE; +} + +static const struct cdns_pcie_ops sky1_pcie_ops =3D { + .start_link =3D sky1_pcie_start_link, + .stop_link =3D sky1_pcie_stop_link, + .link_up =3D sky1_pcie_link_up, +}; + +static int sky1_pcie_probe(struct platform_device *pdev) +{ + const struct sky1_pcie_data *data; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *cdns_pcie; + struct resource_entry *bus; + struct cdns_pcie_rc *rc; + struct sky1_pcie *pcie; + int ret; + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + pcie->data =3D data; + pcie->dev =3D dev; + dev_set_drvdata(dev, pcie); + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + ret =3D sky1_pcie_parse_property(pdev, pcie); + if (ret < 0) + return -ENXIO; + + pcie->cfg =3D pci_ecam_create(dev, pcie->cfg_res, bus->res, + &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) + return PTR_ERR(pcie->cfg); + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + rc =3D pci_host_bridge_priv(bridge); + rc->ecam_support_flag =3D 1; + rc->cfg_base =3D pcie->cfg->win; + rc->cfg_res =3D &pcie->cfg->res; + + cdns_pcie =3D &rc->pcie; + cdns_pcie->dev =3D dev; + cdns_pcie->ops =3D &sky1_pcie_ops; + cdns_pcie->reg_base =3D pcie->reg_base; + cdns_pcie->msg_res =3D pcie->msg_res; + cdns_pcie->cdns_pcie_reg_offsets =3D &data->reg_off; + cdns_pcie->is_rc =3D data->reg_off.is_rc; + + pcie->cdns_pcie =3D cdns_pcie; + pcie->cdns_pcie_rc =3D rc; + pcie->cfg_base =3D rc->cfg_base; + bridge->sysdata =3D pcie->cfg; + + if (data->soc_type =3D=3D CIX_SKY1) { + rc->vendor_id =3D PCI_VENDOR_ID_CIX; + rc->device_id =3D PCI_DEVICE_ID_CIX_SKY1; + rc->no_inbound_flag =3D 1; + } + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret < 0) { + pci_ecam_free(pcie->cfg); + return ret; + } + + return 0; +} + +static const struct sky1_pcie_data sky1_pcie_rc_data =3D { + .reg_off =3D { + .is_rc =3D true, + .ip_reg_bank_offset =3D SKY1_IP_REG_BANK_OFFSET, + .ip_cfg_ctrl_reg_offset =3D SKY1_IP_CFG_CTRL_REG_BANK_OFFSET, + .axi_mstr_common_offset =3D SKY1_IP_AXI_MASTER_COMMON_OFFSET, + .axi_slave_offset =3D SKY1_AXI_SLAVE_OFFSET, + .axi_master_offset =3D SKY1_AXI_MASTER_OFFSET, + .axi_hls_offset =3D SKY1_AXI_HLS_REGISTERS_OFFSET, + .axi_ras_offset =3D SKY1_AXI_RAS_REGISTERS_OFFSET, + .axi_dti_offset =3D SKY1_DTI_REGISTERS_OFFSET, + }, + .soc_type =3D CIX_SKY1, +}; + +static const struct of_device_id of_sky1_pcie_match[] =3D { + { + .compatible =3D "cix,sky1-pcie-host", + .data =3D &sky1_pcie_rc_data, + }, + {}, +}; + +static void sky1_pcie_remove(struct platform_device *pdev) +{ + struct sky1_pcie *pcie =3D platform_get_drvdata(pdev); + + pci_ecam_free(pcie->cfg); +} + +static struct platform_driver sky1_pcie_driver =3D { + .probe =3D sky1_pcie_probe, + .remove =3D sky1_pcie_remove, + .driver =3D { + .name =3D "sky1-pcie", + .of_match_table =3D of_sky1_pcie_match, + }, +}; +module_platform_driver(sky1_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCIe controller driver for CIX's sky1 SoCs"); +MODULE_AUTHOR("Hans Zhang "); --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023112.outbound.protection.outlook.com [52.101.127.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1900236435; Fri, 8 Aug 2025 07:29:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.127.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; cv=fail; b=nVvmc8C5nksh/xxn6+gZs7xAJ7MHN0Kb5xFeMw+edR13Eqh9o0cyAdqKk//TuMeuaKVBvNe2i1IRNB6iuUYy8mpx0yOGydTH28cfRyiRFYysTZbXMxQfTENzwR9ZZtGYrMIoGYyGoQ1juYaf7v6PGLWNXJr7yiWmCnIe69t4sm4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638182; c=relaxed/simple; bh=sl7/VabDxpHGsJdbr1d/h3Rhe8ob4l84qjtjnRrrR1Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DPzmbJYNHSA0f5AJ+tqbN39qvKA71f1D51EkPEydxY1hwH9KGSvZdtXpVAkHQBxZU0ZijDdVIi68yEMpUxYivNkXd06uhBVG18NS31d8x+gkRtGLH9IO0yZJk4rH93K9gBSLXIK+93388vKZBY09RGFG2nhlE7GMQOMKAFatXqw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.127.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fFM+yWOdR3UkqLwuXPBlgjfGD6XK7v07FnCuAVi9ZN4MCB8phvEKgawNKqmpdJ27E0hP9buwjbtzlR/teh6mOOzcNfQzGU8wWhKyGT4N9+wKVz5ZpztlIj431oO7iE7gaDucoiMcfw3Jh2/E1BwG4rsNANOGebWJGesRLwYIOZggmURmL3dUSaQKSbbS3q29F1+n+jciGnYgysJYUH7dA8jL2Rc9UuuJF9byufz1F/8EioPzSUMWznoq5EsdpeLSuM7KEwOVSmviKjSUKk/nAoF6bu91d97XzdFEVJZI6V5hbD+IRZxxia9PAmjWiSIoA5kB0mK9f5eqLv142U9QHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rOcYy8CSvCRKl/kPo7gnSb4Du3AmwoR5HWuzhkGaiwg=; b=rtdmkAv6ATsIlv/dOPx3q8Tcq118DsxHvESDzusT0UDx2wQDPnSzd6BjPwWL/wQI/aXZMl3PtkxN4Qlu98RmpTOHM2NTBbvh+arZUIVn442Z53nquV97E33scyilIQviOiVHLCqYONfP8zOjV4uP0ZjsjYylowB/cmx1e0sIkrIJ6ismvKvFZ/ImUiMt6L1juLwLJwXwcEnja/mrc5uyGCTca3nNMXoIySqG1NGCU5dKeRiG2tEc2UyE2h7/ItE6xEujUral8xK48jOlAtkfUTG0vS4h4nDCYlEDEwmhKlAXSFDyznzQzpeFtqZH3J9WalF/wi77PIgmT0oOgKdiww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SG2PR02CA0036.apcprd02.prod.outlook.com (2603:1096:3:18::24) by TYUPR06MB5946.apcprd06.prod.outlook.com (2603:1096:400:347::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:36 +0000 Received: from SG2PEPF000B66CA.apcprd03.prod.outlook.com (2603:1096:3:18:cafe::c6) by SG2PR02CA0036.outlook.office365.com (2603:1096:3:18::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.15 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CA.mail.protection.outlook.com (10.167.240.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 97F964160509; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 10/12] MAINTAINERS: add entry for CIX Sky1 PCIe driver Date: Fri, 8 Aug 2025 15:29:27 +0800 Message-ID: <20250808072929.4090694-11-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|TYUPR06MB5946:EE_ X-MS-Office365-Filtering-Correlation-Id: 22ccb7bf-d985-42f9-23e5-08ddd64d53c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qlTYVixLBQRXIXO7wKvdokPuXbGEEQwAFtz2boYdpIvQ2YDU2ciDI/QoAQAE?= =?us-ascii?Q?6eP1o0jhaz6CLzJSSlBOwGWekKgN0YNjgNFZNmZk4b79+T+8CSqmRSxJoyd/?= =?us-ascii?Q?C1NtPYgLhLuCdE7peLO9z4nJKDe+73fvAdQmq7XHViXv/Xv54JWOoyIhTXgQ?= =?us-ascii?Q?7CBbvXuPtGsDGLFpPtnOxF5t8pWHd+Y1ibvgIc1YEfTqKqKOXl1etKWSZxh5?= =?us-ascii?Q?hEXf6e9J+uTAalit3Gvj1q1ARWMiDba/r+G7lg2OQZfPrY6P2f2fLKdKDmnH?= =?us-ascii?Q?6nnO8LIvS5v2eiYJBhUWIrVpr85k8csCca07IhyD3hx6qarB7g0KnRelfhTP?= =?us-ascii?Q?ZXRPVM7RrdaUR0ufz/PxkMpXHdN/100qIjUPKeG+qjyhsBRXZkKkxSPkdNZO?= =?us-ascii?Q?OTRlhHLT4CBSwrUVTUdii6bulMsbV6Z0tEHCHHle29z170QqknZWEK5WpD8f?= =?us-ascii?Q?EGXRnZIJzXDy0fO3rFUpHDEwTEz+yO5ptT/yUONLrlBKG/oCtR4J07REIXMi?= =?us-ascii?Q?Vn8AfVzynWIvkZFiyulGbooF1tqaQxT+6Wyn2Y01LkJYGtyEddC0+Fp18KmF?= =?us-ascii?Q?J3MrD2TfbHOHbpduNXnwlVfvjRUyO49vdBjZNzgFcI4SJ3bleLShLiuDBgiC?= =?us-ascii?Q?5sDLe1+qzRhMblQXDzULw2ri1jz6v5+NuXHQqjYrSOp9tDfCBD5Ig+BoZxfR?= =?us-ascii?Q?1BOvUYadiLgTcZHezymysWQ4Qoii2hQi3xAAUFSK4Dczp24wx9NmS4iWhN+5?= =?us-ascii?Q?jANfi7CDgYGLepS9jMQAcTQaAUrMhvxNBLlVdDvoxFcYz8x/5iRw5SzjG2pL?= =?us-ascii?Q?VZBYa4W+0VRlzkp4C6Za7+Qj1vKIy360WJ+B89gZkWA9F3M/CAIQRDdz5AlU?= =?us-ascii?Q?3QuQyvClTB3APQFO9PxVRl4yhn6R+FC5xppmnZG2E08PIoIVa82mmDMXMqR8?= =?us-ascii?Q?BvDk0cjhmOyPwfYAO4TLlKqC0UaQrorja5i2t/C1xnvRz1mWv1ZiBdqcpkZt?= =?us-ascii?Q?cMkyN1Nt955d5vqsIXc01qvpIQgIwTArZN3U0O89oNflF06xpNeQlq1S5+bL?= =?us-ascii?Q?4JX9SQtxzum6N/GSb9ptEzbeAP4taISy5o1s6OVsvif3CD9ct9oBbhqiedkX?= =?us-ascii?Q?JSOFvDJqh3ND36fUpwWfgB85uux97F9fYd+R8FOK0j53LIMz84uQhAlW1dKG?= =?us-ascii?Q?w1DX8mh/+XVmsARI0ljGgsUWuKRoN1ZxCjYaxNE0o5/7FP++i7D/g3jdL4ZN?= =?us-ascii?Q?iXiSilB21VvE2G5BXoCN4EzOmtG80SVoIa8doiwoA1xAWGBdcLcQQ9jkuWcf?= =?us-ascii?Q?wnT6NTXxFMrnPt1IhmzsX32Ij1n1eQn1E6Lm6pXyO9alf2GqwayTAYGqbC3P?= =?us-ascii?Q?z+0AsGd9NMbhknwNyBRGs/09Vr21Fo3gsWfeyluEvCtSs5hJmhwIaUeenfpi?= =?us-ascii?Q?RxC81TC8oPSv3h+rzc+4Wfsvg/3vn6mX1dLovgX1Ln8W4RGqfV4cud3XwVcn?= =?us-ascii?Q?afNYPPY4jyLpDL+bOAgZ0gi76d1//5rdKMKp?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.0869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22ccb7bf-d985-42f9-23e5-08ddd64d53c5 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYUPR06MB5946 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add myself as maintainer of Sky1 PCIe host driver Signed-off-by: Hans Zhang --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bd62ad58a47f..9cd32ea6d60d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19253,6 +19253,13 @@ S: Orphan F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/cadence/*cadence* =20 +PCI DRIVER FOR CIX Sky1 +M: Hans Zhang +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml +F: drivers/pci/controller/cadence/*sky1* + PCI DRIVER FOR FREESCALE LAYERSCAPE M: Minghuan Lian M: Mingkai Hu --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from TYPPR03CU001.outbound.protection.outlook.com (mail-japaneastazon11022121.outbound.protection.outlook.com [52.101.126.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91E54276020; Fri, 8 Aug 2025 07:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.126.121 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638194; cv=fail; b=Es9VMfgvKHqM+wJkVd5GTgCQ+kivrkE7dMjCNDRVF5uJOVTFHSTFILEMWqzL6YIWDe5JoY/dQkC+8q5WkzkvUUi4z+dpUBtw6x/snypM8rkV9T6/eGEjt3a3T4dlAmsEJqmip8eqSnYLm6nG/mL6LOb7ZM6uGLvkI4J9Z6ruX4Q= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638194; c=relaxed/simple; bh=5r2bP7wVnpDA+nj2eWxEMkp7ZJM3qp0xftH6fsdbeKU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M9QnEYeVTyHNY9KvJpOvwFYoDsj5d2/NlaGSCdKB77wGtTRyh/YmBk59k1PTQr2e2D06LxNIm/Dr3vkJiikMlkQwzeRyHnU17xr3EOcwOp04h8SI5ooAHZEzOwwuCzTICmeRpGbLPDFkNXjp+Vl90mxs5Oa4x517yiZQ9OOqY6Y= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.126.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CXbsSen6CQXPQ2NcZjhvelqobT+DlEubAg34XWM9RK3owgjR97IdVMYrtXy/Ckajk3pV+cGYS5d+oUU1biKri72FJRBXs0dQ9gdYHEtGd54O2yNVdrEx9a3vF1DVNie7OIIvXDHrv8U6KIUidGabje80huKlAHvBP+6/v+Axz78YtA2MO/+uImK4bSwGrqionpcOpT3Fx7jVzPhdxYZqdQexQ275D1V9k2aNZz4PAS85v05JYUC2C8C8GdnS/IuIFxmWqJB4phmfX/D0IhwOR9OW7dVk+Esx/UaGvwrm4aR+BJO8HgEkNZ9oLQVFPy/yRz54x5G+qPVBTxilrOX0Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iodmOlYm0/HiWFPiDth8gwAbe72TTsTeVjkZRlbI26I=; b=imPKikdkgEgYgn8fXaNQdbm+D3gNpyU/h6ahRouWl6ackszpZgsDT62KLjiccFcdmN8SVfMWqrmXwp/6tH8xFgTDK3yPVR6fBbnwKkQrUmOKVYG63iUjWPD6m+TpULk7jNYJvVgMpA8VVJb9cW5nIQYaLdo+swb0lxvsnad9NUkYjUOx4hH+/Pvcn/SC4vCPhFcLE1OLmhAZCc+FP/9lnzA4r6h4tQkaD2Te3GyCnbyCQayVn51iBLq2Doj0j6xuagX3saTWdM8W0tDXq5N5bb5gbjlV5AkZisUevi+C6CdrC290lq1X6Ipyk5jGxsoyxD8wyis39RzXvTBjXyZh6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TYCP286CA0027.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:263::18) by KU2PPF1A2CB34C0.apcprd06.prod.outlook.com (2603:1096:d18::48b) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.18; Fri, 8 Aug 2025 07:29:46 +0000 Received: from TY2PEPF0000AB86.apcprd03.prod.outlook.com (2603:1096:400:263:cafe::c7) by TYCP286CA0027.outlook.office365.com (2603:1096:400:263::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9009.14 via Frontend Transport; Fri, 8 Aug 2025 07:29:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB86.mail.protection.outlook.com (10.167.253.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9B9D7416050B; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 11/12] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Fri, 8 Aug 2025 15:29:28 +0800 Message-ID: <20250808072929.4090694-12-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB86:EE_|KU2PPF1A2CB34C0:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d392f48-e042-48a0-8938-08ddd64d5415 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aWtA30K0zA4f3lve4U99k1FaysfMZYYocY+XQa5UWNL2ELcw6Ps0U+FTgTTz?= =?us-ascii?Q?dsQYrUgr9F1ohzjC5hWL27+doz4umxdjWTHgZuX2Wv3yeKNtDrrDdkAMdYc/?= =?us-ascii?Q?Z2iSuCMohNiJGS34YqnCTRudATFuUlF520DsRkQ+Z5YXkJ0fxnlNx2VMrEzk?= =?us-ascii?Q?foMBoZ1z9Nzi2j7Sz0qoOfaVw49XZngSZIEgEBSdEHgvbdf2tI/YWmnMkhpr?= =?us-ascii?Q?1L5S3O8u9XYTTexJS9xuU7QdCIlRp32FlSB1fh8N1Ki20RpwYy6jHiOOJqdH?= =?us-ascii?Q?O9hqkYfvaIoiwHX/DL3RXJv3ADmrb+Fa6KoWqOgBjxJFzjlrN7C5Kj4GqaVN?= =?us-ascii?Q?Ceh7jq7+JbR6SqsIHfBc19oHzEaaKWU4k0huHLpRuQhgGzFIvVqqRKQxp5c0?= =?us-ascii?Q?/mOQnl0LS3AdNNMgfU89zIyjCuFeFqIvv82m7/bzLBQglh83M6UnNE+TZtjQ?= =?us-ascii?Q?5Aq39Q4wc3g11tmcGF8RtBImIadGChfWMTi+ns4LSvI8KFZT368vpIzSyzEc?= =?us-ascii?Q?kl3RZjvfepSV7vLeD03ymRoMDxbAQLj26doHXABFehgrjH+PtQM2muD4cj44?= =?us-ascii?Q?83bbZvbEh1rr+8Zy01K/zzMqQvCRakOqIT8ZJAaW3Ty2LAwIw5AGfmDHcjg/?= =?us-ascii?Q?oCGPKuI+/Oi8PM2eRaIKZ5rlqCNh8bwqpFm5UIGFoON6jnWxdTfXRPul55Hz?= =?us-ascii?Q?37hGHFuHroU+WPjqJj8TWtIpjMWwzIEks8h9A67iewVzfCMirAW1TDGt/YL0?= =?us-ascii?Q?cJIlVpGKATlJKBHGGhEwfl9hoPqN1cAu8k4/5wHIlwkg8LvQH2IRpWbID3tf?= =?us-ascii?Q?PsnmhIePx2qha6RcLsrHaSwYkxmAEdEHoFxaq3l95ZBZ8a5GoIjcDz+JpOEk?= =?us-ascii?Q?DDeNtz/WIFW/0vpJVwWx4q0F1W7CSWZAafRCtaAWPe9+la0N/3RorvClKWfv?= =?us-ascii?Q?wDjwWBXK9mlKkHySZuY3P48bBC37bbZitp6LnJjPYAys7fEHA2KLHoNg0liB?= =?us-ascii?Q?WJAPwPhfZV2vX+E1217PGvQPO9uEqQTKHVl6ynd7dANX66FpzzTDZQfV2OFT?= =?us-ascii?Q?omcXvoWuDPVXxdVTzImk6I1QZ0RBiTvu6F7g8rnljRPLW1DfnYdDEuFKVT+H?= =?us-ascii?Q?+Ueopq2aI7GrwbtGy48mX+/V65iegorDVnMgZ5LPW+0OQnW25GMGxqvl9dlS?= =?us-ascii?Q?ld0HpWDtjBW8m1Fdr3nPNoNaoV7hA0UZmuFrwl0gZHWmDiN2Z/RPQuUUx42Z?= =?us-ascii?Q?09aJYNOdighGeRD6SyFwYzrW4uvuJ/PtQc92XrhCWdCv+gQwXMR4qcoHsZU3?= =?us-ascii?Q?JIpo+e4wo0zCbjC9DoF2ds9navrluB98YrAP7LN+ttcneHm7tqReeM2jEz8f?= =?us-ascii?Q?Cj7M4M7rBeUt5RWkIZceNQTHsixMRTWPXapmLLfXTxVkV7uThTASgVIyWoj3?= =?us-ascii?Q?3Ul5FxP9TbzKiFp6XYDJOpOfPGmJ2l5FcoLD09Ef5dWhR4mGwOQiX+JdOgSY?= =?us-ascii?Q?EOF0klQKQ7ptYMa/BW2DH5BNgruKkATtY7qh?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.5729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d392f48-e042-48a0-8938-08ddd64d5415 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB86.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KU2PPF1A2CB34C0 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang --- arch/arm64/boot/dts/cix/sky1.dtsi | 121 ++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 7dfe7677e649..04ba80d4fc06 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -288,6 +288,127 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000000 0x00 0x10000>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060000 0x00 0x10000>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a060040 0x00 0x10000>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060060 0x00 0x10000>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060080 0x00 0x10000>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu", "msg"; + ranges =3D <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x30 0x5f>; + device_type =3D "pci"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x3000 &gic_its 0x3000 0x3000>; + status =3D "disabled"; + }; + gic: interrupt-controller@e010000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ --=20 2.49.0 From nobody Sun Oct 5 05:27:11 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022111.outbound.protection.outlook.com [40.107.75.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2554723C4FC; Fri, 8 Aug 2025 07:29:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.75.111 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638184; cv=fail; b=TAjyQRmbUTx/IZQN/zsSrjM1gzA4vDNffP5iKUVEIWspG7x7MUDN3t/HydNPT+u5BvL+AR/hJuMquDe9jW0m4nFIWd2YGviNOfkO7FfuEYp60ao5ELJvr44IdtUidERm74Vmagxqbx6PXw2+AWjgoXDQTF6E/IkfdK2HzxbHUs4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754638184; c=relaxed/simple; bh=r+Qkefs47oY6jF0PEqr2QE+PsGCgJIkkgwfbMofRvbI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TQptFq6SAdG4xkuou2veWf//Cg4mVZ4WCHnLiOg7WIBXWvbeWDha9Jpcck5Yz09nB2U1k/VAba5t+BDZk9o/XCRyz8GsioHH+anr91Y1VQdLRqW8Jd7jYuEHrETqnrF1sKdORoZ8s8JSYYYY5s53pe2RjsZkk5VjmRkDun9fwuk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.75.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eker2cvojW5An/e3aYoALn3PCbpj842QLnxOGLp/hQ6HoJhEfMA+gY3qOR5rdAKqkd+WKDlJ+EOyv51yOkZ040WQ720CGhODMn5NsrIJGDDfhhc6Ez0xLSh0ZrIScpO2gIEJ22v0xhq0OENG/U2lcGIOjFw1ga8ljqZdRVcuVZR8EH/bAUeqBTh6ZLSSLl0oY4EP/VuJ2Pnu5NaswSL7vFti8BnzzvurfRklm0fjInWj03kI0G/mdf9FuVFLLRecxkasel6hjVDRNUtCiEE1EpJDEqxrYQW+RLl8VqxL5i9L7GOWG0YFTuEepO/ibKR61h0uqVPW7VurNZ8CweAX8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=M+5ibsszrIdg2MynYFSRWpz2hkTGEqoGCPPfJGeKGNk=; b=Xhl9Kfc2uC3yxihlojRBQU1Tu50ShDZdzDu08aVryegXcn/X0lgbarcvXu02+3Bqe0B7lXu1N5a8tz54pvidCKCoR93hmKS6q0nCBCm93QWfFB++NOtPH41T0igI96x1CgRX13aarkeycVLyqFVFdeVW0s0KN4qbEJS0/0009qteegbGeQIjVYmz8MwkaApmkqYuiNZd/SsML1zwBDJ1J3dQZQgsZpFkLAYKspcjFObes+piKxroD1G2Tlzc34bS9o5iHgbRJm934aEjGsldUZ3IWRGGvPsqa1L4KaGDghDgozrJpWA7woD/eZE3mXZcsu8lGvi2YbIX/fCU5GlUAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SI2P153CA0001.APCP153.PROD.OUTLOOK.COM (2603:1096:4:140::7) by TYZPR06MB6914.apcprd06.prod.outlook.com (2603:1096:405:41::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.15; Fri, 8 Aug 2025 07:29:38 +0000 Received: from SG1PEPF000082E8.apcprd02.prod.outlook.com (2603:1096:4:140:cafe::d5) by SI2P153CA0001.outlook.office365.com (2603:1096:4:140::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9031.9 via Frontend Transport; Fri, 8 Aug 2025 07:29:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E8.mail.protection.outlook.com (10.167.240.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Fri, 8 Aug 2025 07:29:36 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id AAE9F4160511; Fri, 8 Aug 2025 15:29:31 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v6 12/12] arm64: dts: cix: Enable PCIe on the Orion O6 board Date: Fri, 8 Aug 2025 15:29:29 +0800 Message-ID: <20250808072929.4090694-13-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250808072929.4090694-1-hans.zhang@cixtech.com> References: <20250808072929.4090694-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E8:EE_|TYZPR06MB6914:EE_ X-MS-Office365-Filtering-Correlation-Id: fccb934d-03f4-4614-5c0b-08ddd64d5430 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?c9HPCUoYmIMdzr/E0ep7ItL0yh6PeoVQrt2Y+kduHz0eIhNjMAh1kuNDrY/1?= =?us-ascii?Q?lelv0E3JU3+81BTl2I0CQK7zOQEPt7OIBQlhbECKd2XKyT/r+UNoOLs/eaQV?= =?us-ascii?Q?Ksd7C9j1AvicJmmnknWVo7LNjD51SVKxtpGIJou2GcDX6zvZma2nG4Zkn+ZJ?= =?us-ascii?Q?iow5HE0oKfyd17LSFPW6zFGdBW4j0MkQgtXA863d6FKEerAXVqU1kvy6vsnh?= =?us-ascii?Q?Tk5THiJKqCyQQm4koVZmX0gaK1ez4irdDFh9t8Ij7z9xEEk5X1VR8mRRhHxa?= =?us-ascii?Q?Zwq1FdUjXDehsNcWQ3wDFfCLoeQ07GOlKbGwHuloSDvGKSLj0mCisXudjqko?= =?us-ascii?Q?SOT2b+XU2tdn4AP9MY7oQBEh/A3BZLovYP0XasYpP0ThbR1kwCndbc3PNxNU?= =?us-ascii?Q?UyFVaZep+NB8uZmwlACEvRgffKbwabX1AwOb65KJVFMYBwnq21PJMKIxGbID?= =?us-ascii?Q?O/5EIDQBqnZs3Syz9DwNAZd8yUFkJVs2t8u5UcYNK6x3I8U71nBX7bpAB/Cp?= =?us-ascii?Q?4sP0tlhB6pFmi88u1t57UVo5KaDn1oMrruja+LpYm1KUy5M94v8/J9E45s8z?= =?us-ascii?Q?4XgjX1tt8AW3+mVdTLe7/2zFPFzozeiyrAjahAK9aCcofT02Pf2xoOpTCsLm?= =?us-ascii?Q?NaeNMPaMmBszxzEfSvrcWcboIHehEa1shtFZG37pGRcbDnD3aqC23urz60Ub?= =?us-ascii?Q?TjsDas1BApAgVi7xy/d5qvsdG5OsgRjX1/Z0qShwjymShfMcoaJRKMtc5cFQ?= =?us-ascii?Q?uGQrbSsOfTwx8zoWbXbiki+JBzDkK++RP5Kp7lYnksUQJWDox4t24VH6L2WZ?= =?us-ascii?Q?4bIw7Uw+7SG+eB31aLPv/fjZ+cdb98l84xFULb5g3X9XkYppwoz+eIqn8WDW?= =?us-ascii?Q?f+C5kQgWkYw6hS5sIFCwJ6b39WbYv9n0l+Xp8FDIz7rW4iVcpMFlcWs9lnsp?= =?us-ascii?Q?AHC3/Hx8Yo1kNVLWVOF2xYCrW9k2fHTlFcl20L3ylrtbR5FPDMmnh4p0O54F?= =?us-ascii?Q?K/vZ+gUh5EkLM53cMWM80TUsTZW4Sv+xEmLPUau8D3rdkvym2p54c0tPjYjw?= =?us-ascii?Q?tdilTLTlJb151xm/XQEzFPUkyLfUzU/zA3oRuOCGFrWmUxzXVZnRTlma9uEc?= =?us-ascii?Q?uUzY9BIKyboaB06GFgABFf25N2Shto0QaNi8vFShG+lqlplTyXfMUiIA/7BI?= =?us-ascii?Q?pBkHbCjrv95luFaKYYcQEIu+5/XdBspipTxoTD8R5WtOM+sjpB7oCGOXdM4J?= =?us-ascii?Q?wyotAYnWDWVbwcFcLatHKr2yIxvcSdnhBONxEj0NNydKeirJsp0UGfImn3Ob?= =?us-ascii?Q?hVdg+pUp0xciPsBLP+j5zmbKN1ZxYWLg6Bfz5jBDQOe7gDE2DoSsVnGvEqSw?= =?us-ascii?Q?+4V7Vq9mzAqrfCN+u6tgadXrGvzrKAP/OvsoKmAZ4EjqW9nQ1xKQCG7mFzZ/?= =?us-ascii?Q?beQtHkZd22maQAGbaadb6YIXNJAnsXZQJKiwX2M6OwNfUd5lXDZNPX10qIjr?= =?us-ascii?Q?CgRF3eyg7Ly5ZKwQ5uM+kIwUYhdEhnD69p4D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2025 07:29:36.2956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fccb934d-03f4-4614-5c0b-08ddd64d5430 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6914 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add PCIe RC support on Orion O6 board. Signed-off-by: Hans Zhang --- Dear Krzysztof, Due to the fact that the GPIO, PINCTRL and other modules of our platform are not yet ready for upstream. Attributes that PCIe depends on, such as reset-= gpios and pinctrl*, have not been added for the time being. It will be added grad= ually in the future. The following are Arnd's previous comments. We can go to upsteam separately. https://lore.kernel.org/all/422deb4d-db29-48c1-b0c9-7915951df500@app.fastma= il.com/ --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index d74964d53c3b..be3ec4f5d11e 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -34,6 +34,26 @@ linux,cma { =20 }; =20 +&pcie_x8_rc { + status =3D "okay"; +}; + +&pcie_x4_rc { + status =3D "okay"; +}; + +&pcie_x2_rc { + status =3D "okay"; +}; + +&pcie_x1_0_rc { + status =3D "okay"; +}; + +&pcie_x1_1_rc { + status =3D "okay"; +}; + &uart2 { status =3D "okay"; }; --=20 2.49.0