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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, John Madieu , Claudiu Beznea Subject: [PATCH v4 1/8] soc: renesas: rz-sysc: Add syscon/regmap support Date: Fri, 8 Aug 2025 09:17:59 +0300 Message-ID: <20250808061806.2729274-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: John Madieu The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, register a custom regmap configuration. Signed-off-by: John Madieu [claudiu.beznea: - do not check the match->data validity in rz_sysc_probe() as it is always valid - dinamically allocate regmap_cfg] Signed-off-by: Claudiu Beznea --- Changes in v4: - adjusted the patch description by dropping "add" from "add register a custom regmap configuration" - updated the list of changes from Claudiu Beznea - dynamically allocate the regmap_config as proposed at [2] - this patch is needed for proper function of USB (as proposed in this series) that being the reason it is introduced here, as well [2] https://lore.kernel.org/all/CAMuHMdVyf3Xtpw=3DLWHrnD2CVQX4xYm=3DFBHvY_d= x9OesHDz5zNg@mail.gmail.com/ Changes in v3: - none, this patch is new, it was picked from John after he addressed the review comments received at [1]; - I adjusted as specified in the SoB area, and included it here as it is the base for the signal support presented in the next commits [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.r= enesas.com/ drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 1 + drivers/soc/renesas/r9a09g047-sys.c | 1 + drivers/soc/renesas/r9a09g057-sys.c | 1 + drivers/soc/renesas/rz-sysc.c | 29 +++++++++++++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 2 ++ 6 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 719b7f4f376f..c97e2a183388 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -449,6 +449,7 @@ config RST_RCAR =20 config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON =20 config SYSC_R9A08G045 bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPIL= E_TEST diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index f4db1431e036..0504d4e68761 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -20,4 +20,5 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_s= oc_id_init_data __initc =20 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, + .max_register =3D 0xe20, }; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index cd2eb7782cfe..2e8426c03050 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_so= c_id_init_data __initco =20 const struct rz_sysc_init_data rzg3e_sys_init_data =3D { .soc_id_init_data =3D &rzg3e_sys_soc_id_init_data, + .max_register =3D 0x170c, }; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 4c21cc29edbc..e3390e7c7fe5 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_so= c_id_init_data __initco =20 const struct rz_sysc_init_data rzv2h_sys_init_data =3D { .soc_id_init_data =3D &rzv2h_sys_soc_id_init_data, + .max_register =3D 0x170c, }; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ffa65fb4dade..66cc8d01f096 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -6,8 +6,10 @@ */ =20 #include +#include #include #include +#include #include =20 #include "rz-sysc.h" @@ -100,14 +102,20 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); =20 static int rz_sysc_probe(struct platform_device *pdev) { + const struct rz_sysc_init_data *data; const struct of_device_id *match; + struct regmap_config *regmap_cfg; struct device *dev =3D &pdev->dev; + struct regmap *regmap; struct rz_sysc *sysc; + int ret; =20 match =3D of_match_node(rz_sysc_match, dev->of_node); if (!match) return -ENODEV; =20 + data =3D match->data; + sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) return -ENOMEM; @@ -117,7 +125,26 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); =20 sysc->dev =3D dev; - return rz_sysc_soc_init(sysc, match); + ret =3D rz_sysc_soc_init(sysc, match); + if (ret) + return ret; + + regmap_cfg =3D devm_kzalloc(dev, sizeof(*regmap_cfg), GFP_KERNEL); + if (!regmap_cfg) + return -ENOMEM; + + regmap_cfg->name =3D "rz_sysc_regs"; + regmap_cfg->reg_bits =3D 32; + regmap_cfg->reg_stride =3D 4; + regmap_cfg->val_bits =3D 32; + regmap_cfg->fast_io =3D true; + regmap_cfg->max_register =3D data->max_register; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Conor Dooley Subject: [PATCH v4 2/8] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Date: Fri, 8 Aug 2025 09:18:00 +0300 Message-ID: <20250808061806.2729274-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S p= hy bindings") Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - collected tags - rebased on top of latest version of renesas,usb2-phy.yaml; Conor, Geert: I kept your tags; please let me know if you consider it otherwise Changes in v2: - none; this patch is new Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/= Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index f45c5f039ae8..52d777057281 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -112,6 +112,7 @@ allOf: contains: enum: - renesas,usb2-phy-r9a09g057 + - renesas,usb2-phy-r9a08g045 - renesas,rzg2l-usb2-phy then: properties: --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28098224B06 for ; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Christophe JAILLET , Claudiu Beznea Subject: [PATCH v4 3/8] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Date: Fri, 8 Aug 2025 09:18:01 +0300 Message-ID: <20250808061806.2729274-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christophe JAILLET If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initiali= ze the bus") Signed-off-by: Christophe JAILLET Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven [claudiu.beznea: removed "struct reset_control *rstc =3D data;" from rcar_gen3_reset_assert()] Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - collected tags Changes in v2: - none; this patch is new; re-spinned the Christophe's work at https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR= 01MB11332.jpnprd01.prod.outlook.com/ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas= /phy-rcar-gen3-usb2.c index 47beb94cd424..d61c171d454f 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -699,6 +699,11 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct d= evice_node *np) return candidate; } =20 +static void rcar_gen3_reset_assert(void *data) +{ + reset_control_assert(data); +} + static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) { struct device *dev =3D channel->dev; @@ -717,6 +722,11 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen= 3_chan *channel) if (ret) goto rpm_put; =20 + ret =3D devm_add_action_or_reset(dev, rcar_gen3_reset_assert, + channel->rstc); + if (ret) + goto rpm_put; + val =3D readl(channel->base + USB2_AHB_BUS_CTR); val &=3D ~USB2_AHB_BUS_CTR_MBL_MASK; val |=3D USB2_AHB_BUS_CTR_MBL_INCR4; @@ -860,7 +870,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_d= evice *pdev) if (channel->is_otg_channel) device_remove_file(&pdev->dev, &dev_attr_role); =20 - reset_control_assert(channel->rstc); pm_runtime_disable(&pdev->dev); }; =20 --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEF2022759C for ; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:28 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v4 4/8] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Date: Fri, 8 Aug 2025 09:18:02 +0300 Message-ID: <20250808061806.2729274-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas USB PHY hardware block needs to have the PWRRDY bit in the system controller set before applying any other settings. The PWRRDY bit must be controlled during power-on, power-off, and system suspend/resume sequences as follows: - during power-on/resume, it must be set to zero before enabling clocks and modules - during power-off/suspend, it must be set to one after disabling clocks and modules Add the renesas,sysc-pwrrdy device tree property, which allows the reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system controller PWRRDY bit at the appropriate time. Along with it add a new compatible for the RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring (Arm) --- Changes in v4: - dropped blank line from compatible section - s/renesas,sysc-signals/renesas,sysc-pwrrdy/g - dropped description from renesas,sysc-pwrrdy - updated description of renesas,sysc-pwrrdy items - updated patch description Changes in v3: - none; this patch is new .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 40 ++++++++++++++++--- 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-c= trl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctr= l.yaml index b0b20af15313..c1d5f3228aa9 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,14 @@ description: =20 properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S =20 reg: maxItems: 1 @@ -48,6 +50,19 @@ properties: $ref: /schemas/regulator/regulator.yaml# unevaluatedProperties: false =20 + renesas,sysc-pwrrdy: + description: The system controller PWRRDY indicates to the USB PHY if = the + power supply is ready. PWRRDY needs to be set during powe= r-on + before applying any other settings. It also needs to + be set before powering off the USB. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: System controller phandle required by USB PHY CTRL + driver to set PWRRDY + - description: Register offset associated with PWRRDY + - description: Register bitmask associated with PWRRDY + required: - compatible - reg @@ -57,6 +72,19 @@ required: - '#reset-cells' - regulator-vbus =20 +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-usbphy-ctrl + then: + required: + - renesas,sysc-pwrrdy + else: + properties: + renesas,sysc-pwrrdy: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DE1621CFEF for ; Fri, 8 Aug 2025 06:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754633914; cv=none; b=kI8j7yifjZ8hhV+yoBJhaNabFxlGGQT/AIegwJn894MF8qXrkZaqyxY54oiA+GlEXGjoG+S/LClvZT0SvBC7R9TePLE8SxEqNdbSSNgYBZCOn+DmXTbiraUpgvQgg9CpOP8GV9sw/LkTrm6t08L/AIsoAIBepEMY9eYSVvc4/Mg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754633914; c=relaxed/simple; bh=XAgJqTi+xocUch4hMijm4OJw8p22LIqhgdGf5SAzVA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kcXcnSC0K4PIzwVx3tRmingU3hTenkQWTrF+dXpWs30S6rYPpihU0SyPB4A+hxlrZs3MJvukaeG2cQVocSTU4Mck4QTRlOMIWOLSMGabvpnHjUdoFNwW5MHZLKmlG377GYSMsFIkUuTX20K+VP9PQV1w0PiO5TQIuPWQukt7fZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Hgzpea4D; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Hgzpea4D" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-af910372ab3so475996766b.1 for ; Thu, 07 Aug 2025 23:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1754633910; x=1755238710; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rlVUJVCA5E+NH57NVU2ZeWb+jDLbLNL3sIxsb59oNIs=; b=Hgzpea4DdTkd/hUizXiffjbV2DwxzHmF/Bn2eEiOmYqAmgzVbqVEw4/ubImaeiR9ER vca+pudyks+CjVx1l7O+J9bkq98cIsGwmlLpHDCgBUreBGgmAuMGRC6RDQHS4lTeZ4Pm 4B4/ncCsNJnO7t2zif77gAjrx3Cw5sNnAtI0D3KHfqi9z3lbEH1Bg9m6cD6QgCk++MWr NWxz+gfKP/wtwxF6isHf9qCnW4cKXV062fEcZgvU4Frb1Exs3sNcOEVcPSilIU2Mh8EU Amg0mTs9wYq5JGwuSphWZpUTiWvy7nvUBDQhlpmLCH1Meey+7jpNI9aN4qkrmAlBMNdM ok9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754633910; x=1755238710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rlVUJVCA5E+NH57NVU2ZeWb+jDLbLNL3sIxsb59oNIs=; b=kiU+ZvKb3XeZoYIgT1awan0euftK/arl7h/jFT44gMMl2FL8EVvoEO9dW1XXqP2co0 060izYC/XoxJ33f5Ld0iMotUvK2Wlh7xMBSSdXsZQMHru0BmsvGIzprDMSI5f3+xQkEI +DZonbp19M60lqRu/RE2VAefAM+Zl+Rm6ZeVLhCRZNwgxyAbTUB/P5Xzk9dPJI3NHPme uJ9gkz5JghCpVpiiQttdDuaOTcNdpDftaCuIeZbIWJIMAaH7LpY9p7YUf2v3YjEzFb++ MsuVwdLpdBVVHxy5g3D0ttbu8YXAS0Y1k0SmbiSeIzTjcfMYvwi/2cfTPFwkA5rMaDvY QCuQ== X-Forwarded-Encrypted: i=1; AJvYcCUWdcSkvusLzt7WUpnmA3E1fZACVnUDEyUthzXi0YMNR2wRMiWsGUahj2qg9aFGF7bcXIOlC0b12YDE6Jg=@vger.kernel.org X-Gm-Message-State: AOJu0YyjC6uGyWOhe3WQfc0i58qYyH84cTGBpP+TR711eSDAbZUFCbJ3 iwLE8UwFSKwMg39f8m7sPc6DD51j/EcPXetwZobcQwAbm652u0D6GfngZUw4BmNDWs4= X-Gm-Gg: ASbGncuHK+zUrfVEARPWVoLtlwnR5cQ6hVGAkPaIro1k8ppG2z2zg5dMhm8wva2g+ro AnM7mdnB0duY/sTfNtaoQGFKVsaoWxw0lcIR+KoJgADbyEPboTB4dBzr9AdEB6lrk8ppQP8pN/B TZ4Fu5/WtfbLeIKiNwOZrY+FlFrzuGj33tcsdTuREy+cD4RMT/BOIs84WSYCF8q4QltvgqEq3Pq iHscXdzYrmkW2ZAuo29OtXILwbkd3kINnrXKN6QV+BN7fmcpM9wjdZ7FaMg8gG8WiGAoOIvUSa1 ooPI87gLZyaJwAfd8N4bIb2UlCdyj3MitdF5yoy7IqQ33dIc7gZcPKFUHuhQis3Zx0dEk8ea2I1 +lI2zc/5+g8DZWTjMEdkZ9kX5NKVwbKrq7N7YbS1/fkQYRZoj/PKV X-Google-Smtp-Source: AGHT+IHKJhBC5W1zHHSEO8GQ/O6uPU5JFViR6qbM512GPR/tuQoaCZTYbDiZRLovnGz2SYP/L6FNWg== X-Received: by 2002:a17:907:d0b:b0:af9:3f99:1422 with SMTP id a640c23a62f3a-af9a3c59269mr632176066b.5.1754633910467; Thu, 07 Aug 2025 23:18:30 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v4 5/8] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY Date: Fri, 8 Aug 2025 09:18:03 +0300 Message-ID: <20250808061806.2729274-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. On power-on the USB PWRRDY signal need to be de-asserted before enabling clock and switching the module to normal state (through MSTOP support). The power-on configuration sequence must be: 1/ PWRRDY=3D0 2/ CLK_ON=3D1 3/ MSTOP=3D0 On power-off the configuration sequence should be: 1/ MSTOP=3D1 2/ CLK_ON=3D0 3/ PWRRDY=3D1 The CLK_ON and MSTOP functionalities are controlled by clock drivers. After long discussions with the internal HW team, it has been confirmed that the HW connection b/w USB PHY block, the USB channels, the system controller, clock, MSTOP, PWRRDY signal is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2= =94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK0_ON =E2=94=82 USB CH0 =E2= =94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90= =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK2_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82host control= ler registers =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82fu= nction controller registers=E2=94=82 =E2=94=82 =E2=94=82 PHY0 =E2=94=82=E2=97=84=E2=94=80=E2= =94=80=E2=94=A4=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 USB PHY =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTO= P{6, 5}_ON =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82USHPHY control=E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82 registers =E2=94=82 =E2=94=82 PHY1 =E2=94=82 =E2= =94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =98 =E2=94=82 =E2=94=82=E2=97=84=E2=94=80=E2=94=80=E2=94=A4 USB = CH1 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=8C=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK1_ON =E2=94=94=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=82 host controller registers = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=94= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MS= TOP.MSTOP7_ON =E2=94=82PWRRDY =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_CLK_ON_USB.CLK3_ON =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82SYSC=E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 where: - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X of different USB blocks, X in {0, 1, 2, 3} - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the MSTOP of different USB blocks, X in {4, 5, 6, 7} - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used by the USB CH0, USB CH1 - SYSC is the system controller block controlling the PWRRDY signal - USB CHx are individual USB block with host and function capabilities (USB CH0 have both host and function capabilities, USB CH1 has only host capabilities) The USBPHY control registers are controlled though the reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver. The connection b/w the system controller and the USB PHY CTRL driver is implemented through the renesas,sysc-pwrrdy device tree property proposed in this patch. This property specifies the register offset and the bitmask required to control the PWRRDY signal. Since the USB PHY CTRL driver needs to be probed before any other USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively to it. This guarantees the correct configuration sequence between clocks, MSTOP bits, and the PWRRDY bit. At the same time, changes are kept minimal by avoiding modifications to the USB PHY driver to also handle the PWRRDY itself. Signed-off-by: Claudiu Beznea --- Changes in v4: - updated patch description - updated rzg2l_usbphy_ctrl_pwrrdy_init() to map directly the "renesas,sysc-pwrrdy" as the SYSC signal abstraction was dropped in this version, along with rz_sysc_get_signal_map() - dropped priv member of rzg2l_usbphy_ctrl_pwrrdy_init() as it is not needed in this version - shift left !power_on with pwrrdy->mask as this is how the regmap_update_bits() needs the last member to be - selected MFD_SYSCON Changes in v3: - none; this patch is new drivers/reset/Kconfig | 1 + drivers/reset/reset-rzg2l-usbphy-ctrl.c | 66 +++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 635eef469ab7..3524b760dc1b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -230,6 +230,7 @@ config RESET_RASPBERRYPI config RESET_RZG2L_USBPHY_CTRL tristate "Renesas RZ/G2L USBPHY control driver" depends on ARCH_RZG2L || COMPILE_TEST + select MFD_SYSCON help Support for USBPHY Control found on RZ/G2L family. It mainly controls reset and power down of the USB/PHY. diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 8a7f167e405e..fc14c41f5572 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #define RESET 0x000 #define VBENCTL 0x03c @@ -41,6 +42,18 @@ struct rzg2l_usbphy_ctrl_priv { =20 #define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rc= dev) =20 +/** + * struct rzg2l_usbphy_ctrl_pwrrdy - SYSC PWRRDY signal descriptor + * @regmap: SYSC regmap + * @offset: offset into the SYSC address space for accessing PWRRDY + * @mask: mask into the register at offset for accessing PWRRDY + */ +struct rzg2l_usbphy_ctrl_pwrrdy { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev, unsigned long id) { @@ -91,6 +104,8 @@ static int rzg2l_usbphy_ctrl_status(struct reset_control= ler_dev *rcdev, return !!(readl(priv->base + RESET) & port_mask); } =20 +#define RZG2L_USBPHY_CTRL_PWRRDY 1 + static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, { /* Sentinel */ } @@ -110,6 +125,53 @@ static const struct regmap_config rzg2l_usb_regconf = =3D { .max_register =3D 1, }; =20 +static void rzg2l_usbphy_ctrl_set_pwrrdy(struct rzg2l_usbphy_ctrl_pwrrdy *= pwrrdy, + bool power_on) +{ + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, + !power_on << pwrrdy->mask); +} + +static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) +{ + rzg2l_usbphy_ctrl_set_pwrrdy(data, false); +} + +static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev) +{ + struct rzg2l_usbphy_ctrl_pwrrdy *pwrrdy; + struct of_phandle_args args; + struct regmap *regmap; + const int *data; + int ret; + + data =3D device_get_match_data(dev); + if (data !=3D (int *)RZG2L_USBPHY_CTRL_PWRRDY) + return 0; + + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "renesas,sysc-pwrr= dy", 2, + 0, &args); + if (ret) + return ret; + + regmap =3D syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pwrrdy =3D devm_kzalloc(dev, sizeof(*pwrrdy), GFP_KERNEL); + if (!pwrrdy) + return -ENOMEM; + + pwrrdy->regmap =3D regmap; + pwrrdy->offset =3D args.args[0]; + pwrrdy->mask =3D args.args[1]; + + rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true); + + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy= ); +} + static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -132,6 +194,10 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_dev= ice *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + error =3D rzg2l_usbphy_ctrl_pwrrdy_init(dev); + if (error) + return error; + priv->rstc =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7558D2288E3 for ; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:31 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v4 6/8] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Date: Fri, 8 Aug 2025 09:18:04 +0300 Message-ID: <20250808061806.2729274-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY signal from the system controller. Add support for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - none; this patch is new drivers/reset/reset-rzg2l-usbphy-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index fc14c41f5572..8aa2a5833c2e 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -108,6 +108,10 @@ static int rzg2l_usbphy_ctrl_status(struct reset_contr= oller_dev *rcdev, =20 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, + { + .compatible =3D "renesas,r9a08g045-usbphy-ctrl", + .data =3D (void *)RZG2L_USBPHY_CTRL_PWRRDY + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F834239E65 for ; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v4 7/8] arm64: dts: renesas: r9a08g045: Add USB support Date: Fri, 8 Aug 2025 09:18:05 +0300 Message-ID: <20250808061806.2729274-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Signed-off-by: Claudiu Beznea --- Changes in v4: - dropped renesas,sysc-signals from usb2_phy0, usb2_phy1 nodes - s/renesas,sysc-signals/renesas,sysc-pwrrdy/g Changes in v3: - changed the nodes order to keep similar nodes toghether Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise=20 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 0364f89776e6..b7ad6db0174b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -681,6 +681,124 @@ eth1: ethernet@11c40000 { status =3D "disabled"; }; =20 + phyrst: usbphy-ctrl@11e00000 { + compatible =3D "renesas,r9a08g045-usbphy-ctrl"; + reg =3D <0 0x11e00000 0 0x10000>; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets =3D <&cpg R9A08G045_USB_PRESETN>; + power-domains =3D <&cpg>; + #reset-cells =3D <1>; + renesas,sysc-pwrrdy =3D <&sysc 0xd70 0x1>; + status =3D "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name =3D "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e10000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ohci1: usb@11e30000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e30000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci0: usb@11e10100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e10100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 2>; + phy-names =3D "usb"; + companion =3D <&ohci0>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci1: usb@11e30100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e30100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 2>; + phy-names =3D "usb"; + companion =3D <&ohci1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e10200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e30200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + hsusb: usb@11e20000 { + compatible =3D "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg =3D <0 0x11e20000 0 0x10000>; + interrupts =3D , + , + , + ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait =3D <7>; + phys =3D <&usb2_phy0 3>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + gic: interrupt-controller@12400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; --=20 2.43.0 From nobody Sun Oct 5 05:29:01 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87130223DD9 for ; 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([82.78.167.188]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a218ab4sm1440488566b.92.2025.08.07.23.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 23:18:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea Subject: [PATCH v4 8/8] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Fri, 8 Aug 2025 09:18:06 +0300 Message-ID: <20250808061806.2729274-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> References: <20250808061806.2729274-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable USB support (host, device, USB PHYs). Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - collected tags Changes in v2: - this was patch 15/16 in v1: - dropped sysc enablement as it is now done in SoC dtsi file arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 5e044a4d0234..5586dd43c4d5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -92,6 +92,20 @@ &audio_clk2 { clock-frequency =3D <12288000>; }; =20 +&ehci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&hsusb { + dr_mode =3D "otg"; + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -132,6 +146,15 @@ power-monitor@44 { }; }; =20 +&ohci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + &pinctrl { audio_clock_pins: audio-clock { pins =3D "AUDIO_CLK1", "AUDIO_CLK2"; @@ -207,6 +230,27 @@ ssi3_pins: ssi3 { , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + peri { + pinmux =3D , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux =3D ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux =3D , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status =3D "okay"; }; =20 &scif0 { @@ -242,3 +286,16 @@ &ssi3 { pinctrl-0 =3D <&ssi3_pins>, <&audio_clock_pins>; status =3D "okay"; }; + +&usb2_phy0 { + pinctrl-0 =3D <&usb0_pins>; + pinctrl-names =3D "default"; + vbus-supply =3D <&usb0_vbus_otg>; + status =3D "okay"; +}; + +&usb2_phy1 { + pinctrl-0 =3D <&usb1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.43.0