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[93.89.165.28]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3b8fc6ef28esm6308907f8f.60.2025.08.08.10.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Aug 2025 10:15:05 -0700 (PDT) From: Gabor Juhos Date: Fri, 08 Aug 2025 19:15:01 +0200 Subject: [PATCH] spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com> X-B4-Tracking: v=1; b=H4sIAJQwlmgC/x2MUQqDMBAFryL77UKaElt7FRHR7Gu7UFKbRSmId zf4OQwzGxmywuhRbZSxquk3FbjUFcX3mF5glcLknQ/u7gL/Zo1saUzCxcsHvBgGxMiC1rfXWyP BTVT6OeOp//Pd9ft+AMSK76hrAAAA X-Change-ID: 20250805-qpic-snand-handle-use_ecc-de929376d50b To: Mark Brown Cc: Md Sadre Alam , Varadarajan Narayanan , Sricharan Ramabadhran , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.14.2 During raw read, neither the status of the ECC correction nor the erased state of the codeword gets checked by the qcom_spi_read_cw_raw() function, so in case of raw access reading the corresponding registers via DMA is superfluous. Extend the qcom_spi_config_cw_read() function to evaluate the existing (but actually unused) 'use_ecc' parameter, and configure reading only the flash status register when ECC is not used. With the change, the code gets in line with the corresponding part of the config_nand_cw_read() function in the qcom_nandc driver. Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio --- drivers/spi/spi-qpic-snand.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index 7b76d2c82a5287df13ee6fcebc4abbe58ca861ee..119003c4784890458a41c67fa8b= c17d721030b0d 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -494,9 +494,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *s= nandc, bool use_ecc, int c qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BA= M_NEXT_SGL); qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BA= M_NEXT_SGL); =20 - qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); - qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, - NAND_BAM_NEXT_SGL); + if (use_ecc) { + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, + NAND_BAM_NEXT_SGL); + } else { + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, + NAND_BAM_NEXT_SGL); + } } =20 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) --- base-commit: 13d0fe84a214658254a7412b2b46ec1507dc51f0 change-id: 20250805-qpic-snand-handle-use_ecc-de929376d50b Best regards, --=20 Gabor Juhos