From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04C4D272E7F for ; Fri, 8 Aug 2025 10:13:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754648007; cv=none; b=azCVmoL7Vs+5nqb5kuNmoaQmeFTqfd3kxU6OCADiurBCTycsi2v1XqIZNzhODlyrIjEVuqRrsrgxxxiyGvFpjv/j4gNwQwvsKpcVrANyzyd7SLMcjLNZjSgpTReXmyyGp0PIjHakWfutvgeqxdd77uTbagfeJC0se1q/TCIqZT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754648007; c=relaxed/simple; bh=nf5h1lNpleNGuRl1UxQ6idA0pn7vVFi/xWcII3JgkvM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HaZpamnNmW+JuNXwTcwSiknR0PFc8ivgAQsuryp/o2V1anrQzyCHSlKBA8hfGJ6MR3TGWX6P9PQeu04R4S8K6HBN/7+0k6Tb97msBknxfAos4HFi3ROKSEMaEc4kvkz93WLFwneGqKjF2I2gBrOJIm9gW+QebnpNHNvBv6Pr1bw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=XuYDVq6/; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="XuYDVq6/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1754648004; bh=nf5h1lNpleNGuRl1UxQ6idA0pn7vVFi/xWcII3JgkvM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XuYDVq6/PUBXKvt3WdNPtCfXSv4tMht8of1SsoVik+9NJ5S/vHMf6l7gb1q18868I 9DhUPo0FRvCGigq/EQPqzEdB1QQ4pld6GSpz1XVoV1kp6412nvsWxNnzuU8FKo0oMq mzDav6+6WyCEJuLMjFgF558IGVtUGILBTHiRVB/FtdZgeroFEfGTp5tTpvoL2Yh9Nd T8m4FqgLYFst8hOUioJkq2PYxvVxXyERyujf3X6Rm1Bmpe3b5OTTXq6wqKgGGwLDyY a241oSry5VW8i7wfae1/Z33+vas8Gl7xj/2W39w1AIa/SPL5Jrkzvtyq1Mu9jCPHtv +IltMkW0+h4Sw== Received: from yukiji.home (amontpellier-657-1-116-247.w83-113.abo.wanadoo.fr [83.113.51.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7282A17E0109; Fri, 8 Aug 2025 12:13:23 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:11 +0200 Subject: [PATCH v10 01/10] drm/mediatek: mtk_hdmi: Drop redundant clock retrieval in mtk_hdmi_get_cec_dev Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-1-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=1400; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=nf5h1lNpleNGuRl1UxQ6idA0pn7vVFi/xWcII3JgkvM=; b=edtZnff7qnJqLIBEeReiUZ3kiy09NLgimvwuBq5wQ79sQzHm3ZXeENMSPSenFakreoHXYmvKo gd72/k1VvXQAN8FvRYOSVpLWs49UZE54EPel+NIRSxQpKV9o2jz+NHW X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= In mtk_hdmi driver, when the CEC device parsing logic was moved from mtk_hdmi_dt_parse_pdata function to the new mtk_hdmi_get_cec_dev sub function, the call to mtk_hdmi_get_all_clk was kept in both functions, whereas it was only called once in the original mtk_hdmi_dt_parse_pdata code and does not need to be called a second time. So, remove this call from mtk_hdmi_get_cec_dev to keep the same sequence as previously. Fixes: 7485be967f7f ("drm/mediatek: mtk_hdmi: Move CEC device parsing in ne= w function") Signed-off-by: Louis-Alexis Eyraud Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek= /mtk_hdmi.c index 845fd8aa43c3c91659808d9e6bb78758d1f9b857..0ac4e755bdf8aace766feffa577= 12a8fbf4ff791 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -1349,11 +1349,6 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdm= i, struct device *dev, struc { struct platform_device *cec_pdev; struct device_node *cec_np; - int ret; - - ret =3D mtk_hdmi_get_all_clk(hdmi, np); - if (ret) - return dev_err_probe(dev, ret, "Failed to get clocks\n"); =20 /* The CEC module handles HDMI hotplug detection */ cec_np =3D of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8492B2737E4 for ; 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Fri, 8 Aug 2025 12:13:24 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:12 +0200 Subject: [PATCH v10 02/10] drm/mediatek: mtk_hdmi: Improve mtk_hdmi_get_all_clk() flexibility Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-2-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=3369; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=xnx1IaetdDkDo+i9PLhUTBKoc6Cky0j3zcT6XI9QWTk=; b=n0YVRgmc0m/ApOdY4c7Hh9BuETYUhPDlU8k9Ukxhi1LqMjq3O0cL0rBdLUK2Z6w/2kam+/X9A zK9+jqIwCUeCwe5MldCThnSLLdhZA7VaPcfO5iPvS2XHcrfU7Pxi646 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for splitting common bits of this driver and for introducing a new version of the MediaTek HDMI Encoder IP, improve the flexibility of function mtk_hdmi_get_all_clk() by adding a pointer to the clock names array and size of it to its parameters. Also change the array of struct clock pointers in the mtk_hdmi structure to be dynamically allocated, and allocate it in probe. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek= /mtk_hdmi.c index 0ac4e755bdf8aace766feffa57712a8fbf4ff791..f38269616679544810edafd70fd= d156aca14ad46 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -159,7 +159,7 @@ struct mtk_hdmi { struct phy *phy; struct device *cec_dev; struct i2c_adapter *ddc_adpt; - struct clk *clk[MTK_HDMI_CLK_COUNT]; + struct clk **clk; struct drm_display_mode mode; bool dvi_mode; struct regmap *sys_regmap; @@ -1072,17 +1072,18 @@ static const char * const mtk_hdmi_clk_names[MTK_HD= MI_CLK_COUNT] =3D { [MTK_HDMI_CLK_AUD_SPDIF] =3D "spdif", }; =20 -static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, - struct device_node *np) +static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node = *np, + const char * const *clock_names, size_t num_clocks) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { - hdmi->clk[i] =3D of_clk_get_by_name(np, - mtk_hdmi_clk_names[i]); + for (i =3D 0; i < num_clocks; i++) { + hdmi->clk[i] =3D of_clk_get_by_name(np, clock_names[i]); + if (IS_ERR(hdmi->clk[i])) return PTR_ERR(hdmi->clk[i]); } + return 0; } =20 @@ -1379,15 +1380,15 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hd= mi, struct device *dev, struc return 0; } =20 -static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, - struct platform_device *pdev) +static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_= device *pdev, + const char * const *clk_names, size_t num_clocks) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; struct device_node *remote, *i2c_np; int ret; =20 - ret =3D mtk_hdmi_get_all_clk(hdmi, np); + ret =3D mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks); if (ret) return dev_err_probe(dev, ret, "Failed to get clocks\n"); =20 @@ -1636,6 +1637,7 @@ static int mtk_hdmi_probe(struct platform_device *pde= v) { struct mtk_hdmi *hdmi; struct device *dev =3D &pdev->dev; + const int num_clocks =3D MTK_HDMI_CLK_COUNT; int ret; =20 hdmi =3D devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge, @@ -1646,7 +1648,11 @@ static int mtk_hdmi_probe(struct platform_device *pd= ev) hdmi->dev =3D dev; hdmi->conf =3D of_device_get_match_data(dev); =20 - ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev); + hdmi->clk =3D devm_kcalloc(dev, num_clocks, sizeof(*hdmi->clk), GFP_KERNE= L); + if (!hdmi->clk) + return -ENOMEM; + + ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev, mtk_hdmi_clk_names, num_clock= s); if (ret) return ret; =20 --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D5C42737E7 for ; Fri, 8 Aug 2025 10:13:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Fri, 8 Aug 2025 12:13:24 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:13 +0200 Subject: [PATCH v10 03/10] drm/mediatek: mtk_hdmi: Add HDMI IP version configuration to pdata Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-3-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=4617; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=ZtM41epaTDPJUP1XU4R6Byolcll2dwLNLe8c/CHQCYc=; b=4wX5iFSp5QpsXBR/pL/B9gdWUTPDd7j54Dw3B+aRbEhd5/xgjTv6FINqgo1AXNRGJtAAC2uOK ztZ5vuyajbuDESlmWwOen1JqKL/dJTjLBgAa5E3VAsKWB5jV6XE3/Qi X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for adding a driver for the HDMIv2 IP and before moving the common bits out of this driver, add a new structure `mtk_hdmi_ver_conf`, holding pointers to HDMI IP version specific drm_bridge_funcs, hdmi_codec_ops and clock array used for probe, and nest it into the mtk_hdmi_conf platform data structure. While at it, also convert all of the direct users of mtk_hdmi_bridge_funcs, mtk_hdmi_audio_codec_ops, mtk_hdmi_clk_names to use pointers from the ver_conf platform data. In order to do so, it was also necessary to fill a new version 1 specific const `mtk_hdmi_v1_ver_conf` and assign it to all of the currently supported compatibles for this driver. This commit brings no functional change. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 45 ++++++++++++++++++++++++++++++---= ---- 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek= /mtk_hdmi.c index f38269616679544810edafd70fdd156aca14ad46..63534f5a1b4d5543cd8ba10b802= c9c5b50c542d9 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -144,7 +144,15 @@ struct hdmi_audio_param { struct hdmi_codec_params codec_params; }; =20 +struct mtk_hdmi_ver_conf { + const struct drm_bridge_funcs *bridge_funcs; + const struct hdmi_codec_ops *codec_ops; + const char * const *mtk_hdmi_clock_names; + int num_clocks; +}; + struct mtk_hdmi_conf { + const struct mtk_hdmi_ver_conf *ver_conf; bool tz_disabled; bool cea_modes_only; unsigned long max_mode_clock; @@ -1602,7 +1610,7 @@ static int mtk_hdmi_register_audio_driver(struct devi= ce *dev) struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); struct hdmi_audio_param *aud_param =3D &hdmi->aud_param; struct hdmi_codec_pdata codec_data =3D { - .ops =3D &mtk_hdmi_audio_codec_ops, + .ops =3D hdmi->conf->ver_conf->codec_ops, .max_i2s_channels =3D 2, .i2s =3D 1, .data =3D hdmi, @@ -1635,24 +1643,32 @@ static int mtk_hdmi_register_audio_driver(struct de= vice *dev) =20 static int mtk_hdmi_probe(struct platform_device *pdev) { + const struct mtk_hdmi_ver_conf *ver_conf; + const struct mtk_hdmi_conf *hdmi_conf; struct mtk_hdmi *hdmi; struct device *dev =3D &pdev->dev; - const int num_clocks =3D MTK_HDMI_CLK_COUNT; int ret; =20 + hdmi_conf =3D of_device_get_match_data(dev); + if (!hdmi_conf) + return -ENODEV; + + ver_conf =3D hdmi_conf->ver_conf; + hdmi =3D devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge, - &mtk_hdmi_bridge_funcs); + ver_conf->bridge_funcs); if (IS_ERR(hdmi)) return PTR_ERR(hdmi); =20 hdmi->dev =3D dev; - hdmi->conf =3D of_device_get_match_data(dev); + hdmi->conf =3D hdmi_conf; =20 - hdmi->clk =3D devm_kcalloc(dev, num_clocks, sizeof(*hdmi->clk), GFP_KERNE= L); + hdmi->clk =3D devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk),= GFP_KERNEL); if (!hdmi->clk) return -ENOMEM; =20 - ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev, mtk_hdmi_clk_names, num_clock= s); + ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_name= s, + ver_conf->num_clocks); if (ret) return ret; =20 @@ -1713,19 +1729,32 @@ static __maybe_unused int mtk_hdmi_resume(struct de= vice *dev) =20 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resum= e); =20 +static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf =3D { + .bridge_funcs =3D &mtk_hdmi_bridge_funcs, + .codec_ops =3D &mtk_hdmi_audio_codec_ops, + .mtk_hdmi_clock_names =3D mtk_hdmi_clk_names, + .num_clocks =3D ARRAY_SIZE(mtk_hdmi_clk_names) +}; + static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 =3D { .tz_disabled =3D true, + .ver_conf =3D &mtk_hdmi_v1_ver_conf }; =20 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 =3D { - .max_mode_clock =3D 148500, .cea_modes_only =3D true, + .max_mode_clock =3D 148500, + .ver_conf =3D &mtk_hdmi_v1_ver_conf +}; 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Fri, 8 Aug 2025 12:13:25 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:14 +0200 Subject: [PATCH v10 04/10] drm/mediatek: mtk_hdmi: Split driver and add common probe function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-4-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=40011; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=RjB7NizhYGkDTueHu5gYLmZYqombFaTmKg0ncb5AEcs=; b=07c1R1vPEtVLxo3CwTlqA7R5shrLkHQL1s+/x1JT5dLPqHQGp00sBfRlCiRFCwrzpFeK9RxV6 QpL5f5AcmNLB02wHIh6Cpte6kSxKy9DvZXhkGmgVnp9ZxFXZnXIi02I X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for adding a new driver for the HDMI TX v2 IP, split out the functions that will be common between the already present mtk_hdmi (v1) driver and the new one. Since the probe flow for both drivers is 90% similar, add a common probe function that will be called from each driver's .probe() callback, avoiding lots of code duplication. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/Kconfig | 11 +- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_hdmi.c | 539 +------------------------= ---- drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 428 +++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 188 ++++++++++ 5 files changed, 633 insertions(+), 534 deletions(-) diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kc= onfig index e47debd60619d9a1dadaa547241dc06607fb845f..994b48b82d447c47391122e6ff2= d139edb223536 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -30,9 +30,18 @@ config DRM_MEDIATEK_DP help DRM/KMS Display Port driver for MediaTek SoCs. =20 +config DRM_MEDIATEK_HDMI_COMMON + tristate + depends on DRM_MEDIATEK + select DRM_DISPLAY_HDMI_HELPER + select DRM_DISPLAY_HELPER + select SND_SOC_HDMI_CODEC if SND_SOC + help + MediaTek SoC HDMI common library + config DRM_MEDIATEK_HDMI tristate "DRM HDMI Support for Mediatek SoCs" depends on DRM_MEDIATEK - select SND_SOC_HDMI_CODEC if SND_SOC + select DRM_MEDIATEK_HDMI_COMMON help DRM/KMS HDMI driver for Mediatek SoCs diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index 43afd0a26d145edaa051e67ee4dddbf34c963e9b..78cf2d4fc85ff444b936a6b705d= 86a3ec7ff1574 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -21,6 +21,7 @@ mediatek-drm-y :=3D mtk_crtc.o \ =20 obj-$(CONFIG_DRM_MEDIATEK) +=3D mediatek-drm.o =20 +obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) +=3D mtk_hdmi_common.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_cec.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_hdmi.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_hdmi_ddc.o diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek= /mtk_hdmi.c index 63534f5a1b4d5543cd8ba10b802c9c5b50c542d9..9480e4007aedd315f02b9bb050d= 6f67013a814fc 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -31,6 +31,7 @@ #include =20 #include "mtk_cec.h" +#include "mtk_hdmi_common.h" #include "mtk_hdmi_regs.h" =20 #define NCTS_BYTES 7 @@ -43,151 +44,6 @@ enum mtk_hdmi_clk_id { MTK_HDMI_CLK_COUNT }; =20 -enum hdmi_aud_input_type { - HDMI_AUD_INPUT_I2S =3D 0, - HDMI_AUD_INPUT_SPDIF, -}; - -enum hdmi_aud_i2s_fmt { - HDMI_I2S_MODE_RJT_24BIT =3D 0, - HDMI_I2S_MODE_RJT_16BIT, - HDMI_I2S_MODE_LJT_24BIT, - HDMI_I2S_MODE_LJT_16BIT, - HDMI_I2S_MODE_I2S_24BIT, - HDMI_I2S_MODE_I2S_16BIT -}; - -enum hdmi_aud_mclk { - HDMI_AUD_MCLK_128FS, - HDMI_AUD_MCLK_192FS, - HDMI_AUD_MCLK_256FS, - HDMI_AUD_MCLK_384FS, - HDMI_AUD_MCLK_512FS, - HDMI_AUD_MCLK_768FS, - HDMI_AUD_MCLK_1152FS, -}; - -enum hdmi_aud_channel_type { - HDMI_AUD_CHAN_TYPE_1_0 =3D 0, - HDMI_AUD_CHAN_TYPE_1_1, - HDMI_AUD_CHAN_TYPE_2_0, - HDMI_AUD_CHAN_TYPE_2_1, - HDMI_AUD_CHAN_TYPE_3_0, - HDMI_AUD_CHAN_TYPE_3_1, - HDMI_AUD_CHAN_TYPE_4_0, - HDMI_AUD_CHAN_TYPE_4_1, - HDMI_AUD_CHAN_TYPE_5_0, - HDMI_AUD_CHAN_TYPE_5_1, - HDMI_AUD_CHAN_TYPE_6_0, - HDMI_AUD_CHAN_TYPE_6_1, - HDMI_AUD_CHAN_TYPE_7_0, - HDMI_AUD_CHAN_TYPE_7_1, - HDMI_AUD_CHAN_TYPE_3_0_LRS, - HDMI_AUD_CHAN_TYPE_3_1_LRS, - HDMI_AUD_CHAN_TYPE_4_0_CLRS, - HDMI_AUD_CHAN_TYPE_4_1_CLRS, - HDMI_AUD_CHAN_TYPE_6_1_CS, - HDMI_AUD_CHAN_TYPE_6_1_CH, - HDMI_AUD_CHAN_TYPE_6_1_OH, - HDMI_AUD_CHAN_TYPE_6_1_CHR, - HDMI_AUD_CHAN_TYPE_7_1_LH_RH, - HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, - HDMI_AUD_CHAN_TYPE_7_1_LC_RC, - HDMI_AUD_CHAN_TYPE_7_1_LW_RW, - HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, - HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, - HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, - HDMI_AUD_CHAN_TYPE_7_1_CS_CH, - HDMI_AUD_CHAN_TYPE_7_1_CS_OH, - HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, - HDMI_AUD_CHAN_TYPE_7_1_CH_OH, - HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, - HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, - HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, - HDMI_AUD_CHAN_TYPE_6_0_CS, - HDMI_AUD_CHAN_TYPE_6_0_CH, - HDMI_AUD_CHAN_TYPE_6_0_OH, - HDMI_AUD_CHAN_TYPE_6_0_CHR, - HDMI_AUD_CHAN_TYPE_7_0_LH_RH, - HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, - HDMI_AUD_CHAN_TYPE_7_0_LC_RC, - HDMI_AUD_CHAN_TYPE_7_0_LW_RW, - HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, - HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, - HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, - HDMI_AUD_CHAN_TYPE_7_0_CS_CH, - HDMI_AUD_CHAN_TYPE_7_0_CS_OH, - HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, - HDMI_AUD_CHAN_TYPE_7_0_CH_OH, - HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, - HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, - HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, - HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, - HDMI_AUD_CHAN_TYPE_UNKNOWN =3D 0xFF -}; - -enum hdmi_aud_channel_swap_type { - HDMI_AUD_SWAP_LR, - HDMI_AUD_SWAP_LFE_CC, - HDMI_AUD_SWAP_LSRS, - HDMI_AUD_SWAP_RLS_RRS, - HDMI_AUD_SWAP_LR_STATUS, -}; - -struct hdmi_audio_param { - enum hdmi_audio_coding_type aud_codec; - enum hdmi_audio_sample_size aud_sample_size; - enum hdmi_aud_input_type aud_input_type; - enum hdmi_aud_i2s_fmt aud_i2s_fmt; - enum hdmi_aud_mclk aud_mclk; - enum hdmi_aud_channel_type aud_input_chan_type; - struct hdmi_codec_params codec_params; -}; - -struct mtk_hdmi_ver_conf { - const struct drm_bridge_funcs *bridge_funcs; - const struct hdmi_codec_ops *codec_ops; - const char * const *mtk_hdmi_clock_names; - int num_clocks; -}; - -struct mtk_hdmi_conf { - const struct mtk_hdmi_ver_conf *ver_conf; - bool tz_disabled; - bool cea_modes_only; - unsigned long max_mode_clock; -}; - -struct mtk_hdmi { - struct drm_bridge bridge; - struct drm_bridge *next_bridge; - struct drm_connector *curr_conn;/* current connector (only valid when 'en= abled') */ - struct device *dev; - const struct mtk_hdmi_conf *conf; - struct phy *phy; - struct device *cec_dev; - struct i2c_adapter *ddc_adpt; - struct clk **clk; - struct drm_display_mode mode; - bool dvi_mode; - struct regmap *sys_regmap; - unsigned int sys_offset; - struct regmap *regs; - struct platform_device *audio_pdev; - struct hdmi_audio_param aud_param; - bool audio_enable; - bool powered; - bool enabled; - hdmi_codec_plugged_cb plugged_cb; - struct device *codec_dev; - struct mutex update_plugged_status_lock; -}; - -static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) -{ - return container_of(b, struct mtk_hdmi, bridge); -} - static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) { regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL, @@ -608,88 +464,6 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *= hdmi, regmap_write(hdmi->regs, GRL_CFG5, val); } =20 -struct hdmi_acr_n { - unsigned int clock; - unsigned int n[3]; -}; - -/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ -static const struct hdmi_acr_n hdmi_rec_n_table[] =3D { - /* Clock, N: 32kHz 44.1kHz 48kHz */ - { 25175, { 4576, 7007, 6864 } }, - { 74176, { 11648, 17836, 11648 } }, - { 148352, { 11648, 8918, 5824 } }, - { 296703, { 5824, 4459, 5824 } }, - { 297000, { 3072, 4704, 5120 } }, - { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ -}; - -/** - * hdmi_recommended_n() - Return N value recommended by HDMI specification - * @freq: audio sample rate in Hz - * @clock: rounded TMDS clock in kHz - */ -static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clo= ck) -{ - const struct hdmi_acr_n *recommended; - unsigned int i; - - for (i =3D 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { - if (clock =3D=3D hdmi_rec_n_table[i].clock) - break; - } - recommended =3D hdmi_rec_n_table + i; - - switch (freq) { - case 32000: - return recommended->n[0]; - case 44100: - return recommended->n[1]; - case 48000: - return recommended->n[2]; - case 88200: - return recommended->n[1] * 2; - case 96000: - return recommended->n[2] * 2; - case 176400: - return recommended->n[1] * 4; - case 192000: - return recommended->n[2] * 4; - default: - return (128 * freq) / 1000; - } -} - -static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) -{ - switch (clock) { - case 25175: - return 25174825; /* 25.2/1.001 MHz */ - case 74176: - return 74175824; /* 74.25/1.001 MHz */ - case 148352: - return 148351648; /* 148.5/1.001 MHz */ - case 296703: - return 296703297; /* 297/1.001 MHz */ - default: - return clock * 1000; - } -} - -static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, - unsigned int tmds_clock, unsigned int n) -{ - return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, - 128 * audio_sample_rate); -} - -static void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock, - unsigned int *n, unsigned int *cts) -{ - *n =3D hdmi_recommended_n(sample_rate, clock); - *cts =3D hdmi_expected_cts(sample_rate, clock, *n); -} - static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, unsigned int cts) { @@ -1080,21 +854,6 @@ static const char * const mtk_hdmi_clk_names[MTK_HDMI= _CLK_COUNT] =3D { [MTK_HDMI_CLK_AUD_SPDIF] =3D "spdif", }; =20 -static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node = *np, - const char * const *clock_names, size_t num_clocks) -{ - int i; - - for (i =3D 0; i < num_clocks; i++) { - hdmi->clk[i] =3D of_clk_get_by_name(np, clock_names[i]); - - if (IS_ERR(hdmi->clk[i])) - return PTR_ERR(hdmi->clk[i]); - } - - return 0; -} - static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) { int ret; @@ -1239,13 +998,6 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *= bridge, return 0; } =20 -static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - return true; -} - static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -1277,28 +1029,6 @@ static void mtk_hdmi_bridge_atomic_post_disable(stru= ct drm_bridge *bridge, hdmi->powered =3D false; } =20 -static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); - - dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", - adjusted_mode->name, adjusted_mode->hdisplay); - dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", - adjusted_mode->hsync_start, adjusted_mode->hsync_end, - adjusted_mode->htotal); - dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", - adjusted_mode->hskew, adjusted_mode->vdisplay); - dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", - adjusted_mode->vsync_start, adjusted_mode->vsync_end, - adjusted_mode->vtotal); - dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", - adjusted_mode->vscan, adjusted_mode->flags); - - drm_mode_copy(&hdmi->mode, adjusted_mode); -} - static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -1354,164 +1084,10 @@ static const struct drm_bridge_funcs mtk_hdmi_brid= ge_funcs =3D { .edid_read =3D mtk_hdmi_bridge_edid_read, }; =20 -static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev,= struct device_node *np) -{ - struct platform_device *cec_pdev; - struct device_node *cec_np; - - /* The CEC module handles HDMI hotplug detection */ - cec_np =3D of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); - if (!cec_np) - return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n"); - - cec_pdev =3D of_find_device_by_node(cec_np); - if (!cec_pdev) { - dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", - cec_np); - of_node_put(cec_np); - return -EPROBE_DEFER; - } - of_node_put(cec_np); - - /* - * The mediatek,syscon-hdmi property contains a phandle link to the - * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG - * registers it contains. - */ - hdmi->sys_regmap =3D syscon_regmap_lookup_by_phandle_args(np, "mediatek,s= yscon-hdmi", - 1, &hdmi->sys_offset); - if (IS_ERR(hdmi->sys_regmap)) - return dev_err_probe(dev, PTR_ERR(hdmi->sys_regmap), - "Failed to get system configuration registers\n"); - - hdmi->cec_dev =3D &cec_pdev->dev; - return 0; -} - -static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_= device *pdev, - const char * const *clk_names, size_t num_clocks) -{ - struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; - struct device_node *remote, *i2c_np; - int ret; - - ret =3D mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks); - if (ret) - return dev_err_probe(dev, ret, "Failed to get clocks\n"); - - hdmi->regs =3D device_node_to_regmap(dev->of_node); - if (IS_ERR(hdmi->regs)) - return PTR_ERR(hdmi->regs); - - remote =3D of_graph_get_remote_node(np, 1, 0); - if (!remote) - return -EINVAL; - - if (!of_device_is_compatible(remote, "hdmi-connector")) { - hdmi->next_bridge =3D of_drm_find_bridge(remote); - if (!hdmi->next_bridge) { - dev_err(dev, "Waiting for external bridge\n"); - of_node_put(remote); - return -EPROBE_DEFER; - } - } - - i2c_np =3D of_parse_phandle(remote, "ddc-i2c-bus", 0); - of_node_put(remote); - if (!i2c_np) - return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n"); - - hdmi->ddc_adpt =3D of_find_i2c_adapter_by_node(i2c_np); - of_node_put(i2c_np); - if (!hdmi->ddc_adpt) - return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by nod= e\n"); - - ret =3D mtk_hdmi_get_cec_dev(hdmi, dev, np); - if (ret) - return ret; - - return 0; -} - /* * HDMI audio codec callbacks */ =20 -static int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, - struct hdmi_codec_daifmt *daifmt, - struct hdmi_codec_params *params) -{ - struct hdmi_audio_param aud_params =3D { 0 }; - unsigned int chan =3D params->cea.channels; - - dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, - params->sample_rate, params->sample_width, chan); - - if (!hdmi->bridge.encoder) - return -ENODEV; - - switch (chan) { - case 2: - aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_2_0; - break; - case 4: - aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_4_0; - break; - case 6: - aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_5_1; - break; - case 8: - aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_7_1; - break; - default: - dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); - return -EINVAL; - } - - switch (params->sample_rate) { - case 32000: - case 44100: - case 48000: - case 88200: - case 96000: - case 176400: - case 192000: - break; - default: - dev_err(hdmi->dev, "rate[%d] not supported!\n", - params->sample_rate); - return -EINVAL; - } - - switch (daifmt->fmt) { - case HDMI_I2S: - aud_params.aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; - aud_params.aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; - aud_params.aud_input_type =3D HDMI_AUD_INPUT_I2S; - aud_params.aud_i2s_fmt =3D HDMI_I2S_MODE_I2S_24BIT; - aud_params.aud_mclk =3D HDMI_AUD_MCLK_128FS; - break; - case HDMI_SPDIF: - aud_params.aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; - aud_params.aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; - aud_params.aud_input_type =3D HDMI_AUD_INPUT_SPDIF; - break; - default: - dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, - daifmt->fmt); - return -EINVAL; - } - memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params)); - memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params)); - - dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", - aud_params.aud_codec, aud_params.aud_input_type, - aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate); - - return 0; -} - static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, struct hdmi_codec_daifmt *daifmt, struct hdmi_codec_params *params) @@ -1559,26 +1135,6 @@ mtk_hdmi_audio_mute(struct device *dev, void *data, return 0; } =20 -static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t = *buf, size_t len) -{ - struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); - - if (hdmi->enabled) - memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len)= ); - else - memset(buf, 0, len); - return 0; -} - -static void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_code= c_plugged_cb fn, - struct device *codec_dev) -{ - mutex_lock(&hdmi->update_plugged_status_lock); - hdmi->plugged_cb =3D fn; - hdmi->codec_dev =3D codec_dev; - mutex_unlock(&hdmi->update_plugged_status_lock); -} - static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, hdmi_codec_plugged_cb fn, struct device *codec_dev) @@ -1600,105 +1156,21 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_= codec_ops =3D { .hook_plugged_cb =3D mtk_hdmi_audio_hook_plugged_cb, }; =20 -static void mtk_hdmi_unregister_audio_driver(void *data) -{ - platform_device_unregister(data); -} - -static int mtk_hdmi_register_audio_driver(struct device *dev) -{ - struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); - struct hdmi_audio_param *aud_param =3D &hdmi->aud_param; - struct hdmi_codec_pdata codec_data =3D { - .ops =3D hdmi->conf->ver_conf->codec_ops, - .max_i2s_channels =3D 2, - .i2s =3D 1, - .data =3D hdmi, - .no_capture_mute =3D 1, - }; - int ret; - - aud_param->aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; - aud_param->aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; - aud_param->aud_input_type =3D HDMI_AUD_INPUT_I2S; - aud_param->aud_i2s_fmt =3D HDMI_I2S_MODE_I2S_24BIT; - aud_param->aud_mclk =3D HDMI_AUD_MCLK_128FS; - aud_param->aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_2_0; - - hdmi->audio_pdev =3D platform_device_register_data(dev, - HDMI_CODEC_DRV_NAME, - PLATFORM_DEVID_AUTO, - &codec_data, - sizeof(codec_data)); - if (IS_ERR(hdmi->audio_pdev)) - return PTR_ERR(hdmi->audio_pdev); - - ret =3D devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver, - hdmi->audio_pdev); - if (ret) - return ret; - - return 0; -} - static int mtk_hdmi_probe(struct platform_device *pdev) { - const struct mtk_hdmi_ver_conf *ver_conf; - const struct mtk_hdmi_conf *hdmi_conf; struct mtk_hdmi *hdmi; - struct device *dev =3D &pdev->dev; int ret; =20 - hdmi_conf =3D of_device_get_match_data(dev); - if (!hdmi_conf) - return -ENODEV; - - ver_conf =3D hdmi_conf->ver_conf; - - hdmi =3D devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge, - ver_conf->bridge_funcs); + hdmi =3D mtk_hdmi_common_probe(pdev); if (IS_ERR(hdmi)) return PTR_ERR(hdmi); =20 - hdmi->dev =3D dev; - hdmi->conf =3D hdmi_conf; - - hdmi->clk =3D devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk),= GFP_KERNEL); - if (!hdmi->clk) - return -ENOMEM; - - ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_name= s, - ver_conf->num_clocks); - if (ret) - return ret; - - hdmi->phy =3D devm_phy_get(dev, "hdmi"); - if (IS_ERR(hdmi->phy)) - return dev_err_probe(dev, PTR_ERR(hdmi->phy), - "Failed to get HDMI PHY\n"); - - mutex_init(&hdmi->update_plugged_status_lock); - platform_set_drvdata(pdev, hdmi); - - ret =3D mtk_hdmi_register_audio_driver(dev); - if (ret) - return dev_err_probe(dev, ret, - "Failed to register audio driver\n"); - - hdmi->bridge.of_node =3D pdev->dev.of_node; - hdmi->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID - | DRM_BRIDGE_OP_HPD; - hdmi->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; - hdmi->bridge.vendor =3D "MediaTek"; - hdmi->bridge.product =3D "On-Chip HDMI"; - - ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); - if (ret) - return dev_err_probe(dev, ret, "Failed to add bridge\n"); + if (!hdmi->cec_dev) + return dev_err_probe(hdmi->dev, -ENODEV, "CEC is required by HDMIv1\n"); =20 ret =3D mtk_hdmi_clk_enable_audio(hdmi); if (ret) - return dev_err_probe(dev, ret, + return dev_err_probe(hdmi->dev, ret, "Failed to enable audio clocks\n"); =20 return 0; @@ -1774,3 +1246,4 @@ MODULE_AUTHOR("Jie Qiu "); MODULE_DESCRIPTION("MediaTek HDMI Driver"); MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS("DRM_MTK_HDMI_V1"); +MODULE_IMPORT_NS("DRM_MTK_HDMI"); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c new file mode 100644 index 0000000000000000000000000000000000000000..f28e63716d7c2e2c6bdf5b28d24= 789bc926d2beb --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_hdmi_common.h" + +struct hdmi_acr_n { + unsigned int clock; + unsigned int n[3]; +}; + +/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ +static const struct hdmi_acr_n hdmi_rec_n_table[] =3D { + /* Clock, N: 32kHz 44.1kHz 48kHz */ + { 25175, { 4576, 7007, 6864 } }, + { 74176, { 11648, 17836, 11648 } }, + { 148352, { 11648, 8918, 5824 } }, + { 296703, { 5824, 4459, 5824 } }, + { 297000, { 3072, 4704, 5120 } }, + { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ +}; + +/** + * hdmi_recommended_n() - Return N value recommended by HDMI specification + * @freq: audio sample rate in Hz + * @clock: rounded TMDS clock in kHz + */ +static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clo= ck) +{ + const struct hdmi_acr_n *recommended; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { + if (clock =3D=3D hdmi_rec_n_table[i].clock) + break; + } + recommended =3D hdmi_rec_n_table + i; + + switch (freq) { + case 32000: + return recommended->n[0]; + case 44100: + return recommended->n[1]; + case 48000: + return recommended->n[2]; + case 88200: + return recommended->n[1] * 2; + case 96000: + return recommended->n[2] * 2; + case 176400: + return recommended->n[1] * 4; + case 192000: + return recommended->n[2] * 4; + default: + return (128 * freq) / 1000; + } +} + +static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) +{ + switch (clock) { + case 25175: + return 25174825; /* 25.2/1.001 MHz */ + case 74176: + return 74175824; /* 74.25/1.001 MHz */ + case 148352: + return 148351648; /* 148.5/1.001 MHz */ + case 296703: + return 296703297; /* 297/1.001 MHz */ + default: + return clock * 1000; + } +} + +static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, + unsigned int tmds_clock, unsigned int n) +{ + return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, + 128 * audio_sample_rate); +} + +void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock, + unsigned int *n, unsigned int *cts) +{ + *n =3D hdmi_recommended_n(sample_rate, clock); + *cts =3D hdmi_expected_cts(sample_rate, clock, *n); +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_get_ncts, "DRM_MTK_HDMI"); + +int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct hdmi_audio_param aud_params =3D { 0 }; + unsigned int chan =3D params->cea.channels; + + dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, + params->sample_rate, params->sample_width, chan); + + if (!hdmi->bridge.encoder) + return -ENODEV; + + switch (chan) { + case 2: + aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_2_0; + break; + case 4: + aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_4_0; + break; + case 6: + aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_5_1; + break; + case 8: + aud_params.aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_7_1; + break; + default: + dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); + return -EINVAL; + } + + switch (params->sample_rate) { + case 32000: + case 44100: + case 48000: + case 88200: + case 96000: + case 176400: + case 192000: + break; + default: + dev_err(hdmi->dev, "rate[%d] not supported!\n", + params->sample_rate); + return -EINVAL; + } + + switch (daifmt->fmt) { + case HDMI_I2S: + aud_params.aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; + aud_params.aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; + aud_params.aud_input_type =3D HDMI_AUD_INPUT_I2S; + aud_params.aud_i2s_fmt =3D HDMI_I2S_MODE_I2S_24BIT; + aud_params.aud_mclk =3D HDMI_AUD_MCLK_128FS; + break; + case HDMI_SPDIF: + aud_params.aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; + aud_params.aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; + aud_params.aud_input_type =3D HDMI_AUD_INPUT_SPDIF; + break; + default: + dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, + daifmt->fmt); + return -EINVAL; + } + memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params)); + memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params)); + + dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", + aud_params.aud_codec, aud_params.aud_input_type, + aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_params, "DRM_MTK_HDMI"); + +int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, s= ize_t len) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + if (hdmi->enabled) + memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len)= ); + else + memset(buf, 0, len); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_get_eld, "DRM_MTK_HDMI"); + +void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugg= ed_cb fn, + struct device *codec_dev) +{ + mutex_lock(&hdmi->update_plugged_status_lock); + hdmi->plugged_cb =3D fn; + hdmi->codec_dev =3D codec_dev; + mutex_unlock(&hdmi->update_plugged_status_lock); +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_set_plugged_cb, "DRM_MTK_HDMI"); + +static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node = *np, + const char * const *clock_names, size_t num_clocks) +{ + int i; + + for (i =3D 0; i < num_clocks; i++) { + hdmi->clk[i] =3D of_clk_get_by_name(np, clock_names[i]); + + if (IS_ERR(hdmi->clk[i])) + return PTR_ERR(hdmi->clk[i]); + } + + return 0; +} + +bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_fixup, "DRM_MTK_HDMI"); + +void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", + adjusted_mode->name, adjusted_mode->hdisplay); + dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", + adjusted_mode->hsync_start, adjusted_mode->hsync_end, + adjusted_mode->htotal); + dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", + adjusted_mode->hskew, adjusted_mode->vdisplay); + dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", + adjusted_mode->vsync_start, adjusted_mode->vsync_end, + adjusted_mode->vtotal); + dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", + adjusted_mode->vscan, adjusted_mode->flags); + + drm_mode_copy(&hdmi->mode, adjusted_mode); +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_set, "DRM_MTK_HDMI"); + +static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev,= struct device_node *np) +{ + struct platform_device *cec_pdev; + struct device_node *cec_np; + + /* The CEC module handles HDMI hotplug detection */ + cec_np =3D of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); + if (!cec_np) + return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n"); + + cec_pdev =3D of_find_device_by_node(cec_np); + if (!cec_pdev) { + dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", + cec_np); + of_node_put(cec_np); + return -EPROBE_DEFER; + } + of_node_put(cec_np); + + /* + * The mediatek,syscon-hdmi property contains a phandle link to the + * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG + * registers it contains. + */ + hdmi->sys_regmap =3D syscon_regmap_lookup_by_phandle_args(np, "mediatek,s= yscon-hdmi", + 1, &hdmi->sys_offset); + if (IS_ERR(hdmi->sys_regmap)) + return dev_err_probe(dev, PTR_ERR(hdmi->sys_regmap), + "Failed to get system configuration registers\n"); + + hdmi->cec_dev =3D &cec_pdev->dev; + return 0; +} + +static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_= device *pdev, + const char * const *clk_names, size_t num_clocks) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *remote, *i2c_np; + int ret; + + ret =3D mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + hdmi->regs =3D device_node_to_regmap(dev->of_node); + if (IS_ERR(hdmi->regs)) + return PTR_ERR(hdmi->regs); + + remote =3D of_graph_get_remote_node(np, 1, 0); + if (!remote) + return -EINVAL; + + if (!of_device_is_compatible(remote, "hdmi-connector")) { + hdmi->next_bridge =3D of_drm_find_bridge(remote); + if (!hdmi->next_bridge) { + dev_err(dev, "Waiting for external bridge\n"); + of_node_put(remote); + return -EPROBE_DEFER; + } + } + + i2c_np =3D of_parse_phandle(remote, "ddc-i2c-bus", 0); + of_node_put(remote); + if (!i2c_np) + return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n"); + + hdmi->ddc_adpt =3D of_find_i2c_adapter_by_node(i2c_np); + of_node_put(i2c_np); + if (!hdmi->ddc_adpt) + return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by nod= e\n"); + + ret =3D mtk_hdmi_get_cec_dev(hdmi, dev, np); + if (ret) + return ret; + + return 0; +} + +static void mtk_hdmi_unregister_audio_driver(void *data) +{ + platform_device_unregister(data); +} + +static int mtk_hdmi_register_audio_driver(struct device *dev) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + struct hdmi_audio_param *aud_param =3D &hdmi->aud_param; + struct hdmi_codec_pdata codec_data =3D { + .ops =3D hdmi->conf->ver_conf->codec_ops, + .max_i2s_channels =3D 2, + .i2s =3D 1, + .data =3D hdmi, + .no_capture_mute =3D 1, + }; + int ret; + + aud_param->aud_codec =3D HDMI_AUDIO_CODING_TYPE_PCM; + aud_param->aud_sample_size =3D HDMI_AUDIO_SAMPLE_SIZE_16; + aud_param->aud_input_type =3D HDMI_AUD_INPUT_I2S; + aud_param->aud_i2s_fmt =3D HDMI_I2S_MODE_I2S_24BIT; + aud_param->aud_mclk =3D HDMI_AUD_MCLK_128FS; + aud_param->aud_input_chan_type =3D HDMI_AUD_CHAN_TYPE_2_0; + + hdmi->audio_pdev =3D platform_device_register_data(dev, + HDMI_CODEC_DRV_NAME, + PLATFORM_DEVID_AUTO, + &codec_data, + sizeof(codec_data)); + if (IS_ERR(hdmi->audio_pdev)) + return PTR_ERR(hdmi->audio_pdev); + + ret =3D devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver, + hdmi->audio_pdev); + if (ret) + return ret; + + return 0; +} + +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev) +{ + const struct mtk_hdmi_ver_conf *ver_conf; + const struct mtk_hdmi_conf *hdmi_conf; + struct device *dev =3D &pdev->dev; + struct mtk_hdmi *hdmi; + int ret; + + hdmi_conf =3D of_device_get_match_data(dev); + if (!hdmi_conf) + return ERR_PTR(-ENODEV); + + ver_conf =3D hdmi_conf->ver_conf; + + hdmi =3D devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge, + ver_conf->bridge_funcs); + if (IS_ERR(hdmi)) + return hdmi; + + hdmi->dev =3D dev; + hdmi->conf =3D hdmi_conf; + + hdmi->clk =3D devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk),= GFP_KERNEL); + if (!hdmi->clk) + return ERR_PTR(-ENOMEM); + + ret =3D mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_name= s, + ver_conf->num_clocks); + if (ret) + return ERR_PTR(ret); + + hdmi->phy =3D devm_phy_get(dev, "hdmi"); + if (IS_ERR(hdmi->phy)) + return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n"); + + mutex_init(&hdmi->update_plugged_status_lock); + platform_set_drvdata(pdev, hdmi); + + ret =3D mtk_hdmi_register_audio_driver(dev); + if (ret) + return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n"= ); + + hdmi->bridge.of_node =3D pdev->dev.of_node; + hdmi->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID + | DRM_BRIDGE_OP_HPD; + hdmi->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; + hdmi->bridge.vendor =3D "MediaTek"; + hdmi->bridge.product =3D "On-Chip HDMI"; + + ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); + if (ret) + return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n"); + + return hdmi; +} +EXPORT_SYMBOL_NS_GPL(mtk_hdmi_common_probe, "DRM_MTK_HDMI"); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("MediaTek HDMI Common Library"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.h new file mode 100644 index 0000000000000000000000000000000000000000..d3de8afff40f2b1a16e87b15785= 9c04109b6da9f --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2024 Collabora Ltd. + */ + +#ifndef _MTK_HDMI_COMMON_H +#define _MTK_HDMI_COMMON_H + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +enum hdmi_aud_input_type { + HDMI_AUD_INPUT_I2S =3D 0, + HDMI_AUD_INPUT_SPDIF, +}; + +enum hdmi_aud_i2s_fmt { + HDMI_I2S_MODE_RJT_24BIT =3D 0, + HDMI_I2S_MODE_RJT_16BIT, + HDMI_I2S_MODE_LJT_24BIT, + HDMI_I2S_MODE_LJT_16BIT, + HDMI_I2S_MODE_I2S_24BIT, + HDMI_I2S_MODE_I2S_16BIT +}; + +enum hdmi_aud_mclk { + HDMI_AUD_MCLK_128FS, + HDMI_AUD_MCLK_192FS, + HDMI_AUD_MCLK_256FS, + HDMI_AUD_MCLK_384FS, + HDMI_AUD_MCLK_512FS, + HDMI_AUD_MCLK_768FS, + HDMI_AUD_MCLK_1152FS, +}; + +enum hdmi_aud_channel_type { + HDMI_AUD_CHAN_TYPE_1_0 =3D 0, + HDMI_AUD_CHAN_TYPE_1_1, + HDMI_AUD_CHAN_TYPE_2_0, + HDMI_AUD_CHAN_TYPE_2_1, + HDMI_AUD_CHAN_TYPE_3_0, + HDMI_AUD_CHAN_TYPE_3_1, + HDMI_AUD_CHAN_TYPE_4_0, + HDMI_AUD_CHAN_TYPE_4_1, + HDMI_AUD_CHAN_TYPE_5_0, + HDMI_AUD_CHAN_TYPE_5_1, + HDMI_AUD_CHAN_TYPE_6_0, + HDMI_AUD_CHAN_TYPE_6_1, + HDMI_AUD_CHAN_TYPE_7_0, + HDMI_AUD_CHAN_TYPE_7_1, + HDMI_AUD_CHAN_TYPE_3_0_LRS, + HDMI_AUD_CHAN_TYPE_3_1_LRS, + HDMI_AUD_CHAN_TYPE_4_0_CLRS, + HDMI_AUD_CHAN_TYPE_4_1_CLRS, + HDMI_AUD_CHAN_TYPE_6_1_CS, + HDMI_AUD_CHAN_TYPE_6_1_CH, + HDMI_AUD_CHAN_TYPE_6_1_OH, + HDMI_AUD_CHAN_TYPE_6_1_CHR, + HDMI_AUD_CHAN_TYPE_7_1_LH_RH, + HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, + HDMI_AUD_CHAN_TYPE_7_1_LC_RC, + HDMI_AUD_CHAN_TYPE_7_1_LW_RW, + HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, + HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, + HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, + HDMI_AUD_CHAN_TYPE_7_1_CS_CH, + HDMI_AUD_CHAN_TYPE_7_1_CS_OH, + HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, + HDMI_AUD_CHAN_TYPE_7_1_CH_OH, + HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, + HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, + HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, + HDMI_AUD_CHAN_TYPE_6_0_CS, + HDMI_AUD_CHAN_TYPE_6_0_CH, + HDMI_AUD_CHAN_TYPE_6_0_OH, + HDMI_AUD_CHAN_TYPE_6_0_CHR, + HDMI_AUD_CHAN_TYPE_7_0_LH_RH, + HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, + HDMI_AUD_CHAN_TYPE_7_0_LC_RC, + HDMI_AUD_CHAN_TYPE_7_0_LW_RW, + HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, + HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, + HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, + HDMI_AUD_CHAN_TYPE_7_0_CS_CH, + HDMI_AUD_CHAN_TYPE_7_0_CS_OH, + HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, + HDMI_AUD_CHAN_TYPE_7_0_CH_OH, + HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, + HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, + HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, + HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, + HDMI_AUD_CHAN_TYPE_UNKNOWN =3D 0xFF +}; + +enum hdmi_aud_channel_swap_type { + HDMI_AUD_SWAP_LR, + HDMI_AUD_SWAP_LFE_CC, + HDMI_AUD_SWAP_LSRS, + HDMI_AUD_SWAP_RLS_RRS, + HDMI_AUD_SWAP_LR_STATUS, +}; + +struct hdmi_audio_param { + enum hdmi_audio_coding_type aud_codec; + enum hdmi_audio_sample_size aud_sample_size; + enum hdmi_aud_input_type aud_input_type; + enum hdmi_aud_i2s_fmt aud_i2s_fmt; + enum hdmi_aud_mclk aud_mclk; + enum hdmi_aud_channel_type aud_input_chan_type; + struct hdmi_codec_params codec_params; +}; + +struct mtk_hdmi_ver_conf { + const struct drm_bridge_funcs *bridge_funcs; + const struct hdmi_codec_ops *codec_ops; + const char * const *mtk_hdmi_clock_names; + int num_clocks; +}; + +struct mtk_hdmi_conf { + const struct mtk_hdmi_ver_conf *ver_conf; + bool tz_disabled; + bool cea_modes_only; + unsigned long max_mode_clock; +}; + +struct mtk_hdmi { + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct drm_connector *curr_conn;/* current connector (only valid when 'en= abled') */ + struct device *dev; + const struct mtk_hdmi_conf *conf; + struct phy *phy; + struct device *cec_dev; + struct i2c_adapter *ddc_adpt; + struct clk **clk; + struct drm_display_mode mode; + bool dvi_mode; + struct regmap *sys_regmap; + unsigned int sys_offset; + struct regmap *regs; + struct platform_device *audio_pdev; + struct hdmi_audio_param aud_param; + bool audio_enable; + bool powered; + bool enabled; + hdmi_codec_plugged_cb plugged_cb; + struct device *codec_dev; + struct mutex update_plugged_status_lock; +}; + +static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) +{ + return container_of(b, struct mtk_hdmi, bridge); +} + + +int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, s= ize_t len); +void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugg= ed_cb fn, + struct device *codec_dev); +int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt = *daifmt, + struct hdmi_codec_params *params); +void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock, + unsigned int *n, unsigned int *cts); +bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); +void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode); +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev); +#endif /* _MTK_HDMI_COMMON_H */ --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CD492741DC for ; Fri, 8 Aug 2025 10:13:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754648011; cv=none; b=MNBfnMU4r5aTnfYPfiVQ3v1V9FNfdPGDTvbmfNHAc7kxeiqJIfKfKQDEckpR9t7w6Eg/lmj5NZcy4aiqBM5SnSKejtJXj9mgKku9mOOavDhLgYjBoU6klZgGAHZtw/iR8jZyydjmbEdExbJjGvTSZNP7gL+7zNbRuBD3l0Lb3gg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-5-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=2372; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=rXYgOuvY4xVEkhoV1yELheebNy9aj44v5phMhyfwfOk=; b=tAqo5e9EJRvOYDGl6xb1rbTZQ9T2ZgVBxc0PRLIydgM8xA1wMP6BNy9P8bMedMmQm2NQjNldM qoygPQNpPCaCNzPmMKFOT0P5KGrgHyxg4wOdveoj3gNQplmEYFIIrdB X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for adding a new driver for HDMIv2, for which CEC is not strictly required, change the of_get_compatible_child() failure error to -ENOTSUPP to be able to differentiate between error conditions in mtk_hdmi_dt_parse_pdata(). In that case, if -ENOTSUPP is returned, this driver will print an informative message saying that CEC support is unavailable, as the devicetree node for that was not found, but after that, function mtk_hdmi_dt_parse_pdata() will not return error to the caller. This will not change functionality of the mtk_hdmi (v1) driver as that is still checking whether CEC is present and, if not, will fail probing with an error saying that CEC is required by HDMIv1. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c index f28e63716d7c2e2c6bdf5b28d24789bc926d2beb..989479fdfe40952762a1b63797b= f602b520dcac5 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -253,12 +253,11 @@ static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi= , struct device *dev, struc /* The CEC module handles HDMI hotplug detection */ cec_np =3D of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); if (!cec_np) - return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n"); + return dev_err_probe(dev, -ENOTSUPP, "Failed to find CEC node\n"); =20 cec_pdev =3D of_find_device_by_node(cec_np); if (!cec_pdev) { - dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", - cec_np); + dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np); of_node_put(cec_np); return -EPROBE_DEFER; } @@ -319,7 +318,9 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdm= i, struct platform_device return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by nod= e\n"); =20 ret =3D mtk_hdmi_get_cec_dev(hdmi, dev, np); - if (ret) + if (ret =3D=3D -ENOTSUPP) + dev_info(dev, "CEC support unavailable: node not found\n"); + else if (ret) return ret; =20 return 0; --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CCDE2741D6 for ; Fri, 8 Aug 2025 10:13:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754648010; 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Fri, 8 Aug 2025 12:13:26 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:16 +0200 Subject: [PATCH v10 06/10] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-6-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=1180; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=WCs5up/nLCv/PFqKtFYLxciy/pVVBfJhFHTlCQDh0VE=; b=JR03wGNtxVt1b7sWoZEQaCW/HE0g3poxLjeRNlW+WL0MbQWm9qli/Bn7bxtdQZDFlGsydIex/ tPy4IIwCnk1Aao60Kr4Rvts2+8drxYXg9jDGSyK5YW3mjzw4mM2Dg5T X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for adding the new HDMI TX v2 IP driver, assign the pointer to the DDC adapter to struct drm_bridge during probe. This commit brings no functional changes. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c index 989479fdfe40952762a1b63797bf602b520dcac5..3b589706d61b1e0e4aa66d0c812= 53b8aeb70c0d3 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -412,7 +412,9 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_= device *pdev) hdmi->bridge.of_node =3D pdev->dev.of_node; hdmi->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; + hdmi->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; + hdmi->bridge.ddc =3D hdmi->ddc_adpt; hdmi->bridge.vendor =3D "MediaTek"; hdmi->bridge.product =3D "On-Chip HDMI"; =20 --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF14D274676 for ; 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Fri, 8 Aug 2025 12:13:27 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:17 +0200 Subject: [PATCH v10 07/10] drm/mediatek: mtk_hdmi_common: Add OP_HDMI if helper funcs assigned Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-7-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=1902; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=VFgIkvVzJkA3pH1XUiXTo9X/HXrtyxZhRMF4j8V/Alg=; b=sqyNimNTio89XgmkCZ4TDb3/csaRfDrYegf5ikdYGugP1m5WGZZS4gkK5UlR4Ux+skPTuwIqw HEZr9kQyaavDWlRWFB+5OG0YiOt2gozRAz0A4ds1Nq7Bkeah2au5Jhb X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno In preparation for adding the HDMI TX v2 driver, and to allow a future modernization of the HDMI v1 one, perform changes that enable the usage of the HDMI Helpers provided by DRM. Check if the HDMI driver provides the function pointers to hdmi_{clear,write}_infoframe used by the HDMI Helper API and, if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops, enabling the drm API to register the bridge as HDMI and to use the HDMI Helper functions. If the hdmi_{write,clear}_infoframe pointers are not assigned, vendor and product strings and HDMI helpers will not be used, hence this commit brings no functional changes to drivers that have not been refactored to use the new helpers. This also means that, in the current state, there is effectively no functional change to mtk_hdmi and its other components. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c index 3b589706d61b1e0e4aa66d0c81253b8aeb70c0d3..be63f33d39bfd4625a5f1edd83c= 873cc20ac0018 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -413,6 +413,10 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform= _device *pdev) hdmi->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; =20 + if (ver_conf->bridge_funcs->hdmi_write_infoframe && + ver_conf->bridge_funcs->hdmi_clear_infoframe) + hdmi->bridge.ops |=3D DRM_BRIDGE_OP_HDMI; + hdmi->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; hdmi->bridge.ddc =3D hdmi->ddc_adpt; hdmi->bridge.vendor =3D "MediaTek"; --=20 2.50.1 From nobody Fri Dec 19 06:36:09 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9023E2749D7 for ; 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Fri, 8 Aug 2025 12:13:28 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:18 +0200 Subject: [PATCH v10 08/10] drm/mediatek: mtk_hdmi_common: Add var to enable interlaced modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-8-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=1712; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=F9CodMOckHFmVHgyCUyMC6SuXyKYebONAVjqKAzRLSY=; b=fnkaGNGHjtzzQnU19IfNtb/NPvgIS2ntw8HOnjzL0wvpsCMrsL/JenMyWPMGo0NmRGALmdFCd yYTpqOaVNfCAoENQpLdzv8C6bJfPAiIPs851JvTJKSjeoi3E+HLE7zb X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno Add an interlace_allowed bool member to struct mtk_hdmi_ver_conf which will be used to signal whether interlaced modes are supported by the bridge (in our case, the HDMI IP), and enable it for HDMIv2. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 + drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c index be63f33d39bfd4625a5f1edd83c873cc20ac0018..38986ab61795c22b5b0659ad2ca= 258b923034a34 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -421,6 +421,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_= device *pdev) hdmi->bridge.ddc =3D hdmi->ddc_adpt; hdmi->bridge.vendor =3D "MediaTek"; hdmi->bridge.product =3D "On-Chip HDMI"; + hdmi->bridge.interlace_allowed =3D ver_conf->interlace_allowed; =20 ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); if (ret) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.h index d3de8afff40f2b1a16e87b157859c04109b6da9f..38d1bdf4c77e4f6684473abec0e= 8c1e6ddc7db0f 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h @@ -131,6 +131,7 @@ struct mtk_hdmi_ver_conf { const struct hdmi_codec_ops *codec_ops; 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Fri, 8 Aug 2025 12:13:29 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:19 +0200 Subject: [PATCH v10 09/10] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-9-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=69998; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=f1NvyUS8uoDujGEdcUkEG5AFDVWFoRPs/uojZBfeKNQ=; b=+djdcfpNrtRolA7A397pFPXjQuoSxLMYmjaS+YynyxLtrRSNzNKlBqMuU4LRBmgQZf8KRifdT 44NF06I9o8zD6eCcaoPKFqPqrOod+A0iEMxMGX4uy+rbVjwM/OeJgD/ X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs found in MediaTek's MT8195, MT8188 SoC and their variants, and including support for display modes up to 4k60 and for HDMI Audio, as per the HDMI 2.0 spec. HDCP and CEC functionalities are also supported by this hardware, but are not included in this commit and that also poses a slight difference between the V2 and V1 controllers in how they handle Hotplug Detection (HPD). While the v1 controller was using the CEC controller to check HDMI cable connection and disconnection, in this driver the v2 one does not. This is due to the fact that on parts with v2 designs, like the MT8195 SoC, there is one CEC controller shared between the HDMI Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually adding support to use the CEC HW to wake up the HDMI controllers it is necessary to have support for one TX, one RX *and* for both at the same time. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/Kconfig | 7 + drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 4 + drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 9 + drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 395 ++++++++ drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h | 263 +++++ drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 1398 +++++++++++++++++++++++= ++++ 7 files changed, 2078 insertions(+) diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kc= onfig index 994b48b82d447c47391122e6ff2d139edb223536..c89ae4ed2c96123684ecd357314= fa2d2ba5a4433 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -45,3 +45,10 @@ config DRM_MEDIATEK_HDMI select DRM_MEDIATEK_HDMI_COMMON help DRM/KMS HDMI driver for Mediatek SoCs + +config DRM_MEDIATEK_HDMI_V2 + tristate "DRM HDMI v2 IP support for MediaTek SoCs" + depends on DRM_MEDIATEK + select DRM_MEDIATEK_HDMI_COMMON + help + DRM/KMS HDMI driver for MediaTek SoCs with HDMIv2 IP diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index 78cf2d4fc85ff444b936a6b705d86a3ec7ff1574..e0ac49b07d5050110f250967e65= a87f21decc8cb 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -25,5 +25,7 @@ obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) +=3D mtk_hdmi_comm= on.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_cec.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_hdmi.o obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mtk_hdmi_ddc.o +obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) +=3D mtk_hdmi_v2.o +obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) +=3D mtk_hdmi_ddc_v2.o =20 obj-$(CONFIG_DRM_MEDIATEK_DP) +=3D mtk_dp.o diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.c index 38986ab61795c22b5b0659ad2ca258b923034a34..9cd7add3dd949e2920c876f7bcf= 990350c42d215 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c @@ -290,6 +290,10 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hd= mi, struct platform_device if (ret) return dev_err_probe(dev, ret, "Failed to get clocks\n"); =20 + hdmi->irq =3D platform_get_irq(pdev, 0); + if (!hdmi->irq) + return hdmi->irq; + hdmi->regs =3D device_node_to_regmap(dev->of_node); if (IS_ERR(hdmi->regs)) return PTR_ERR(hdmi->regs); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/m= ediatek/mtk_hdmi_common.h index 38d1bdf4c77e4f6684473abec0e8c1e6ddc7db0f..de5e064585f85d9eb2e447f2d18= 432513d60d2d8 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h @@ -126,6 +126,12 @@ struct hdmi_audio_param { struct hdmi_codec_params codec_params; }; =20 +enum hdmi_hpd_state { + HDMI_PLUG_OUT =3D 0, + HDMI_PLUG_IN_AND_SINK_POWER_ON, + HDMI_PLUG_IN_ONLY, +}; + struct mtk_hdmi_ver_conf { const struct drm_bridge_funcs *bridge_funcs; const struct hdmi_codec_ops *codec_ops; @@ -139,6 +145,7 @@ struct mtk_hdmi_conf { bool tz_disabled; bool cea_modes_only; unsigned long max_mode_clock; + u32 reg_hdmi_tx_cfg; }; =20 struct mtk_hdmi { @@ -161,6 +168,8 @@ struct mtk_hdmi { bool audio_enable; bool powered; bool enabled; + unsigned int irq; + enum hdmi_hpd_state hpd; hdmi_codec_plugged_cb plugged_cb; struct device *codec_dev; struct mutex update_plugged_status_lock; diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_ddc_v2.c new file mode 100644 index 0000000000000000000000000000000000000000..227705a6409ab40b0317df35744= 53252b7f63b33 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek HDMI v2 Display Data Channel Driver + * + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2021 BayLibre, SAS + * Copyright (c) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mtk_hdmi_common.h" +#include "mtk_hdmi_regs_v2.h" + +#define DDC2_DLY_CNT 572 /* BIM=3D208M/(v*4) =3D 90Khz */ +#define DDC2_DLY_CNT_EDID 832 /* BIM=3D208M/(v*4) =3D 62.5Khz */ +#define SI2C_ADDR_READ 0xf4 +#define SCDC_I2C_SLAVE_ADDRESS 0x54 + +struct mtk_hdmi_ddc { + struct device *dev; + void __iomem *regs; + struct clk *clk; + struct i2c_adapter adap; +}; + +static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc) +{ + u32 val; + + regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val); + if (val & DDC_I2C_BUS_LOW) { + regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL)); + usleep_range(250, 300); + } + + if (val & DDC_I2C_NO_ACK) { + u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status; + + regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl); + regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl); + regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status); + } + + if (val & DDC_I2C_NO_ACK) + return -EIO; + + return 0; +} + +static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id, + u16 offset_id, u8 *wr_data) +{ + u32 val; + int ret; + + /* If down, rise bus for write operation */ + mtk_ddc_check_and_rise_low_bus(ddc); + + regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT, + FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT)); + + if (wr_data) { + regmap_write(ddc->regs, SI2C_CTRL, + FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | + FIELD_PREP(SI2C_WDATA, *wr_data) | + SI2C_WR); + } + + regmap_write(ddc->regs, DDC_CTRL, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) | + FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data =3D=3D NULL ? 0 : 1) | + FIELD_PREP(DDC_CTRL_OFFSET, offset_id) | + FIELD_PREP(DDC_CTRL_ADDR, addr_id)); + usleep_range(1000, 1250); + + ret =3D regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val, + !(val & DDC_I2C_IN_PROG), 500, 1000); + if (ret) { + dev_err(ddc->dev, "DDC I2C write timeout\n"); + return ret; + } + + /* The I2C bus might be down after WR operation: rise it again */ + ret =3D mtk_ddc_check_and_rise_low_bus(ddc); + if (ret) { + dev_err(ddc->dev, "Error during write operation: No ACK\n"); + return ret; + } + + return 0; +} + +static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev, + u8 addr, u8 *puc_value, u16 data_cnt) +{ + u16 dly_cnt, i, loop_counter, temp_length, uc_idx; + u32 rem, uc_read_count, val; + int ret; + + mtk_ddc_check_and_rise_low_bus(ddc); + + regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO)); + + if (data_cnt >=3D 16) { + temp_length =3D 16; + loop_counter =3D data_cnt; + + rem =3D do_div(loop_counter, temp_length); + if (rem) + loop_counter++; + } else { + temp_length =3D data_cnt; + loop_counter =3D 1; + } + + if (uc_dev >=3D DDC_ADDR) + dly_cnt =3D DDC2_DLY_CNT_EDID; + else + dly_cnt =3D DDC2_DLY_CNT; + + regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT, + FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt)); + + for (i =3D 0; i < loop_counter; i++) { + rem =3D data_cnt % 16; + + if (i > 0 && i =3D=3D (loop_counter - 1) && rem) + temp_length =3D rem; + + /* 0x51 - 0x53: Flow control */ + if (uc_dev > DDC_ADDR && uc_dev <=3D 0x53) { + regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT, + FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR)); + + regmap_write(ddc->regs, DDC_CTRL, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) | + FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) | + FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) | + FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR)); + } else { + u16 offset; + + if (addr !=3D 0x43) + offset =3D i * 16; + else + offset =3D 0; + + regmap_write(ddc->regs, DDC_CTRL, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) | + FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) | + FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) | + FIELD_PREP(DDC_CTRL_ADDR, uc_dev)); + } + usleep_range(5000, 5500); + + ret =3D regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val, + !(val & DDC_I2C_IN_PROG), 1000, + 500 * (temp_length + 5)); + if (ret) { + dev_err(ddc->dev, "Timeout waiting for DDC I2C\n"); + return ret; + } + + ret =3D mtk_ddc_check_and_rise_low_bus(ddc); + if (ret) { + dev_err(ddc->dev, "Error during read operation: No ACK\n"); + return ret; + } + + for (uc_idx =3D 0; uc_idx < temp_length; uc_idx++) { + unsigned int read_idx =3D i * 16 + uc_idx; + + regmap_write(ddc->regs, SI2C_CTRL, + FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | + SI2C_RD); + + regmap_read(ddc->regs, HPD_DDC_STATUS, &val); + puc_value[read_idx] =3D FIELD_GET(DDC_DATA_OUT, val); + + regmap_write(ddc->regs, SI2C_CTRL, + FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | + SI2C_CONFIRM_READ); + + /* + * If HDMI IP gets reset during EDID read, DDC read + * operation will fail and its delay counter will be + * reset to 400. + */ + regmap_read(ddc->regs, HPD_DDC_CTRL, &val); + if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT) + return 0; + + uc_read_count =3D read_idx + 1; + } + } + if (uc_read_count > U8_MAX) + dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count); + + return uc_read_count; +} + +static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev, + u8 data_addr, u16 data_cnt, u8 *pr_data) +{ + int read_data_cnt; + u16 req_data_cnt; + + if (!data_cnt) { + dev_err(ddc->dev, "Invalid DDCM read request\n"); + return -EINVAL; + } + + req_data_cnt =3D U8_MAX - data_addr + 1; + if (req_data_cnt > data_cnt) + req_data_cnt =3D data_cnt; + + regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN); + + read_data_cnt =3D mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_= data_cnt); + + if (read_data_cnt < 0) + return read_data_cnt; + else if (read_data_cnt !=3D req_data_cnt) + return -EINVAL; + + return 0; +} + +static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev, + u8 data_addr, u16 data_cnt, u8 *pr_data) +{ + int i, ret; + + regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN); + /* + * In case there is no payload data, just do a single write for the + * address only + */ + if (data_cnt =3D=3D 0) + return mtk_ddc_wr_one(ddc, b_dev, data_addr, NULL); + + i =3D 0; + do { + ret =3D mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data + i); + if (ret) + return ret; + } while (++i < data_cnt); + + return 0; +} + +static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_ms= g *msgs, int num) +{ + struct mtk_hdmi_ddc *ddc; + u8 offset =3D 0; + int i, ret; + + ddc =3D adapter->algo_data; + + for (i =3D 0; i < num; i++) { + struct i2c_msg *msg =3D &msgs[i]; + + if (!msg->buf) { + dev_err(ddc->dev, "No message buffer\n"); + return -EINVAL; + } + + if (msg->flags & I2C_M_RD) { + /* + * The underlying DDC hardware always issues a write request + * that assigns the read offset as part of the read operation, + * therefore, use the `offset` value assigned in the previous + * write request from drm_edid + */ + ret =3D mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset, + msg->len, &msg->buf[0]); + if (ret) + return ret; + } else { + /* + * The HW needs the data offset, found in buf[0], in the + * DDC_CTRL register, and each byte of data, starting at + * buf[1], goes in the SI2C_WDATA register. + */ + ret =3D mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0], + msg->len - 1, &msg->buf[1]); + if (ret) + return ret; + + /* + * Store the offset value requested by drm_edid or by + * scdc to use in subsequent read requests. + */ + if ((msg->addr =3D=3D DDC_ADDR || msg->addr =3D=3D SCDC_I2C_SLAVE_ADDRE= SS) && + msg->len =3D=3D 1) { + offset =3D msg->buf[0]; + } + } + } + + return i; +} + +static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm =3D { + .master_xfer =3D mtk_hdmi_ddc_v2_xfer, + .functionality =3D mtk_hdmi_ddc_v2_func, +}; + +static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_hdmi_ddc *ddc; + int ret; + + ddc =3D devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL); + if (!ddc) + return -ENOMEM; + + ddc->dev =3D dev; + ddc->regs =3D device_node_to_regmap(dev->parent->of_node); + if (IS_ERR_OR_NULL(ddc->regs)) + return dev_err_probe(dev, + IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL, + "Cannot get regmap\n"); + + ddc->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(ddc->clk)) + return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n"); + + strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name)); + ddc->adap.owner =3D THIS_MODULE; + ddc->adap.algo =3D &mtk_hdmi_ddc_v2_algorithm; + ddc->adap.retries =3D 3; + ddc->adap.dev.of_node =3D dev->of_node; + ddc->adap.algo_data =3D ddc; + ddc->adap.dev.parent =3D &pdev->dev; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n"); + + pm_runtime_get_sync(dev); + + ret =3D devm_i2c_add_adapter(dev, &ddc->adap); + if (ret < 0) + return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n"); + + platform_set_drvdata(pdev, ddc); + return 0; +} + +static const struct of_device_id mtk_hdmi_ddc_v2_match[] =3D { + { .compatible =3D "mediatek,mt8195-hdmi-ddc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match); + +struct platform_driver mtk_hdmi_ddc_v2_driver =3D { + .probe =3D mtk_hdmi_ddc_v2_probe, + .driver =3D { + .name =3D "mediatek-hdmi-ddc-v2", + .of_match_table =3D mtk_hdmi_ddc_v2_match, + }, +}; +module_platform_driver(mtk_hdmi_ddc_v2_driver); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_AUTHOR("Can Zeng "); +MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h b/drivers/gpu/drm/= mediatek/mtk_hdmi_regs_v2.h new file mode 100644 index 0000000000000000000000000000000000000000..521b35c7e14d37c2189cf9fa5f2= a8660f1cee67f --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2021 BayLibre, SAS + * Copyright (c) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#ifndef _MTK_HDMI_REGS_H +#define _MTK_HDMI_REGS_H + +/* HDMI_TOP Config */ +#define TOP_CFG00 0x000 +#define HDMI2_ON BIT(2) +#define HDMI_MODE_HDMI BIT(3) +#define SCR_ON BIT(4) +#define TMDS_PACK_MODE GENMASK(9, 8) +#define TMDS_PACK_MODE_8BPP 0 +#define TMDS_PACK_MODE_10BPP 1 +#define TMDS_PACK_MODE_12BPP 2 +#define TMDS_PACK_MODE_16BPP 3 +#define DEEPCOLOR_PKT_EN BIT(12) +#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16) +#define HDMI_ABIST_ENABLE BIT(31) +#define TOP_CFG01 0x004 +#define CP_SET_MUTE_EN BIT(0) +#define CP_CLR_MUTE_EN BIT(1) +#define NULL_PKT_EN BIT(2) +#define NULL_PKT_VSYNC_HIGH_EN BIT(3) + +/* HDMI_TOP Audio: Channel Mapping */ +#define TOP_AUD_MAP 0x00c +#define SD0_MAP GENMASK(2, 0) +#define SD1_MAP GENMASK(6, 4) +#define SD2_MAP GENMASK(10, 8) +#define SD3_MAP GENMASK(14, 12) +#define SD4_MAP GENMASK(18, 16) +#define SD5_MAP GENMASK(22, 20) +#define SD6_MAP GENMASK(26, 24) +#define SD7_MAP GENMASK(30, 28) + +/* Auxiliary Video Information (AVI) Infoframe */ +#define TOP_AVI_HEADER 0x024 +#define TOP_AVI_PKT00 0x028 +#define TOP_AVI_PKT01 0x02C +#define TOP_AVI_PKT02 0x030 +#define TOP_AVI_PKT03 0x034 +#define TOP_AVI_PKT04 0x038 +#define TOP_AVI_PKT05 0x03C + +/* Audio Interface Infoframe */ +#define TOP_AIF_HEADER 0x040 +#define TOP_AIF_PKT00 0x044 +#define TOP_AIF_PKT01 0x048 +#define TOP_AIF_PKT02 0x04c +#define TOP_AIF_PKT03 0x050 + +/* Audio SPDIF Infoframe */ +#define TOP_SPDIF_HEADER 0x054 +#define TOP_SPDIF_PKT00 0x058 +#define TOP_SPDIF_PKT01 0x05c +#define TOP_SPDIF_PKT02 0x060 +#define TOP_SPDIF_PKT03 0x064 +#define TOP_SPDIF_PKT04 0x068 +#define TOP_SPDIF_PKT05 0x06c +#define TOP_SPDIF_PKT06 0x070 +#define TOP_SPDIF_PKT07 0x074 + +/* Infoframes Configuration */ +#define TOP_INFO_EN 0x01c +#define AVI_EN BIT(0) +#define SPD_EN BIT(1) +#define AUD_EN BIT(2) +#define CP_EN BIT(5) +#define VSIF_EN BIT(11) +#define AVI_EN_WR BIT(16) +#define SPD_EN_WR BIT(17) +#define AUD_EN_WR BIT(18) +#define CP_EN_WR BIT(21) +#define VSIF_EN_WR BIT(27) +#define TOP_INFO_RPT 0x020 +#define AVI_RPT_EN BIT(0) +#define SPD_RPT_EN BIT(1) +#define AUD_RPT_EN BIT(2) +#define CP_RPT_EN BIT(5) +#define VSIF_RPT_EN BIT(11) + +/* Vendor Specific Infoframe */ +#define TOP_VSIF_HEADER 0x174 +#define TOP_VSIF_PKT00 0x178 +#define TOP_VSIF_PKT01 0x17c +#define TOP_VSIF_PKT02 0x180 +#define TOP_VSIF_PKT03 0x184 +#define TOP_VSIF_PKT04 0x188 +#define TOP_VSIF_PKT05 0x18c +#define TOP_VSIF_PKT06 0x190 +#define TOP_VSIF_PKT07 0x194 + +/* HDMI_TOP Misc */ +#define TOP_MISC_CTLR 0x1a4 +#define DEEP_COLOR_ADD BIT(4) + +/* Hardware interrupts */ +#define TOP_INT_STA00 0x1a8 +#define TOP_INT_ENABLE00 0x1b0 +#define HTPLG_R_INT BIT(0) +#define HTPLG_F_INT BIT(1) +#define PORD_R_INT BIT(2) +#define PORD_F_INT BIT(3) +#define HDMI_VSYNC_INT BIT(4) +#define HDMI_AUDIO_INT BIT(5) +#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25) +#define TOP_INT_ENABLE01 0x1b4 +#define TOP_INT_CLR00 0x1b8 +#define TOP_INT_CLR01 0x1bc + + +/* Video Mute */ +#define TOP_VMUTE_CFG1 0x1c8 +#define REG_VMUTE_EN BIT(16) + +/* HDMI Audio IP */ +#define AIP_CTRL 0x400 +#define CTS_SW_SEL BIT(0) +#define CTS_REQ_EN BIT(1) +#define MCLK_EN BIT(2) +#define NO_MCLK_CTSGEN_SEL BIT(3) +#define AUD_IN_EN BIT(8) +#define AUD_SEL_OWRT BIT(9) +#define SPDIF_EN BIT(13) +#define HBRA_ON BIT(14) +#define DSD_EN BIT(15) +#define I2S_EN GENMASK(19, 16) +#define HBR_FROM_SPDIF BIT(20) +#define CTS_CAL_N4 BIT(23) +#define SPDIF_INTERNAL_MODULE BIT(24) +#define AIP_N_VAL 0x404 +#define AIP_CTS_SVAL 0x408 +#define AIP_SPDIF_CTRL 0x40c +#define WR_1UI_LOCK BIT(0) +#define FS_OVERRIDE_WRITE BIT(1) +#define WR_2UI_LOCK BIT(2) +#define MAX_1UI_WRITE GENMASK(15, 8) +#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16) +#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20) +#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1) +#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16) +#define AUD_ERR_THRESH GENMASK(29, 24) +#define I2S2DSD_EN BIT(30) +#define AIP_I2S_CTRL 0x410 +#define FIFO0_MAP GENMASK(1, 0) +#define FIFO1_MAP GENMASK(3, 2) +#define FIFO2_MAP GENMASK(5, 4) +#define FIFO3_MAP GENMASK(7, 6) +#define I2S_1ST_BIT_NOSHIFT BIT(8) +#define I2S_DATA_DIR_LSB BIT(9) +#define JUSTIFY_RIGHT BIT(10) +#define WS_HIGH BIT(11) +#define VBIT_COMPRESSED BIT(12) +#define CBIT_ORDER_SAME BIT(13) +#define SCK_EDGE_RISE BIT(14) +#define AIP_I2S_CHST0 0x414 +#define AIP_I2S_CHST1 0x418 +#define AIP_TXCTRL 0x424 +#define RST4AUDIO BIT(0) +#define RST4AUDIO_FIFO BIT(1) +#define RST4AUDIO_ACR BIT(2) +#define AUD_LAYOUT_1 BIT(4) +#define AUD_MUTE_FIFO_EN BIT(5) +#define AUD_PACKET_DROP BIT(6) +#define DSD_MUTE_EN BIT(7) +#define AIP_TPI_CTRL 0x428 +#define TPI_AUDIO_LOOKUP_EN BIT(2) + +/* Video downsampling configuration */ +#define VID_DOWNSAMPLE_CONFIG 0x8d0 +#define C444_C422_CONFIG_ENABLE BIT(0) +#define C422_C420_CONFIG_ENABLE BIT(4) +#define C422_C420_CONFIG_BYPASS BIT(5) +#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6) +#define VID_OUT_FORMAT 0x8fc +#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10) + +/* HDCP registers */ +#define HDCP_TOP_CTRL 0xc00 +#define HDCP2X_CTRL_0 0xc20 +#define HDCP2X_EN BIT(0) +#define HDCP2X_ENCRYPT_EN BIT(7) +#define HDCP2X_HPD_OVR BIT(10) +#define HDCP2X_HPD_SW BIT(11) +#define HDCP2X_POL_CTRL 0xc54 +#define HDCP2X_DIS_POLL_EN BIT(16) +#define HDCP1X_CTRL 0xcd0 +#define HDCP1X_ENC_EN BIT(6) + +/* HDMI DDC registers */ +#define HPD_DDC_CTRL 0xc08 +#define HPD_DDC_DELAY_CNT GENMASK(31, 16) +#define HPD_DDC_HPD_DBNC_EN BIT(2) +#define HPD_DDC_PORD_DBNC_EN BIT(3) +#define DDC_CTRL 0xc10 +#define DDC_CTRL_ADDR GENMASK(7, 1) +#define DDC_CTRL_OFFSET GENMASK(15, 8) +#define DDC_CTRL_DIN_CNT GENMASK(25, 16) +#define DDC_CTRL_CMD GENMASK(31, 28) +#define SCDC_CTRL 0xc18 +#define SCDC_DDC_SEGMENT GENMASK(15, 8) +#define HPD_DDC_STATUS 0xc60 +#define HPD_STATE GENMASK(1, 0) +#define HPD_STATE_CONNECTED 2 +#define HPD_PIN_STA BIT(4) +#define PORD_PIN_STA BIT(5) +#define DDC_I2C_IN_PROG BIT(13) +#define DDC_DATA_OUT GENMASK(23, 16) +#define SI2C_CTRL 0xcac +#define SI2C_WR BIT(0) +#define SI2C_RD BIT(1) +#define SI2C_CONFIRM_READ BIT(2) +#define SI2C_WDATA GENMASK(15, 8) +#define SI2C_ADDR GENMASK(23, 16) + +/* HDCP DDC registers */ +#define HDCP2X_DDCM_STATUS 0xc68 +#define DDC_I2C_NO_ACK BIT(10) +#define DDC_I2C_BUS_LOW BIT(11) + +/* HDMI TX registers */ +#define HDMITX_CONFIG_MT8188 0xea0 +#define HDMITX_CONFIG_MT8195 0x900 +#define HDMI_YUV420_MODE BIT(10) +#define HDMITX_SW_HPD BIT(29) +#define HDMITX_SW_RSTB BIT(31) + +/** + * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands + * @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte + * @DDC_CMD_READ: Current address read with ACK on last byte + * @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte + * @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte + * @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte + * @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte + * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte + * @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte + * @DDC_CMD_RSVD: Reserved for future use + * @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO + * @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL + * @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction + */ +enum mtk_hdmi_ddc_v2_cmds { + DDC_CMD_READ_NOACK =3D 0x0, + DDC_CMD_READ, + DDC_CMD_SEQ_READ_NOACK, + DDC_CMD_SEQ_READ, + DDC_CMD_ENH_READ_NOACK, + DDC_CMD_ENH_READ, + DDC_CMD_SEQ_WRITE_NOACK, + DDC_CMD_SEQ_WRITE =3D 0x07, + DDC_CMD_CLEAR_FIFO =3D 0x09, + DDC_CMD_CLOCK_SCL =3D 0x0a, + DDC_CMD_ABORT_XFER =3D 0x0f +}; + +#endif /* _MTK_HDMI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/media= tek/mtk_hdmi_v2.c new file mode 100644 index 0000000000000000000000000000000000000000..2e8d8aed3c47417200dd951755c= c2e3ef41df75d --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c @@ -0,0 +1,1398 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek HDMI v2 IP driver + * + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2022 BayLibre, SAS + * Copyright (c) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_hdmi_common.h" +#include "mtk_hdmi_regs_v2.h" + +#define MTK_HDMI_V2_CLOCK_MIN 27000 +#define MTK_HDMI_V2_CLOCK_MAX 594000 + +#define HPD_PORD_HWIRQS (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_= INT) + +enum mtk_hdmi_v2_clk_id { + MTK_HDMI_V2_CLK_HDCP_SEL, + MTK_HDMI_V2_CLK_HDCP_24M_SEL, + MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI, + MTK_HDMI_V2_CLK_HDMI_APB_SEL, + MTK_HDMI_V2_CLK_COUNT, +}; + +const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] =3D { + [MTK_HDMI_V2_CLK_HDMI_APB_SEL] =3D "bus", + [MTK_HDMI_V2_CLK_HDCP_SEL] =3D "hdcp", + [MTK_HDMI_V2_CLK_HDCP_24M_SEL] =3D "hdcp24m", + [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] =3D "hdmi-split", +}; + +static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi) +{ + regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0); + regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0); +} + +static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, = bool enable) +{ + if (enable) + regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); + else + regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); +} + +static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enab= le) +{ + if (enable) { + regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); + } else { + regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); + regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); + regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD= ); + } +} + +static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bo= ol enable) +{ + struct drm_scdc *scdc =3D &hdmi->curr_conn->display_info.hdmi.scdc; + + if (enable) + regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); + else + regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); + + if (scdc->supported) { + if (scdc->scrambling.supported) + drm_scdc_set_scrambling(hdmi->curr_conn, enable); + drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable); + } +} + +static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable) +{ + /* If enabled, sends a black image */ + if (enable) + regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); + else + regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); +} + +static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable) +{ + u32 aip, val; + + if (!enable) { + regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN); + return; + } + + regmap_read(hdmi->regs, AIP_CTRL, &aip); + + val =3D AUD_MUTE_FIFO_EN; + if (aip & DSD_EN) + val |=3D DSD_MUTE_EN; + + regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val); +} + +static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi) +{ + regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB= ); + udelay(5); + regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); +} + +static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len) +{ + unsigned short i; + u32 val =3D 0; + + for (i =3D 0; i < len; i++) + val |=3D buffer[i] << (i * 8); + + return val; +} + +static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, co= nst u8 *buffer) +{ + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); + + regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&bu= ffer[0], 3)); + regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buf= fer[3], 3)); + regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buf= fer[7], 2)); + regmap_write(hdmi->regs, TOP_AIF_PKT02, 0); + regmap_write(hdmi->regs, TOP_AIF_PKT03, 0); + + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); + regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); +} + +static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, cons= t u8 *buffer) +{ + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); + + regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&bu= ffer[0], 3)); + regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buf= fer[3], 4)); + regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buf= fer[7], 3)); + regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buf= fer[10], 4)); + regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buf= fer[14], 3)); + regmap_write(hdmi->regs, TOP_AVI_PKT04, 0); + regmap_write(hdmi->regs, TOP_AVI_PKT05, 0); + + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); + regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); +} + +static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, cons= t u8 *buffer) +{ + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); + + regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&= buffer[0], 3)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&b= uffer[3], 4)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&b= uffer[7], 3)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&b= uffer[10], 4)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&b= uffer[14], 3)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&b= uffer[17], 4)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&b= uffer[21], 3)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&b= uffer[24], 4)); + regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]); + + regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); +} + +static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, c= onst u8 *buffer) +{ + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); + + regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&b= uffer[0], 3)); + regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&bu= ffer[3], 4)); + regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&bu= ffer[7], 2)); + regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0); + regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0); + regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0); + regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0); + regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0); + regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0); + + regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); +} + +static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enabl= e) +{ + u32 val; + + regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val); + + if (enable) { + regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MOD= E); + + val |=3D C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE; + val |=3D C422_C420_CONFIG_OUT_CB_OR_CR; + val &=3D ~C422_C420_CONFIG_BYPASS; + regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); + + regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENAB= LE); + } else { + regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_M= ODE); + + val &=3D ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE); + val &=3D ~C422_C420_CONFIG_OUT_CB_OR_CR; + val |=3D C422_C420_CONFIG_BYPASS; + regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); + + regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_EN= ABLE); + } +} + +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi) +{ + struct hdmi_codec_params *params =3D &hdmi->aud_param.codec_params; + struct hdmi_audio_infoframe frame; + u8 buffer[14]; + ssize_t ret; + + memcpy(&frame, ¶ms->cea, sizeof(frame)); + + ret =3D hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); + if (ret < 0) + return ret; + + mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer); + + return 0; +} + +static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool m= ute) +{ + u32 val; + + regmap_read(hdmi->regs, TOP_CFG01, &val); + val &=3D ~(CP_CLR_MUTE_EN | CP_SET_MUTE_EN); + + if (mute) { + val |=3D CP_SET_MUTE_EN; + val &=3D ~CP_CLR_MUTE_EN; + } else { + val |=3D CP_CLR_MUTE_EN; + val &=3D ~CP_SET_MUTE_EN; + } + regmap_write(hdmi->regs, TOP_CFG01, val); + + regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN); + regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR); +} + +static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable) +{ + if (enable) + regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); + else + regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); +} + +static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi) +{ + u8 *ch_status =3D hdmi->aud_param.codec_params.iec.status; + + /* Only the first 5 to 7 bytes of Channel Status contain useful informati= on */ + regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_= status[0], 4)); + regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_= status[4], 3)); +} + +static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi, + unsigned int sample_rate, + unsigned int clock) +{ + unsigned int n, cts; + + mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts); + + regmap_write(hdmi->regs, AIP_N_VAL, n); + regmap_write(hdmi->regs, AIP_CTS_SVAL, cts); +} + +static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable) +{ + if (enable) + regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); + else + regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); +} + +static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 s= d3, + u8 sd4, u8 sd5, u8 sd6, u8 sd7) +{ + u32 val; + + /* + * Each of the Output Channels (0-7) can be mapped to get their input + * from any of the available Input Channels (0-7): this function + * takes input channel numbers and formats a value that must then + * be written to the TOP_AUD_MAP hardware register by the caller. + */ + val =3D FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1); + val |=3D FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3); + val |=3D FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5); + val |=3D FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7); + + return val; +} + +static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi, + unsigned char chnum, bool dsd_bypass) +{ + u32 channel_map; + + regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD= _EN); + regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN); + + if (dsd_bypass) + channel_map =3D mtk_hdmi_v2_aud_output_channel_map(0, 2, 4, 6, 1, 3, 5, = 7); + else + channel_map =3D mtk_hdmi_v2_aud_output_channel_map(0, 5, 1, 0, 3, 2, 4, = 0); + + regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map); + regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); +} + +static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 = fifo_mapping) +{ + regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, + FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, fifo_mapping); +} + +static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 = chnum) +{ + regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum= )); +} + +static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum,= u8 mapping) +{ + u32 fifo_map; + u8 bdata; + + switch (chnum) { + default: + case 2: + bdata =3D 0x1; + break; + case 3: + bdata =3D 0x3; + break; + case 6: + if (mapping =3D=3D 0x0e) { + bdata =3D 0xf; + break; + } + fallthrough; + case 5: + bdata =3D 0x7; + break; + case 7: + case 8: + bdata =3D 0xf; + break; + } + + /* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */ + fifo_map =3D FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1); + fifo_map |=3D FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3); + mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map); + mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata); + + /* + * Set HDMI Audio packet layout indicator: + * Layout 0 is for two channels + * Layout 1 is for up to eight channels + */ + if (chnum =3D=3D 2) + regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); + else + regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); +} + +static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt) +{ + u32 val; + + regmap_read(hdmi->regs, AIP_I2S_CTRL, &val); + val &=3D ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT); + + switch (fmt) { + case HDMI_I2S_MODE_RJT_24BIT: + case HDMI_I2S_MODE_RJT_16BIT: + val |=3D (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT); + break; + case HDMI_I2S_MODE_LJT_24BIT: + case HDMI_I2S_MODE_LJT_16BIT: + val |=3D (WS_HIGH | I2S_1ST_BIT_NOSHIFT); + break; + case HDMI_I2S_MODE_I2S_24BIT: + case HDMI_I2S_MODE_I2S_16BIT: + default: + break; + } + + regmap_write(hdmi->regs, AIP_I2S_CTRL, val); +} + +static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool = rise) +{ + if (rise) + regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); + else + regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); +} + +static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned= int cbit) +{ + regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit); +} + +static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int v= bit) +{ + /* V bit: 0 for PCM, 1 for Compressed data */ + regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit); +} + +static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsi= gned int is_lsb) +{ + regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb); +} + +static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsign= ed int spdif_i2s) +{ + regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, s= pdif_i2s)); +} + +static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel= _type) +{ + switch (channel_type) { + case HDMI_AUD_CHAN_TYPE_1_1: + case HDMI_AUD_CHAN_TYPE_2_1: + return 0x01; + case HDMI_AUD_CHAN_TYPE_3_0: + return 0x02; + case HDMI_AUD_CHAN_TYPE_3_1: + return 0x03; + case HDMI_AUD_CHAN_TYPE_3_0_LRS: + case HDMI_AUD_CHAN_TYPE_4_0: + return 0x08; + case HDMI_AUD_CHAN_TYPE_5_1: + return 0x0b; + case HDMI_AUD_CHAN_TYPE_4_1_CLRS: + case HDMI_AUD_CHAN_TYPE_6_0: + case HDMI_AUD_CHAN_TYPE_6_0_CS: + case HDMI_AUD_CHAN_TYPE_6_0_CH: + case HDMI_AUD_CHAN_TYPE_6_0_OH: + case HDMI_AUD_CHAN_TYPE_6_0_CHR: + return 0x0e; + case HDMI_AUD_CHAN_TYPE_1_0: + case HDMI_AUD_CHAN_TYPE_2_0: + case HDMI_AUD_CHAN_TYPE_3_1_LRS: + case HDMI_AUD_CHAN_TYPE_4_1: + case HDMI_AUD_CHAN_TYPE_5_0: + case HDMI_AUD_CHAN_TYPE_4_0_CLRS: + case HDMI_AUD_CHAN_TYPE_6_1: + case HDMI_AUD_CHAN_TYPE_6_1_CS: + case HDMI_AUD_CHAN_TYPE_6_1_CH: + case HDMI_AUD_CHAN_TYPE_6_1_OH: + case HDMI_AUD_CHAN_TYPE_6_1_CHR: + case HDMI_AUD_CHAN_TYPE_7_0: + case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: + case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: + case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: + case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: + case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: + case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: + case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: + case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: + case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: + case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: + case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: + case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: + case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: + case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: + case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: + case HDMI_AUD_CHAN_TYPE_7_1: + case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: + case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: + case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: + case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: + case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: + case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: + case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: + case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: + case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: + case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: + case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: + case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: + case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: + case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: + default: + return 0; + } + + return 0; +} + +static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi) +{ + regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, + FIELD_PREP(MAX_2UI_I2S_HI_WRITE, MAX_2UI_I2S_LFE_CC_SWAP)); +} + +static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass) +{ + const u32 hbr_mask =3D SPDIF_EN | DSD_EN | HBRA_ON; + + if (dsd_bypass) { + regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON); + regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN); + } else { + regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN); + regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE); + regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF); + regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4); + } +} + +static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi) +{ + regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK); + regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE); + regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK); + + regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE, + FIELD_PREP(MAX_1UI_WRITE, 4)); + regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE, + FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9)); + regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH, + FIELD_PREP(AUD_ERR_THRESH, 4)); + + regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); +} + +static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi) +{ + struct hdmi_audio_param *aud_param =3D &hdmi->aud_param; + struct hdmi_codec_params *codec_params =3D &aud_param->codec_params; + u8 i2s_ch_map; + u32 out_ch_map; + + /* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1= , etc */ + out_ch_map =3D mtk_hdmi_v2_aud_output_channel_map(0, 1, 2, 3, 4, 5, 6, 7); + regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map); + + regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0); + regmap_clear_bits(hdmi->regs, AIP_CTRL, + SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 | + HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE); + regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1); + + if (aud_param->aud_input_type =3D=3D HDMI_AUD_INPUT_I2S) { + switch (aud_param->aud_codec) { + case HDMI_AUDIO_CODING_TYPE_DTS_HD: + case HDMI_AUDIO_CODING_TYPE_MLP: + mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); + mtk_hdmi_hbr_config(hdmi, true); + break; + case HDMI_AUDIO_CODING_TYPE_DSD: + mtk_hdmi_audio_dsd_config(hdmi, codec_params->channels, 0); + mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, 1); + break; + default: + mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); + mtk_hdmi_i2s_sck_edge_rise(hdmi, true); + mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME); + mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */ + mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */ + mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S); + i2s_ch_map =3D mtk_hdmi_v2_get_i2s_ch_mapping(hdmi, + aud_param->aud_input_chan_type); + mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, i2s_ch_map); + mtk_hdmi_v2_hw_i2s_ch_swap(hdmi); + } + } else { + if (codec_params->sample_rate =3D=3D 768000 && + (aud_param->aud_codec =3D=3D HDMI_AUDIO_CODING_TYPE_DTS_HD || + aud_param->aud_codec =3D=3D HDMI_AUDIO_CODING_TYPE_MLP)) { + mtk_hdmi_hbr_config(hdmi, false); + } else { + mtk_hdmi_v2_hw_spdif_config(hdmi); + mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0); + } + } +} + +static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi= , bool ena) +{ + if (ena) + regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); + else + regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); +} + +static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi) +{ + regmap_set_bits(hdmi->regs, AIP_CTRL, + AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN); + regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN); +} + +static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset) +{ + const u32 arst_bits =3D RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR; + + if (reset) + regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits); + else + regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits); +} + +static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi, + struct drm_display_mode *display_mode) +{ + /* Shut down and reset the HDMI Audio HW to avoid glitching */ + mtk_hdmi_v2_hw_aud_mute(hdmi, true); + mtk_hdmi_v2_hw_aud_enable(hdmi, false); + mtk_hdmi_v2_audio_reset(hdmi, true); + + /* Configure the main hardware params and get out of reset */ + mtk_hdmi_v2_aip_ctrl_init(hdmi); + mtk_hdmi_v2_aud_set_input(hdmi); + mtk_hdmi_v2_hw_aud_set_channel_status(hdmi); + mtk_hdmi_v2_setup_audio_infoframe(hdmi); + mtk_hdmi_v2_hw_audio_input_enable(hdmi, true); + mtk_hdmi_v2_audio_reset(hdmi, false); + + /* Ignore N/CTS packet transmission requests and configure */ + mtk_hdmi_v2_hw_ncts_enable(hdmi, false); + mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rat= e, + display_mode->clock); + + /* Wait for the HW to apply settings */ + usleep_range(25, 50); + + /* Hardware is fully configured: enable TX of N/CTS pkts and unmute */ + mtk_hdmi_v2_hw_ncts_enable(hdmi, true); + mtk_hdmi_v2_hw_aud_enable(hdmi, true); + mtk_hdmi_v2_hw_aud_mute(hdmi, false); +} + +static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi, + struct drm_connector_state *conn_state) +{ + mtk_hdmi_v2_hw_reset(hdmi); + mtk_hdmi_v2_set_sw_hpd(hdmi, true); + udelay(2); + + regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0); + + /* + * Enable HDCP reauthentication interrupt: the HW uses this internally + * for the HPD state machine even if HDCP encryption is not enabled. + */ + regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_I= NT); + + /* Enable hotplug and pord interrupts */ + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); + + /* Force enabling HDCP HPD */ + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); + regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); + + /* Set 8 bits per pixel */ + regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE, + FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP)); + /* Disable generating deepcolor packets */ + regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN); + /* Disable adding deepcolor information to the general packet */ + regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD); + + if (hdmi->curr_conn->display_info.is_hdmi) + regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); + else + regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); + + udelay(5); + mtk_hdmi_v2_hw_vid_mute(hdmi, true); + mtk_hdmi_v2_hw_aud_mute(hdmi, true); + mtk_hdmi_v2_hw_gcp_avmute(hdmi, false); + + regmap_update_bits(hdmi->regs, TOP_CFG01, + NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN); + usleep_range(100, 150); + + /* Enable scrambling if tmds clock is 340MHz or more */ + mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >=3D 340 * KILO); + + switch (conn_state->hdmi.output_format) { + default: + case HDMI_COLORSPACE_RGB: + case HDMI_COLORSPACE_YUV444: + /* Disable YUV420 downsampling for RGB and YUV444 */ + mtk_hdmi_yuv420_downsampling(hdmi, false); + break; + case HDMI_COLORSPACE_YUV422: + /* + * YUV420 downsampling is special and needs a bit of setup + * so we disable everything there before doing anything else. + * + * YUV422 downsampling instead just needs one bit to be set. + */ + mtk_hdmi_yuv420_downsampling(hdmi, false); + regmap_set_bits(hdmi->regs, VID_DOWNSAMPLE_CONFIG, + C444_C422_CONFIG_ENABLE); + break; + case HDMI_COLORSPACE_YUV420: + mtk_hdmi_yuv420_downsampling(hdmi, true); + break; + }; +} + +static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi, + struct drm_connector_state *conn_state, + struct drm_display_mode *mode) +{ + union phy_configure_opts opts =3D { + .dp =3D { .link_rate =3D hdmi->mode.clock * KILO } + }; + int ret; + + ret =3D phy_configure(hdmi->phy, &opts); + if (ret) + dev_err(hdmi->dev, "Setting clock=3D%d failed: %d", mode->clock, ret); + + mtk_hdmi_v2_change_video_resolution(hdmi, conn_state); + mtk_hdmi_v2_aud_output_config(hdmi, mode); +} + +static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi) +{ + int ret; + + ret =3D clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); + if (ret) + return ret; + + ret =3D clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); + if (ret) + goto disable_hdcp_clk; + + ret =3D clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); + if (ret) + goto disable_hdcp_24m_clk; + + ret =3D clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); + if (ret) + goto disable_bus_clk; + + return 0; + +disable_bus_clk: + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); +disable_hdcp_24m_clk: + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); +disable_hdcp_clk: + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); + + return ret; +} + +static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi) +{ + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); + clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); +} + +static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hd= mi) +{ + u8 hpd_pin_sta, pord_pin_sta; + u32 hpd_status; + + regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status); + hpd_pin_sta =3D FIELD_GET(HPD_PIN_STA, hpd_status); + pord_pin_sta =3D FIELD_GET(PORD_PIN_STA, hpd_status); + + /* + * Inform that the cable is plugged in (hpd_pin_sta) so that the + * sink can be powered on by switching the 5V VBUS as required by + * the HDMI spec for reading EDID and for HDMI Audio registers to + * be accessible. + * + * PORD detection succeeds only when the cable is plugged in and + * the sink is powered on: reaching that state means that the + * communication with the sink can be started. + * + * Please note that when the cable is plugged out the HPD pin will + * be the first one to fall, while PORD may still be in rise state + * for a few more milliseconds, so we decide HDMI_PLUG_OUT without + * checking PORD at all (we check only HPD falling for that). + */ + if (hpd_pin_sta && pord_pin_sta) + return HDMI_PLUG_IN_AND_SINK_POWER_ON; + else if (hpd_pin_sta) + return HDMI_PLUG_IN_ONLY; + else + return HDMI_PLUG_OUT; +} + +static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg) +{ + struct mtk_hdmi *hdmi =3D arg; + unsigned int irq_sta; + int ret =3D IRQ_HANDLED; + + regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta); + + /* Handle Hotplug Detection interrupts */ + if (irq_sta & HPD_PORD_HWIRQS) { + /* + * Disable the HPD/PORD IRQs now and until thread done to + * avoid interrupt storm that could happen with bad cables + */ + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); + ret =3D IRQ_WAKE_THREAD; + + /* Clear HPD/PORD irqs to avoid unwanted retriggering */ + regmap_write(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS); + regmap_write(hdmi->regs, TOP_INT_CLR00, 0); + } + + return ret; +} + +static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi) +{ + enum hdmi_hpd_state hpd; + + hpd =3D mtk_hdmi_v2_hpd_pord_status(hdmi); + if (hpd !=3D hdmi->hpd) { + struct drm_encoder *encoder =3D hdmi->bridge.encoder; + + hdmi->hpd =3D hpd; + + if (encoder && encoder->dev) + drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); + } + + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); + return IRQ_HANDLED; +} + +static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg) +{ + struct mtk_hdmi *hdmi =3D arg; + + /* + * Debounce HDMI monitor HPD status. + * Empirical testing shows that 30ms is enough wait + */ + msleep(30); + + return __mtk_hdmi_v2_isr_thread(hdmi); +} + +static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi) +{ + bool was_active =3D pm_runtime_active(hdmi->dev); + int ret; + + ret =3D pm_runtime_resume_and_get(hdmi->dev); + if (ret) { + dev_err(hdmi->dev, "Cannot resume HDMI\n"); + return ret; + } + + ret =3D mtk_hdmi_v2_clk_enable(hdmi); + if (ret) { + pm_runtime_put(hdmi->dev); + return ret; + } + + if (!was_active) { + mtk_hdmi_v2_hw_reset(hdmi); + mtk_hdmi_v2_set_sw_hpd(hdmi, true); + } + + return 0; +} + +static void mtk_hdmi_v2_disable(struct mtk_hdmi *hdmi) +{ + mtk_hdmi_v2_clk_disable(hdmi); + pm_runtime_put_sync(hdmi->dev); +} + +/* + * Bridge callbacks + */ + +static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + int ret; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n"); + return -EINVAL; + } + if (hdmi->next_bridge) { + ret =3D drm_bridge_attach(encoder, hdmi->next_bridge, bridge, flags); + if (ret) + return ret; + } + + ret =3D mtk_hdmi_v2_enable(hdmi); + if (ret) + return ret; + + /* Enable Hotplug and Pord pins internal debouncing */ + regmap_set_bits(hdmi->regs, HPD_DDC_CTRL, + HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN); + + irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN); + enable_irq(hdmi->irq); + + /* + * Check if any HDMI monitor was connected before probing this driver + * and/or attaching the bridge, without debouncing: if so, we want to + * notify the DRM so that we start outputting an image ASAP. + * Note that calling the ISR thread function will also perform a HW + * registers write that enables both the HPD and Pord interrupts. + */ + __mtk_hdmi_v2_isr_thread(hdmi); + + mtk_hdmi_v2_disable(hdmi); + + return 0; +} + +static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + WARN_ON(pm_runtime_active(hdmi->dev)); + + /* The controller is already powered off, just disable irq here */ + disable_irq(hdmi->irq); +} + +static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool = plugged) +{ + mutex_lock(&hdmi->update_plugged_status_lock); + if (hdmi->plugged_cb && hdmi->codec_dev) + hdmi->plugged_cb(hdmi->codec_dev, plugged); + mutex_unlock(&hdmi->update_plugged_status_lock); +} + +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + struct drm_connector_state *conn_state; + union phy_configure_opts opts =3D { + .dp =3D { .link_rate =3D hdmi->mode.clock * KILO } + }; + int ret; + + /* Power on the controller before trying to write to registers */ + ret =3D mtk_hdmi_v2_enable(hdmi); + if (WARN_ON(ret)) + return; + + /* Retrieve the connector through the atomic state */ + hdmi->curr_conn =3D drm_atomic_get_new_connector_for_encoder(state, bridg= e->encoder); + + conn_state =3D drm_atomic_get_new_connector_state(state, hdmi->curr_conn); + if (WARN_ON(!conn_state)) + return; + + /* + * Preconfigure the HDMI controller and the HDMI PHY at pre_enable + * stage to make sure that this IP is ready and clocked before the + * mtk_dpi gets powered on and before it enables the output. + */ + mtk_hdmi_v2_output_set_display_mode(hdmi, conn_state, &hdmi->mode); + + /* Reconfigure phy clock link with appropriate rate */ + phy_configure(hdmi->phy, &opts); + + /* Power on the PHY here to make sure that DPI_HDMI is clocked */ + phy_power_on(hdmi->phy); + + hdmi->powered =3D true; +} + +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + int ret; + + if (WARN_ON(!hdmi->powered)) + return; + + ret =3D drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_con= n, state); + if (ret) + dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret); + + mtk_hdmi_v2_hw_vid_mute(hdmi, false); + + /* signal the connect event to audio codec */ + mtk_hdmi_v2_handle_plugged_change(hdmi, true); + + hdmi->enabled =3D true; +} + +static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + if (!hdmi->enabled) + return; + + mtk_hdmi_v2_hw_gcp_avmute(hdmi, true); + msleep(50); + mtk_hdmi_v2_hw_vid_mute(hdmi, true); + mtk_hdmi_v2_hw_aud_mute(hdmi, true); + msleep(50); + + hdmi->enabled =3D false; +} + +static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + if (!hdmi->powered) + return; + + phy_power_off(hdmi->phy); + hdmi->powered =3D false; + + /* signal the disconnect event to audio codec */ + mtk_hdmi_v2_handle_plugged_change(hdmi, false); + + /* Power off */ + mtk_hdmi_v2_disable(hdmi); +} + +static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_brid= ge *bridge, + struct drm_connector *connector) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + return hdmi->hpd !=3D HDMI_PLUG_OUT ? + connector_status_connected : connector_status_disconnected; +} + +static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_brid= ge *bridge, + struct drm_connector *connector) +{ + return drm_edid_read(connector); +} + +static void mtk_hdmi_v2_hpd_enable(struct drm_bridge *bridge) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + int ret; + + ret =3D mtk_hdmi_v2_enable(hdmi); + if (ret) { + dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret); + return; + } + + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); +} + +static void mtk_hdmi_v2_hpd_disable(struct drm_bridge *bridge) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); + mtk_hdmi_v2_disable(hdmi); +} + +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *= bridge, + const struct drm_display_mode *mode, + unsigned long long tmds_rate) +{ + if (mode->clock < MTK_HDMI_V2_CLOCK_MIN) + return MODE_CLOCK_LOW; + else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX) + return MODE_CLOCK_HIGH; + else + return MODE_OK; +} + +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge, + enum hdmi_infoframe_type type) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + switch (type) { + case HDMI_INFOFRAME_TYPE_AUDIO: + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); + break; + case HDMI_INFOFRAME_TYPE_AVI: + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); + break; + case HDMI_INFOFRAME_TYPE_SPD: + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); + break; + case HDMI_INFOFRAME_TYPE_VENDOR: + regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); + regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); + break; + case HDMI_INFOFRAME_TYPE_DRM: + default: + break; + }; + + return 0; +} + +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge, + enum hdmi_infoframe_type type, + const u8 *buffer, size_t len) +{ + struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); + + switch (type) { + case HDMI_INFOFRAME_TYPE_AUDIO: + mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer); + break; + case HDMI_INFOFRAME_TYPE_AVI: + mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer); + break; + case HDMI_INFOFRAME_TYPE_SPD: + mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer); + break; + case HDMI_INFOFRAME_TYPE_VENDOR: + mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer); + break; + case HDMI_INFOFRAME_TYPE_DRM: + default: + dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type); + break; + }; + + return 0; +} + +static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs =3D { + .attach =3D mtk_hdmi_v2_bridge_attach, + .detach =3D mtk_hdmi_v2_bridge_detach, + .mode_fixup =3D mtk_hdmi_bridge_mode_fixup, + .mode_set =3D mtk_hdmi_bridge_mode_set, + .atomic_pre_enable =3D mtk_hdmi_v2_bridge_pre_enable, + .atomic_enable =3D mtk_hdmi_v2_bridge_enable, + .atomic_disable =3D mtk_hdmi_v2_bridge_disable, + .atomic_post_disable =3D mtk_hdmi_v2_bridge_post_disable, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .detect =3D mtk_hdmi_v2_bridge_detect, + .edid_read =3D mtk_hdmi_v2_bridge_edid_read, + .hpd_enable =3D mtk_hdmi_v2_hpd_enable, + .hpd_disable =3D mtk_hdmi_v2_hpd_disable, + .hdmi_tmds_char_rate_valid =3D mtk_hdmi_v2_hdmi_tmds_char_rate_valid, + .hdmi_clear_infoframe =3D mtk_hdmi_v2_hdmi_clear_infoframe, + .hdmi_write_infoframe =3D mtk_hdmi_v2_hdmi_write_infoframe, +}; + +/* + * HDMI audio codec callbacks + */ +static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *dat= a, + hdmi_codec_plugged_cb fn, + struct device *codec_dev) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + bool plugged; + + if (!hdmi) + return -ENODEV; + + mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev); + plugged =3D (hdmi->hpd =3D=3D HDMI_PLUG_IN_AND_SINK_POWER_ON); + mtk_hdmi_v2_handle_plugged_change(hdmi, plugged); + + return 0; +} + +static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + if (hdmi->audio_enable) { + mtk_hdmi_audio_params(hdmi, daifmt, params); + mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode); + } + return 0; +} + +static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + mtk_hdmi_v2_hw_aud_enable(hdmi, true); + hdmi->audio_enable =3D true; + + return 0; +} + +static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + hdmi->audio_enable =3D false; + mtk_hdmi_v2_hw_aud_enable(hdmi, false); +} + +static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool ena= ble, int dir) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + mtk_hdmi_v2_hw_aud_mute(hdmi, enable); + + return 0; +} + +static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops =3D { + .hw_params =3D mtk_hdmi_v2_audio_hw_params, + .audio_startup =3D mtk_hdmi_v2_audio_startup, + .audio_shutdown =3D mtk_hdmi_v2_audio_shutdown, + .mute_stream =3D mtk_hdmi_v2_audio_mute, + .get_eld =3D mtk_hdmi_audio_get_eld, + .hook_plugged_cb =3D mtk_hdmi_v2_audio_hook_plugged_cb, +}; + +static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + mtk_hdmi_v2_disable(hdmi); + + return 0; +} + +static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev) +{ + struct mtk_hdmi *hdmi =3D dev_get_drvdata(dev); + + return mtk_hdmi_v2_enable(hdmi); +} + +static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi= _v2_resume); + +static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 =3D { + .bridge_funcs =3D &mtk_v2_hdmi_bridge_funcs, + .codec_ops =3D &mtk_hdmi_v2_audio_codec_ops, + .mtk_hdmi_clock_names =3D mtk_hdmi_v2_clk_names, + .num_clocks =3D MTK_HDMI_V2_CLK_COUNT, + .interlace_allowed =3D true, +}; + +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 =3D { + .ver_conf =3D &mtk_hdmi_conf_v2, + .reg_hdmi_tx_cfg =3D HDMITX_CONFIG_MT8188 +}; + +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 =3D { + .ver_conf =3D &mtk_hdmi_conf_v2, + .reg_hdmi_tx_cfg =3D HDMITX_CONFIG_MT8195 +}; + +static int mtk_hdmi_v2_probe(struct platform_device *pdev) +{ + struct mtk_hdmi *hdmi; + int ret; + + /* Populate HDMI sub-devices if present */ + ret =3D devm_of_platform_populate(&pdev->dev); + if (ret) + return ret; + + hdmi =3D mtk_hdmi_common_probe(pdev); + if (IS_ERR(hdmi)) + return PTR_ERR(hdmi); + + hdmi->hpd =3D HDMI_PLUG_OUT; + + /* Disable all HW interrupts at probe stage */ + mtk_hdmi_v2_hwirq_disable(hdmi); + + /* + * In case bootloader leaves HDMI enabled before booting, make + * sure that any interrupt that was left is cleared by setting + * all bits in the INT_CLR registers for all 32+19 interrupts. + */ + regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0)); + regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0)); + + /* Restore interrupt clearing registers to zero */ + regmap_write(hdmi->regs, TOP_INT_CLR00, 0); + regmap_write(hdmi->regs, TOP_INT_CLR01, 0); + + /* + * Install the ISR but keep it disabled: as the interrupts are + * being set up in the .bridge_attach() callback which will + * enable both the right HW IRQs and the ISR. + */ + irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN); + ret =3D devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr, + mtk_hdmi_v2_isr_thread, + IRQ_TYPE_LEVEL_HIGH, + dev_name(&pdev->dev), hdmi); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n"); + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n"); + + return 0; +} + +static void mtk_hdmi_v2_remove(struct platform_device *pdev) +{ + struct mtk_hdmi *hdmi =3D platform_get_drvdata(pdev); + + i2c_put_adapter(hdmi->ddc_adpt); +} + +static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] =3D { + { .compatible =3D "mediatek,mt8188-hdmi-tx", .data =3D &mtk_hdmi_conf_mt8= 188 }, + { .compatible =3D "mediatek,mt8195-hdmi-tx", .data =3D &mtk_hdmi_conf_mt8= 195 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids); + +static struct platform_driver mtk_hdmi_v2_driver =3D { + .probe =3D mtk_hdmi_v2_probe, + .remove =3D mtk_hdmi_v2_remove, + .driver =3D { + .name =3D "mediatek-drm-hdmi-v2", + .of_match_table =3D mtk_drm_hdmi_v2_of_ids, + .pm =3D &mtk_hdmi_v2_pm_ops, + }, +}; +module_platform_driver(mtk_hdmi_v2_driver); + +MODULE_AUTHOR("AngeloGioacchino Del Regno >"); +MODULE_DESCRIPTION("MediaTek HDMIv2 Driver"); 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Fri, 8 Aug 2025 12:13:29 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 08 Aug 2025 12:12:20 +0200 Subject: [PATCH v10 10/10] drm/mediatek: mtk_hdmi_v2: Add debugfs ops and implement ABIST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250808-mediatek-drm-hdmi-v2-v10-10-21ea82eec1f6@collabora.com> References: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> In-Reply-To: <20250808-mediatek-drm-hdmi-v2-v10-0-21ea82eec1f6@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754648002; l=4864; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=59N2cla9Emq1ytbntdF30iQ+szR28dGc6Xg6uqfCh0M=; b=KsUO3c5rhM4Dpkvtprk+n0IaAuO+WVQ3k4TjZj2ZB+L84ltxtsVbudlyKwRKPO6uj/nsV6wez xL3Ax+Ja+MnCi70mKqUAJIOBn0e0d3x90/hONPlDCR2g6XNTSvfhw1E X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: AngeloGioacchino Del Regno Implement the Automated Built-In Self-Test ABIST functionality provided by the HDMIv2 IP and expose it through the "hdmi_abist" debugfs file. Write "1" to this file to activate ABIST, or "0" to deactivate. The ABIST functionality can be used to validate that the HDMI Transmitter itself works and that can output a valid image to the HDMI Display that is connected. This is especially useful when trying to rule out any possible issue that is related to the display pipeline, as the HDMI Tx is always the last component; this means that HDMI ABIST can be used even without prior display controller pipeline configuration. The expected output is a 100% color bar (rainbow) test pattern. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 123 +++++++++++++++++++++++++++++= ++++ 1 file changed, 123 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/media= tek/mtk_hdmi_v2.c index 2e8d8aed3c47417200dd951755cc2e3ef41df75d..c272e1e74b7de03a726402f7729= 6b05c87b24e05 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c @@ -1190,6 +1190,128 @@ static int mtk_hdmi_v2_hdmi_write_infoframe(struct = drm_bridge *bridge, return 0; } =20 +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable) +{ + struct drm_display_mode *mode =3D &hdmi->mode; + int abist_format =3D -EINVAL; + bool interlaced; + + if (!enable) { + regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); + return 0; + } + + if (!mode->hdisplay || !mode->vdisplay) + return -EINVAL; + + interlaced =3D mode->flags & DRM_MODE_FLAG_INTERLACE; + + switch (mode->hdisplay) { + case 720: + if (mode->vdisplay =3D=3D 480) + abist_format =3D 2; + else if (mode->vdisplay =3D=3D 576) + abist_format =3D 11; + break; + case 1280: + if (mode->vdisplay =3D=3D 720) + abist_format =3D 3; + break; + case 1440: + if (mode->vdisplay =3D=3D 480) + abist_format =3D interlaced ? 5 : 9; + else if (mode->vdisplay =3D=3D 576) + abist_format =3D interlaced ? 14 : 18; + break; + case 1920: + if (mode->vdisplay =3D=3D 1080) + abist_format =3D interlaced ? 4 : 10; + break; + case 3840: + if (mode->vdisplay =3D=3D 2160) + abist_format =3D 25; + break; + case 4096: + if (mode->vdisplay =3D=3D 2160) + abist_format =3D 26; + break; + default: + break; + } + if (abist_format < 0) + return abist_format; + + regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT, + FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format)); + regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); + return 0; +} + +static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg) +{ + struct mtk_hdmi *hdmi =3D m->private; + bool en; + u32 val; + int ret; + + if (!hdmi) + return -EINVAL; + + ret =3D regmap_read(hdmi->regs, TOP_CFG00, &val); + if (ret) + return ret; + + en =3D FIELD_GET(HDMI_ABIST_ENABLE, val); + + seq_printf(m, "HDMI Automated Built-In Self Test: %s\n", + en ? "Enabled" : "Disabled"); + + return 0; +} + +static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m =3D file->private_data; + int ret; + u32 en; + + if (!m || !m->private || *offp) + return -EINVAL; + + ret =3D kstrtouint_from_user(ubuf, len, 0, &en); + if (ret) + return ret; + + if (en < 0 || en > 1) + return -EINVAL; + + mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en); + return len; +} + +static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *= file) +{ + return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private); +} + +static const struct file_operations mtk_hdmi_debug_abist_fops =3D { + .owner =3D THIS_MODULE, + .open =3D mtk_hdmi_v2_debug_abist_open, + .read =3D seq_read, + .write =3D mtk_hdmi_v2_debug_abist_write, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct den= try *root) +{ + struct mtk_hdmi *dpi =3D hdmi_ctx_from_bridge(bridge); + + debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_= fops); +} + static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs =3D { .attach =3D mtk_hdmi_v2_bridge_attach, .detach =3D mtk_hdmi_v2_bridge_detach, @@ -1209,6 +1331,7 @@ static const struct drm_bridge_funcs mtk_v2_hdmi_brid= ge_funcs =3D { .hdmi_tmds_char_rate_valid =3D mtk_hdmi_v2_hdmi_tmds_char_rate_valid, .hdmi_clear_infoframe =3D mtk_hdmi_v2_hdmi_clear_infoframe, .hdmi_write_infoframe =3D mtk_hdmi_v2_hdmi_write_infoframe, + .debugfs_init =3D mtk_hdmi_v2_debugfs_init, }; =20 /* --=20 2.50.1