From nobody Sun Oct 5 05:26:34 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D58151DDA18; Thu, 7 Aug 2025 21:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754603082; cv=none; b=mx66fgDJ02LsqYVbLuIn7SxwhP+jghoIq1fy845Gks9ZYOpY/bUgyzcZmSoOpI+jLQ12D35UPA9N64mjoBui2vt7P3Cmq6icrn0HIH2uXZ4oQIks9qaqyKJye5Fm9CXsl9fPqfWob7NOSN9m45Snuhw+0MPm/WsKrGWAt7AMM3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754603082; c=relaxed/simple; bh=+DBg50Szd+rGRxJ8Bc8+14Qwysk4w0Ub9V4nfqyXPng=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=bd/UE3MWTdMMypwkvwm03AnWWCawS9914Q5/vOWtZgKGb+tHrPThwBikLZSKI4CyHHePbxMoqVEnUCSXXTDU99cxdUAablVZI8BVixOas/OsEPcIDnIN5ew9/9Xp6qElDC1SO5Jw6+gMfCso6OTVS9e+UxWIEv8vN8HM2CIilsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qLq4yByf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qLq4yByf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56085C4CEEB; Thu, 7 Aug 2025 21:44:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754603082; bh=+DBg50Szd+rGRxJ8Bc8+14Qwysk4w0Ub9V4nfqyXPng=; h=From:To:Cc:Subject:Date:From; b=qLq4yByfFTTUMIgpVTPav3ckUdC2tFL3Dzf5pr4eGDYayIxoCIYwWyuHmlAjjrlZD b1xOnVNYIvzxUqiQZqxCYc0eerWaXQptmHFRRUpi6XkuswpVCFAAZBVSI0OTmhRo+l yxjmqKSWxg7auAq672/RgiP+IQ1DG9lHe1I12HXCQXhvHlq77ofngFC9mOFF5QFbMn BI1tfcjVZ/theHodpUFFBSAEFVmGGyo6FV0erjfKUrf58HEap+Tl0ZQAk/haAa424S c/MWnspjS81T5bvzGe9eoXyr5Db0o2ASvfE6T26SXl4VToleg6dq2bWuYv3J5kHL3d hlepU1Om+NWiQ== From: "Rob Herring (Arm)" To: Thomas Gleixner , Krzysztof Kozlowski , Conor Dooley , Scott Wood , Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH] dt-bindings: powerpc: Drop duplicate fsl/mpic.txt Date: Thu, 7 Aug 2025 16:44:30 -0500 Message-ID: <20250807214432.4173273-1-robh@kernel.org> X-Mailer: git-send-email 2.47.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The chrp,open-pic binding schema already supports the "fsl,mpic" compatible. A couple of properties are missing, so add them and remove fsl/mpic.txt. Signed-off-by: Rob Herring (Arm) Acked-by: Conor Dooley --- .../interrupt-controller/chrp,open-pic.yaml | 12 + .../devicetree/bindings/powerpc/fsl/mpic.txt | 231 ------------------ 2 files changed, 12 insertions(+), 231 deletions(-) delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/chrp,op= en-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/chrp,o= pen-pic.yaml index f0d9bbd7d510..f748d42d2273 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.= yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.= yaml @@ -42,6 +42,18 @@ properties: description: Indicates the PIC shall not be reset during runtime initi= alization. type: boolean =20 + single-cpu-affinity: + description: + If present, non-IPI interrupts will be routed to a single CPU at a t= ime. + type: boolean + + last-interrupt-source: + description: + Some MPICs do not correctly report the number of hardware sources in= the + global feature registers. This value, if specified, overrides the va= lue + read from MPIC_GREG_FEATURE_LAST_SRC. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Docum= entation/devicetree/bindings/powerpc/fsl/mpic.txt deleted file mode 100644 index dc5744636a57..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ /dev/null @@ -1,231 +0,0 @@ -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Freescale MPIC Interrupt Controller Node -Copyright (C) 2010,2011 Freescale Semiconductor Inc. -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The Freescale MPIC interrupt controller is found on all PowerQUICC -and QorIQ processors and is compatible with the Open PIC. The -notable difference from Open PIC binding is the addition of 2 -additional cells in the interrupt specifier defining interrupt type -information. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Shall include "fsl,mpic". Freescale MPIC - controllers compatible with this binding have Block - Revision Registers BRR1 and BRR2 at offset 0x0 and - 0x10 in the MPIC. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - offset and length of the device's registers within the - CCSR address space. - - - interrupt-controller - Usage: required - Value type: - Definition: Specifies that this node is an interrupt - controller - - - #interrupt-cells - Usage: required - Value type: - Definition: Shall be 2 or 4. A value of 2 means that interrupt - specifiers do not contain the interrupt-type or type-specific - information cells. - - - #address-cells - Usage: required - Value type: - Definition: Shall be 0. - - - pic-no-reset - Usage: optional - Value type: - Definition: The presence of this property specifies that the - MPIC must not be reset by the client program, and that - the boot program has initialized all interrupt source - configuration registers to a sane state-- masked or - directed at other cores. This ensures that the client - program will not receive interrupts for sources not belonging - to the client. The presence of this property also mandates - that any initialization related to interrupt sources shall - be limited to sources explicitly referenced in the device tree. - - - big-endian - Usage: optional - Value type: - If present the MPIC will be assumed to be big-endian. Some - device-trees omit this property on MPIC nodes even when the MPIC= is - in fact big-endian, so certain boards override this property. - - - single-cpu-affinity - Usage: optional - Value type: - If present the MPIC will be assumed to only be able to route - non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC= ). - - - last-interrupt-source - Usage: optional - Value type: - Some MPICs do not correctly report the number of hardware sources - in the global feature registers. If specified, this field will - override the value read from MPIC_GREG_FEATURE_LAST_SRC. - -INTERRUPT SPECIFIER DEFINITION - - Interrupt specifiers consists of 4 cells encoded as - follows: - - <1st-cell> interrupt-number - - Identifies the interrupt source. The meaning - depends on the type of interrupt. - - Note: If the interrupt-type cell is undefined - (i.e. #interrupt-cells =3D 2), this cell - should be interpreted the same as for - interrupt-type 0-- i.e. an external or - normal SoC device interrupt. - - <2nd-cell> level-sense information, encoded as follows: - 0 =3D low-to-high edge triggered - 1 =3D active low level-sensitive - 2 =3D active high level-sensitive - 3 =3D high-to-low edge triggered - - <3rd-cell> interrupt-type - - The following types are supported: - - 0 =3D external or normal SoC device interrupt - - The interrupt-number cell contains - the SoC device interrupt number. The - type-specific cell is undefined. The - interrupt-number is derived from the - MPIC a block of registers referred to as - the "Interrupt Source Configuration Registers". - Each source has 32-bytes of registers - (vector/priority and destination) in this - region. So interrupt 0 is at offset 0x0, - interrupt 1 is at offset 0x20, and so on. - - 1 =3D error interrupt - - The interrupt-number cell contains - the SoC device interrupt number for - the error interrupt. The type-specific - cell identifies the specific error - interrupt number. - - 2 =3D MPIC inter-processor interrupt (IPI) - - The interrupt-number cell identifies - the MPIC IPI number. The type-specific - cell is undefined. - - 3 =3D MPIC timer interrupt - - The interrupt-number cell identifies - the MPIC timer number. The type-specific - cell is undefined. - - <4th-cell> type-specific information - - The type-specific cell is encoded as follows: - - - For interrupt-type 1 (error interrupt), - the type-specific cell contains the - bit number of the error interrupt in the - Error Interrupt Summary Register. - -EXAMPLE 1 - /* - * mpic interrupt controller with 4 cells per specifier - */ - mpic: pic@40000 { - compatible =3D "fsl,mpic"; - interrupt-controller; - #interrupt-cells =3D <4>; - #address-cells =3D <0>; - reg =3D <0x40000 0x40000>; - }; - -EXAMPLE 2 - /* - * The MPC8544 I2C controller node has an internal - * interrupt number of 27. As per the reference manual - * this corresponds to interrupt source configuration - * registers at 0x5_0560. - * - * The interrupt source configuration registers begin - * at 0x5_0000. - * - * To compute the interrupt specifier interrupt number - * - * 0x560 >> 5 =3D 43 - * - * The interrupt source configuration registers begin - * at 0x5_0000, and so the i2c vector/priority registers - * are at 0x5_0560. - */ - i2c@3000 { - #address-cells =3D <1>; - #size-cells =3D <0>; - cell-index =3D <0>; - compatible =3D "fsl-i2c"; - reg =3D <0x3000 0x100>; - interrupts =3D <43 2>; - interrupt-parent =3D <&mpic>; - dfsrr; - }; - - -EXAMPLE 3 - /* - * Definition of a node defining the 4 - * MPIC IPI interrupts. Note the interrupt - * type of 2. - */ - ipi@410a0 { - compatible =3D "fsl,mpic-ipi"; - reg =3D <0x40040 0x10>; - interrupts =3D <0 0 2 0 - 1 0 2 0 - 2 0 2 0 - 3 0 2 0>; - }; - -EXAMPLE 4 - /* - * Definition of a node defining the MPIC - * global timers. Note the interrupt - * type of 3. - */ - timer0: timer@41100 { - compatible =3D "fsl,mpic-global-timer"; - reg =3D <0x41100 0x100 0x41300 4>; - interrupts =3D <0 0 3 0 - 1 0 3 0 - 2 0 3 0 - 3 0 3 0>; - }; - -EXAMPLE 5 - /* - * Definition of an error interrupt (interrupt type 1). - * SoC interrupt number is 16 and the specific error - * interrupt bit in the error interrupt summary register - * is 23. - */ - memory-controller@8000 { - compatible =3D "fsl,p4080-memory-controller"; - reg =3D <0x8000 0x1000>; - interrupts =3D <16 2 1 23>; - }; --=20 2.47.2