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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3b9074sm26786942f8f.17.2025.08.07.09.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Aug 2025 09:44:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH] clk: renesas: cpg-mssr: Add module reset support for RZ/T2H Date: Thu, 7 Aug 2025 17:43:53 +0100 Message-ID: <20250807164353.1543461-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for module reset handling on the RZ/T2H SoC. Unlike earlier CPG/MSSR variants, RZ/T2H uses a unified set of Module Reset Control Registers (MRCR) where both reset and deassert actions are done via read-modify-write (RMW) to the same register. Introduce a new MRCR offset table (mrcr_for_rzt2h) for RZ/T2H and assign it to both reset_regs and reset_clear_regs. For RZ/T2H, set rcdev.nr_resets based on the number of MRCR registers rather than the number of module clocks. Update the reset/assert/deassert/status operations to perform RMW when handling RZ/T2H-specific layout. This enables proper reset sequencing for modules on RZ/T2H without affecting the behavior of other supported SoCs. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/renesas-cpg-mssr.c | 40 ++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index 5ff6ee1f7d4b..d299c2bb6100 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -137,6 +137,22 @@ static const u16 srcr_for_gen4[] =3D { 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, }; =20 +static const u16 mrcr_for_rzt2h[] =3D { + 0x240, /* MRCTLA */ + 0x244, /* Reserved */ + 0x248, /* Reserved */ + 0x24C, /* Reserved */ + 0x250, /* MRCTLE */ + 0x254, /* Reserved */ + 0x258, /* Reserved */ + 0x25C, /* Reserved */ + 0x260, /* MRCTLI */ + 0x264, /* Reserved */ + 0x268, /* Reserved */ + 0x26C, /* Reserved */ + 0x270, /* MRCTLM */ +}; + /* * Software Reset Clearing Register offsets */ @@ -686,12 +702,16 @@ static int cpg_mssr_reset(struct reset_controller_dev= *rcdev, =20 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); =20 + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + bitmask =3D readl(priv->pub.base0 + priv->reset_regs[reg]) | bitmask; /* Reset module */ writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); =20 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ udelay(35); =20 + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + bitmask =3D readl(priv->pub.base0 + priv->reset_clear_regs[reg]) & ~bitm= ask; /* Release module from reset state */ writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); =20 @@ -707,6 +727,8 @@ static int cpg_mssr_assert(struct reset_controller_dev = *rcdev, unsigned long id) =20 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); =20 + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + bitmask =3D readl(priv->pub.base0 + priv->reset_regs[reg]) | bitmask; writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); return 0; } @@ -721,6 +743,8 @@ static int cpg_mssr_deassert(struct reset_controller_de= v *rcdev, =20 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); =20 + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + bitmask =3D readl(priv->pub.base0 + priv->reset_regs[reg]) & ~bitmask; writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); return 0; } @@ -764,7 +788,16 @@ static int cpg_mssr_reset_controller_register(struct c= pg_mssr_priv *priv) priv->rcdev.of_node =3D priv->dev->of_node; priv->rcdev.of_reset_n_cells =3D 1; priv->rcdev.of_xlate =3D cpg_mssr_reset_xlate; - priv->rcdev.nr_resets =3D priv->num_mod_clks; + + /* + * RZ/T2H (and family) has the Module Reset Control Registers + * which allows control resets of certain modules. + * The number of resets is not equal to the number of module clocks. + */ + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + priv->rcdev.nr_resets =3D ARRAY_SIZE(mrcr_for_rzt2h) * 32; + else + priv->rcdev.nr_resets =3D priv->num_mod_clks; return devm_reset_controller_register(priv->dev, &priv->rcdev); } =20 @@ -1166,6 +1199,8 @@ static int __init cpg_mssr_common_init(struct device = *dev, priv->control_regs =3D stbcr; } else if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) { priv->control_regs =3D mstpcr_for_rzt2h; + priv->reset_regs =3D mrcr_for_rzt2h; + priv->reset_clear_regs =3D mrcr_for_rzt2h; } else if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RCAR_GEN4) { priv->status_regs =3D mstpsr_for_gen4; priv->control_regs =3D mstpcr_for_gen4; @@ -1262,8 +1297,7 @@ static int __init cpg_mssr_probe(struct platform_devi= ce *pdev) goto reserve_exit; =20 /* Reset Controller not supported for Standby Control SoCs */ - if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_A || - priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_T2H) + if (priv->reg_layout =3D=3D CLK_REG_LAYOUT_RZ_A) goto reserve_exit; =20 error =3D cpg_mssr_reset_controller_register(priv); --=20 2.50.1