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Thu, 07 Aug 2025 04:24:15 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Inochi Amaoto , Saurabh Sengar , Shradha Gupta , Jonathan Cameron , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 1/4] genirq: Add irq_chip_(startup/shutdown)_parent Date: Thu, 7 Aug 2025 19:23:22 +0800 Message-ID: <20250807112326.748740-2-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250807112326.748740-1-inochiama@gmail.com> References: <20250807112326.748740-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helper irq_chip_startup_parent and irq_chip_shutdown_parent. The helper implement the default behavior in case irq_startup or irq_shutdown is not implemented for the parent interrupt chip, which will fallback to irq_chip_enable_parent or irq_chip_disable_parent if not available. Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- include/linux/irq.h | 2 ++ kernel/irq/chip.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 1d6b606a81ef..890e1371f5d4 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -669,6 +669,8 @@ extern int irq_chip_set_parent_state(struct irq_data *d= ata, extern int irq_chip_get_parent_state(struct irq_data *data, enum irqchip_irq_state which, bool *state); +extern void irq_chip_shutdown_parent(struct irq_data *data); +extern unsigned int irq_chip_startup_parent(struct irq_data *data); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 0d0276378c70..3ffa0d80ddd1 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1259,6 +1259,43 @@ int irq_chip_get_parent_state(struct irq_data *data, } EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); =20 +/** + * irq_chip_shutdown_parent - Shutdown the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_shutdown() callback of the parent if available or falls + * back to irq_chip_disable_parent(). + */ +void irq_chip_shutdown_parent(struct irq_data *data) +{ + struct irq_data *parent =3D data->parent_data; + + if (parent->chip->irq_shutdown) + parent->chip->irq_shutdown(parent); + else + irq_chip_disable_parent(data); +} +EXPORT_SYMBOL_GPL(irq_chip_shutdown_parent); + +/** + * irq_chip_startup_parent - Startup the parent interrupt + * @data: Pointer to interrupt specific data + * + * Invokes the irq_startup() callback of the parent if available or falls + * back to irq_chip_enable_parent(). + */ +unsigned int irq_chip_startup_parent(struct irq_data *data) +{ + struct irq_data *parent =3D data->parent_data; + + if (parent->chip->irq_startup) + return parent->chip->irq_startup(parent); + + irq_chip_enable_parent(data); + return 0; +} +EXPORT_SYMBOL_GPL(irq_chip_startup_parent); + /** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmas= k if * NULL) --=20 2.50.1 From nobody Sun Oct 5 07:20:28 2025 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07CCA2798E3; Thu, 7 Aug 2025 11:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754565864; cv=none; b=YGQyApCVDemV2f1dRVxkGypnORa8ALXZwOrzwRuC3icvYELjrR8ywzj5qW8UsXbnCwHIRy4dmKwZL0aGDM7XCL1yo6aMGzfqiSbWnmQH3/cSqZodoE0thMpoLAfa5ssui2bRvHyvBLxHjgu25LRI/WhWMMi6sRfB3DxNnJR/JgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754565864; c=relaxed/simple; bh=mgFje9VCuxYaDkRn2eUEOdlrR0FNGsyIAb/QQlxEqHI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Thu, 07 Aug 2025 04:24:20 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Bjorn Helgaas , Marc Zyngier , Lorenzo Pieralisi , Inochi Amaoto , Saurabh Sengar , Shradha Gupta , Jonathan Cameron , Nicolin Chen , Jason Gunthorpe , Chen Wang Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH 2/4] PCI/MSI: Add startup/shutdown support for per device MSI[X] domains Date: Thu, 7 Aug 2025 19:23:23 +0800 Message-ID: <20250807112326.748740-3-inochiama@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250807112326.748740-1-inochiama@gmail.com> References: <20250807112326.748740-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As The RISC-V PLIC can not apply affinity setting without calling irq_enable(), it will make the interrupt unavaible when using as an underlying irq chip for MSI controller. Introduce the irq_startup/irq_shutdown for PCI domain template with new MSI domain flag. This allow the PLIC can be properly configurated when calling irq_startup(). Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- drivers/pci/msi/irqdomain.c | 52 +++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/pci/msi/irqdomain.c b/drivers/pci/msi/irqdomain.c index 0938ef7ebabf..f0d18cadbe20 100644 --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -148,6 +148,23 @@ static void pci_device_domain_set_desc(msi_alloc_info_= t *arg, struct msi_desc *d arg->hwirq =3D desc->msi_index; } =20 +static __always_inline void cond_shutdown_parent(struct irq_data *data) +{ + struct msi_domain_info *info =3D data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + irq_chip_shutdown_parent(data); +} + +static __always_inline unsigned int cond_startup_parent(struct irq_data *d= ata) +{ + struct msi_domain_info *info =3D data->domain->host_data; + + if (unlikely(info->flags & MSI_FLAG_PCI_MSI_STARTUP_PARENT)) + return irq_chip_startup_parent(data); + return 0; +} + static __always_inline void cond_mask_parent(struct irq_data *data) { struct msi_domain_info *info =3D data->domain->host_data; @@ -164,6 +181,23 @@ static __always_inline void cond_unmask_parent(struct = irq_data *data) irq_chip_unmask_parent(data); } =20 +static void pci_irq_shutdown_msi(struct irq_data *data) +{ + struct msi_desc *desc =3D irq_data_get_msi_desc(data); + + pci_msi_mask(desc, BIT(data->irq - desc->irq)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msi(struct irq_data *data) +{ + struct msi_desc *desc =3D irq_data_get_msi_desc(data); + unsigned int ret =3D cond_startup_parent(data); + + pci_msi_unmask(desc, BIT(data->irq - desc->irq)); + return ret; +} + static void pci_irq_mask_msi(struct irq_data *data) { struct msi_desc *desc =3D irq_data_get_msi_desc(data); @@ -194,6 +228,8 @@ static void pci_irq_unmask_msi(struct irq_data *data) static const struct msi_domain_template pci_msi_template =3D { .chip =3D { .name =3D "PCI-MSI", + .irq_startup =3D pci_irq_startup_msi, + .irq_shutdown =3D pci_irq_shutdown_msi, .irq_mask =3D pci_irq_mask_msi, .irq_unmask =3D pci_irq_unmask_msi, .irq_write_msi_msg =3D pci_msi_domain_write_msg, @@ -210,6 +246,20 @@ static const struct msi_domain_template pci_msi_templa= te =3D { }, }; =20 +static void pci_irq_shutdown_msix(struct irq_data *data) +{ + pci_msix_mask(irq_data_get_msi_desc(data)); + cond_shutdown_parent(data); +} + +static unsigned int pci_irq_startup_msix(struct irq_data *data) +{ + unsigned int ret =3D cond_startup_parent(data); + + pci_msix_unmask(irq_data_get_msi_desc(data)); + return ret; +} + static void pci_irq_mask_msix(struct irq_data *data) { pci_msix_mask(irq_data_get_msi_desc(data)); @@ -234,6 +284,8 @@ EXPORT_SYMBOL_GPL(pci_msix_prepare_desc); static const struct msi_domain_template pci_msix_template =3D { .chip =3D { .name =3D "PCI-MSIX", + .irq_startup =3D pci_irq_startup_msix, + .irq_shutdown =3D pci_irq_shutdown_msix, .irq_mask =3D pci_irq_mask_msix, .irq_unmask =3D pci_irq_unmask_msix, .irq_write_msi_msg =3D pci_msi_domain_write_msg, diff --git a/include/linux/msi.h b/include/linux/msi.h index e5e86a8529fb..3111ba95fbde 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -568,6 +568,8 @@ enum { MSI_FLAG_PARENT_PM_DEV =3D (1 << 8), /* Support for parent mask/unmask */ MSI_FLAG_PCI_MSI_MASK_PARENT =3D (1 << 9), + /* Support for parent startup/shutdown */ + MSI_FLAG_PCI_MSI_STARTUP_PARENT =3D (1 << 10), =20 /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK =3D GENMASK(15, 0), --=20 2.50.1 From nobody Sun Oct 5 07:20:28 2025 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34ADA279DAA; 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charset="utf-8" When using NVME on SG2044, the NVME always complains "I/O tag XXX (XXX) QID XX timeout, completion polled", which is caused by the broken handler of the sg2042-msi driver. As PLIC driver can only setting affinity when enabling, the sg2042-msi does not properly handled affinity setting previously and enable irq in an unexpected executing path. Since the PCI template domain supports irq_startup/irq_shutdown, set irq_chip_[startup/shutdown]_parent for irq_startup/irq_shutdown. So the irq can be started properly. Fixes: e96b93a97c90 ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interru= pt controller") Reported-by: Han Gao Suggested-by: Thomas Gleixner Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index bcfddc51bc6a..2b7ee17232ab 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -85,6 +85,8 @@ static void sg2042_msi_irq_compose_msi_msg(struct irq_dat= a *d, struct msi_msg *m =20 static const struct irq_chip sg2042_msi_middle_irq_chip =3D { .name =3D "SG2042 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2042_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -114,6 +116,8 @@ static void sg2044_msi_irq_compose_msi_msg(struct irq_d= ata *d, struct msi_msg *m =20 static struct irq_chip sg2044_msi_middle_irq_chip =3D { .name =3D "SG2044 MSI", + .irq_startup =3D irq_chip_startup_parent, + .irq_shutdown =3D irq_chip_shutdown_parent, .irq_ack =3D sg2044_msi_irq_ack, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, @@ -186,7 +190,9 @@ static const struct irq_domain_ops sg204x_msi_middle_do= main_ops =3D { }; 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charset="utf-8" The MSI controller on SG2044 has the ability to allocate multiple PCI MSI interrupt if the controller supports it. Add the missing flag so the controller can make full use of it. Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 2b7ee17232ab..6efb34a91937 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -212,6 +212,7 @@ static const struct msi_parent_ops sg2042_msi_parent_op= s =3D { MSI_FLAG_PCI_MSI_STARTUP_PARENT) =20 #define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX) =20 static const struct msi_parent_ops sg2044_msi_parent_ops =3D { --=20 2.50.1