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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2025 20:47:38.4099 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bea81dcd-7507-4b01-3a06-08ddd52a7af9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4471 Content-Type: text/plain; charset="utf-8" The boot_rdmsr and boot_wrmsr helpers used to reduce the need for inline assembly in the boot kernel can also be useful in code shared by boot and run-time kernel code. Move these helpers to asm/shared/msr.h and rename to raw_rdmsr and raw_wrmsr to indicate that these may also be used outside of the boot kernel. Signed-off-by: John Allen Reviewed-by: Tom Lendacky --- arch/x86/boot/compressed/sev.c | 7 ++++--- arch/x86/boot/compressed/sev.h | 6 +++--- arch/x86/boot/cpucheck.c | 16 ++++++++-------- arch/x86/boot/msr.h | 26 -------------------------- arch/x86/include/asm/shared/msr.h | 15 +++++++++++++++ 5 files changed, 30 insertions(+), 40 deletions(-) delete mode 100644 arch/x86/boot/msr.h diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index fd1b67dfea22..250b7156bd0f 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -14,6 +14,7 @@ =20 #include #include +#include #include #include #include @@ -436,7 +437,7 @@ void sev_enable(struct boot_params *bp) } =20 /* Set the SME mask if this is an SEV guest. */ - boot_rdmsr(MSR_AMD64_SEV, &m); + raw_rdmsr(MSR_AMD64_SEV, &m); sev_status =3D m.q; if (!(sev_status & MSR_AMD64_SEV_ENABLED)) return; @@ -499,7 +500,7 @@ u64 sev_get_status(void) if (sev_check_cpu_support() < 0) return 0; =20 - boot_rdmsr(MSR_AMD64_SEV, &m); + raw_rdmsr(MSR_AMD64_SEV, &m); return m.q; } =20 @@ -549,7 +550,7 @@ bool early_is_sevsnp_guest(void) struct msr m; =20 /* Obtain the address of the calling area to use */ - boot_rdmsr(MSR_SVSM_CAA, &m); + raw_rdmsr(MSR_SVSM_CAA, &m); boot_svsm_caa =3D (void *)m.q; boot_svsm_caa_pa =3D m.q; =20 diff --git a/arch/x86/boot/compressed/sev.h b/arch/x86/boot/compressed/sev.h index 92f79c21939c..81766d002c0a 100644 --- a/arch/x86/boot/compressed/sev.h +++ b/arch/x86/boot/compressed/sev.h @@ -10,7 +10,7 @@ =20 #ifdef CONFIG_AMD_MEM_ENCRYPT =20 -#include "../msr.h" +#include "asm/shared/msr.h" =20 void snp_accept_memory(phys_addr_t start, phys_addr_t end); u64 sev_get_status(void); @@ -20,7 +20,7 @@ static inline u64 sev_es_rd_ghcb_msr(void) { struct msr m; =20 - boot_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m); + raw_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m); =20 return m.q; } @@ -30,7 +30,7 @@ static inline void sev_es_wr_ghcb_msr(u64 val) struct msr m; =20 m.q =3D val; - boot_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m); + raw_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m); } =20 #else diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c index f82de8de5dc6..2e1bb936cba2 100644 --- a/arch/x86/boot/cpucheck.c +++ b/arch/x86/boot/cpucheck.c @@ -26,9 +26,9 @@ #include #include #include +#include =20 #include "string.h" -#include "msr.h" =20 static u32 err_flags[NCAPINTS]; =20 @@ -134,9 +134,9 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u= 32 **err_flags_ptr) =20 struct msr m; =20 - boot_rdmsr(MSR_K7_HWCR, &m); + raw_rdmsr(MSR_K7_HWCR, &m); m.l &=3D ~(1 << 15); - boot_wrmsr(MSR_K7_HWCR, &m); + raw_wrmsr(MSR_K7_HWCR, &m); =20 get_cpuflags(); /* Make sure it really did something */ err =3D check_cpuflags(); @@ -148,9 +148,9 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u= 32 **err_flags_ptr) =20 struct msr m; =20 - boot_rdmsr(MSR_VIA_FCR, &m); + raw_rdmsr(MSR_VIA_FCR, &m); m.l |=3D (1 << 1) | (1 << 7); - boot_wrmsr(MSR_VIA_FCR, &m); + raw_wrmsr(MSR_VIA_FCR, &m); =20 set_bit(X86_FEATURE_CX8, cpu.flags); err =3D check_cpuflags(); @@ -160,14 +160,14 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr,= u32 **err_flags_ptr) struct msr m, m_tmp; u32 level =3D 1; =20 - boot_rdmsr(0x80860004, &m); + raw_rdmsr(0x80860004, &m); m_tmp =3D m; m_tmp.l =3D ~0; - boot_wrmsr(0x80860004, &m_tmp); + raw_wrmsr(0x80860004, &m_tmp); asm("cpuid" : "+a" (level), "=3Dd" (cpu.flags[0]) : : "ecx", "ebx"); - boot_wrmsr(0x80860004, &m); + raw_wrmsr(0x80860004, &m); =20 err =3D check_cpuflags(); } else if (err =3D=3D 0x01 && diff --git a/arch/x86/boot/msr.h b/arch/x86/boot/msr.h deleted file mode 100644 index aed66f7ae199..000000000000 --- a/arch/x86/boot/msr.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Helpers/definitions related to MSR access. - */ - -#ifndef BOOT_MSR_H -#define BOOT_MSR_H - -#include - -/* - * The kernel proper already defines rdmsr()/wrmsr(), but they are not for= the - * boot kernel since they rely on tracepoint/exception handling infrastruc= ture - * that's not available here. - */ -static inline void boot_rdmsr(unsigned int reg, struct msr *m) -{ - asm volatile("rdmsr" : "=3Da" (m->l), "=3Dd" (m->h) : "c" (reg)); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2025 20:47:43.8366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc923ed5-2b7d-4f86-49a6-08ddd52a7e35 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 Content-Type: text/plain; charset="utf-8" When a guest issues a cpuid instruction for Fn0000000D_x0B (CetUserOffset), the hypervisor may intercept and access the guest XSS value. For SEV-ES, this is encrypted and needs to be included in the GHCB to be visible to the hypervisor. Signed-off-by: John Allen Reviewed-by: Tom Lendacky --- arch/x86/coco/sev/vc-shared.c | 11 +++++++++++ arch/x86/include/asm/svm.h | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/x86/coco/sev/vc-shared.c b/arch/x86/coco/sev/vc-shared.c index 2c0ab0fdc060..079fffdb12c0 100644 --- a/arch/x86/coco/sev/vc-shared.c +++ b/arch/x86/coco/sev/vc-shared.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 +#ifndef __BOOT_COMPRESSED +#define has_cpuflag(f) boot_cpu_has(f) +#endif + static enum es_result vc_check_opcode_bytes(struct es_em_ctxt *ctxt, unsigned long exit_code) { @@ -452,6 +456,13 @@ static enum es_result vc_handle_cpuid(struct ghcb *ghc= b, /* xgetbv will cause #GP - use reset value for xcr0 */ ghcb_set_xcr0(ghcb, 1); =20 + if (has_cpuflag(X86_FEATURE_SHSTK) && regs->ax =3D=3D 0xd && regs->cx <= =3D 1) { + struct msr m; + + raw_rdmsr(MSR_IA32_XSS, &m); + ghcb_set_xss(ghcb, m.q); + } + ret =3D sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0); if (ret !=3D ES_OK) return ret; diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index ffc27f676243..870ebfef86d6 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -700,5 +700,6 @@ DEFINE_GHCB_ACCESSORS(sw_exit_info_1) DEFINE_GHCB_ACCESSORS(sw_exit_info_2) DEFINE_GHCB_ACCESSORS(sw_scratch) DEFINE_GHCB_ACCESSORS(xcr0) +DEFINE_GHCB_ACCESSORS(xss) =20 #endif --=20 2.34.1