From nobody Sun Oct 5 09:07:17 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DAFB2E0B74 for ; Wed, 6 Aug 2025 19:58:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510326; cv=none; b=ChDmiFfkngI9Z3w00d6jnJLuiquwXuuP702tWUdTL1B8E2Wqq1n4wyaspvs7ikQe5nsOMN0l1eQKCqVLd+7OgeBkHpSCSDATBxzVHTH6kyRvI1cV+lz/Zw1BjKKnkHvagh7iqedXI145y9YSlsGtNXyxMWttFfFyMndEIOkrIW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510326; c=relaxed/simple; bh=xxEMYMafoH1hCuYfyuUxc0eXfBZ4HMKS++5sGsaBrpM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=rJgpU5t+5p8Emrlvf20LL0ci7OOeMypJnC1zDD9E+AAw6x79pwSjVHKp9dQFMg5mXptpGDsRi36h5GKG9qWc6axvbPxSXIt7fs3k9mBBn4Jg30EhL6DZ87ZOoJSNmVFCVGGTE6e3y/dWZcUTvyvlNtkYE5rWpaoDfXLj7wtcd/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=DdMX0++t; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="DdMX0++t" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-313d6d671ffso303261a91.2 for ; Wed, 06 Aug 2025 12:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1754510323; x=1755115123; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=AqSoz/ys0/nDwriVLA2HvcSasFXIo2nt11bZwmhw7W4=; b=DdMX0++t8TEps43r4L+BtI7kaHxLQ23a6EcGQADh64fVkngAr1srAI1De2hl8ngyEe 3JFAGghDRRDhlOAcvP9QpeZp3jcHVJbnVRuqa+ZNKHu5SWTgBI6TeEbI9Mx4vJqKE+qj lNKy41AZYlLdc7rC+TdxoxcLxexH+rTAvSdcLSshVJd+brdol6zZpIB9FkD3douITXXU dfBmyHBMkBvqtcLwXMPwU8dOixdNW81FvNoRfNABw4tecv3qPuj3ko3EoybKTrIdQdqs QzD2e5nYosvcuOZCWJ/SUPk8M9KqkXlTqkiaNBB3Z4CS+Y0jS/0Z3PhIWzugklE7aT/u Ar1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754510323; x=1755115123; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=AqSoz/ys0/nDwriVLA2HvcSasFXIo2nt11bZwmhw7W4=; b=smhv97MDyIdaDIYkqvkpo4DsQzCDsA+ENwpQYkiE/daSQFrDB75bzZoD/nL3yz5e+v IjJ89l7rNsHTO4mFv1D1BJZpfWuz/015I+wjfw54lBT3NchTnrhDniFDHuKgJNapkePV GwtXa+YaembthrC6voLl9mOt//BvGw5MIeo7iz/F3skltIXqLX54nadDnBkaVxb3W9N8 oqpK3/CJnSY/4I+M1XrMyq30dDBJerlueasGkqazdYHFhgj8kqe1AUyxwI1H3B699e1P bZ0+i6dVC+i7dgiJkZOEgqfYJ1Cu9N2BwedqCAHRfBNdVmu4bnANIeKdzNnznuF3IzWQ 1hwA== X-Forwarded-Encrypted: i=1; AJvYcCViTnrjPsOi3K6EpqlHi+sP8slLZEPsY/Vaq5zL2dhN+Abq/K7eXuJmv5ob6GubPhVVAJ02LsMutMtWBrw=@vger.kernel.org X-Gm-Message-State: AOJu0Yz8A9fb0idDY92Acm4nVeDEHy6/D+S8GU72KhLmwVJtpJKrRf6Z ngyK1iWrNEGeAegDmKzBiAXEkZ/JfOpEWbchx6rzKnJCjk07BORes5EFlqL1viS+cUh3tTYUQ9d IHLI0Cw== X-Google-Smtp-Source: AGHT+IFhegW1gGR7UHrSJevPOd3ITDk2k4F1jYjU8AgzTqj6JmCrtpCZa2eEdv34H9OVmz6MG3yGyWC8HfY= X-Received: from pjbsx14.prod.google.com ([2002:a17:90b:2cce:b0:311:c197:70a4]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1c09:b0:31e:3bbc:e9e6 with SMTP id 98e67ed59e1d1-3217638fd88mr438488a91.19.1754510322909; Wed, 06 Aug 2025 12:58:42 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 6 Aug 2025 12:57:03 -0700 In-Reply-To: <20250806195706.1650976-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> X-Mailer: git-send-email 2.50.1.565.gc32cd1483b-goog Message-ID: <20250806195706.1650976-42-seanjc@google.com> Subject: [PATCH v5 41/44] KVM: nVMX: Disable PMU MSR interception as appropriate while running L2 From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mingwei Zhang Merge KVM's PMU MSR interception bitmaps with those of L1, i.e. merge the bitmaps of vmcs01 and vmcs12, e.g. so that KVM doesn't interpose on MSR accesses unnecessarily if L1 exposes a mediated PMU (or equivalent) to L2. Signed-off-by: Mingwei Zhang Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi [sean: rewrite changelog and comment, omit MSRs that are always intercepted] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 47f1f0c7d3a7..b986a6fb684c 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -627,6 +627,34 @@ static inline void nested_vmx_set_intercept_for_msr(st= ruct vcpu_vmx *vmx, #define nested_vmx_merge_msr_bitmaps_rw(msr) \ nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_RW) =20 +static void nested_vmx_merge_pmu_msr_bitmaps(struct kvm_vcpu *vcpu, + unsigned long *msr_bitmap_l1, + unsigned long *msr_bitmap_l0) +{ + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + struct vcpu_vmx *vmx =3D to_vmx(vcpu); + int i; + + /* + * Skip the merges if the vCPU doesn't have a mediated PMU MSR, i.e. if + * none of the MSRs can possibly be passed through to L1. + */ + if (!kvm_vcpu_has_mediated_pmu(vcpu)) + return; + + for (i =3D 0; i < pmu->nr_arch_gp_counters; i++) { + nested_vmx_merge_msr_bitmaps_rw(MSR_IA32_PERFCTR0 + i); + nested_vmx_merge_msr_bitmaps_rw(MSR_IA32_PMC0 + i); + } + + for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) + nested_vmx_merge_msr_bitmaps_rw(MSR_CORE_PERF_FIXED_CTR0 + i); + + nested_vmx_merge_msr_bitmaps_rw(MSR_CORE_PERF_GLOBAL_CTRL); + nested_vmx_merge_msr_bitmaps_read(MSR_CORE_PERF_GLOBAL_STATUS); + nested_vmx_merge_msr_bitmaps_write(MSR_CORE_PERF_GLOBAL_OVF_CTRL); +} + /* * Merge L0's and L1's MSR bitmap, return false to indicate that * we do not use the hardware. @@ -724,6 +752,8 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct= kvm_vcpu *vcpu, nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_IA32_MPERF, MSR_TYPE_R); =20 + nested_vmx_merge_pmu_msr_bitmaps(vcpu, msr_bitmap_l1, msr_bitmap_l0); + kvm_vcpu_unmap(vcpu, &map); =20 vmx->nested.force_msr_bitmap_recalc =3D false; --=20 2.50.1.565.gc32cd1483b-goog