From nobody Sun Oct 5 09:07:18 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 055422BEC37 for ; Wed, 6 Aug 2025 19:58:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510324; cv=none; b=O2HlnSdOtu9rtaxF+KZJ/3Y2DDjLdPRvH27h6w4klZSi8U/CMHWpSldtQKICJRJLTmqS53CjSRTj1XoXdKigsUzh3Fs86ote5fz+w5MYN6c89jL+rxurHFK9WoIrD6Ijd2/j8knLvs/EgBW++Xjwlcj5PPiCXbUL8uMNphswIow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510324; c=relaxed/simple; bh=pnnkC1bAXhozYLn1+A5GeTVXCux318fw49cZ8cqaQ5s=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=gkmlmEBSXMr1b7f6ImX1gavrM84Rp2rixZfHLlR6RapkSsVKkPMJ5MxigfOqJyCrKlTyudGfQdDWgS33w4f0nyn1q0BJXn6NE2INVoJgGB9C+Fd6PHa0FJK65Ad3/nrvVVvLZZCvwj9Uk4twEfgbP5HSPVsVD+cKAzXAagIYUMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=IYnVlROR; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="IYnVlROR" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-31ed4a4a05bso1549524a91.1 for ; Wed, 06 Aug 2025 12:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1754510321; x=1755115121; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=RsFIN1Au3Dl4zaCmP13PW3DAgvYNBzVpKCYeyT5lYGI=; b=IYnVlRORAOh1paTIK2Lm6a8cAUBbjU6mYFNK46LfNaO1qKv1SZBsHSBBwZr3wrPEI1 5pktWiRCNbCJrs8AOBxCOjMhGE3//vWjdJA9Ypd6FdVC7yJR+zALuPIIUYEy0qvUpTqC Qm2wPWFU/aKVi2xwFE4P/ntTogfYPhM9kIMlv2Hp3TOQGui9gLeaHBQUhi4VxF7aQjd4 HTTnLb2dHPP9NNwaoCc4amb0JNEskMzjI0UnJQQNzjZAaZfuPgC4+DQyIAGjvQfiCADQ qqs0KUGp7RymYMbO8ErKcYwAHz8aP89ZPnbMp8rapq6g4gqrvnrqtg2Br/8KjfAwkgcp x2XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754510321; x=1755115121; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=RsFIN1Au3Dl4zaCmP13PW3DAgvYNBzVpKCYeyT5lYGI=; b=eIOexld0gi8/+XCYaHIgvLemNqx/mO6tox6Mvt1FmJnmoLhTwNUCE0PHD1SyD4TxAU wkWXIIM0B++T3ldaZHfaFyg845AhqZWp1dSGibmDAfE6RxMzacOpukXX9b8wkpzURVc/ NSEjNFPETwbHXaE8NTl9AKesMdeDnKmynqJkqxbrjeG86Jop9+b2wHJFkSpkA36Nxzj1 ZixjSSoo0ID1xut+qoYLsqPGaC0mmzz9IW00Kdx8vDM0MfpgKy1ORldI1l/Q6aMjxhFP ZswZJldiI4MEELTFnTQj5PMYWJKyC+br4NLXYhTV7RlOMo7J2xfAkxscqxkCQnC/bvr0 Lyqw== X-Forwarded-Encrypted: i=1; AJvYcCXfNrtPf9wtk+IANpUXsV44wf+eyCMlSa6t6fSifVClf2ZYWODAM63fsSvHNz+80Ao+jRrBLb+AqgbRAJY=@vger.kernel.org X-Gm-Message-State: AOJu0YxcP/LIIffH0LO/ocaF8D+rJs3orOs6jEJztiPemCMDIDj4GGrb tj0UV6hi8ekTG2AszB+tormjpzEFt6crqRr8sM/tUfM1cmQN13qEYw61ihTiXJSLiFDmaJNcZIG 4DGTS2w== X-Google-Smtp-Source: AGHT+IFbNifUFnJxYDSjClZPGiWnx/CS0ykT/Hb3U03iCPY3aeaisiXn0lmHgRNeXCjIQ2AkJAWL4xb8X68= X-Received: from pjqh12.prod.google.com ([2002:a17:90a:a88c:b0:311:d79d:e432]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4c07:b0:313:aefa:b08 with SMTP id 98e67ed59e1d1-32175622f9emr956977a91.16.1754510321187; Wed, 06 Aug 2025 12:58:41 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 6 Aug 2025 12:57:02 -0700 In-Reply-To: <20250806195706.1650976-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> X-Mailer: git-send-email 2.50.1.565.gc32cd1483b-goog Message-ID: <20250806195706.1650976-41-seanjc@google.com> Subject: [PATCH v5 40/44] KVM: nVMX: Add macros to simplify nested MSR interception setting From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Add macros nested_vmx_merge_msr_bitmaps_xxx() to simplify nested MSR interception setting. No function change intended. Suggested-by: Sean Christopherson Signed-off-by: Dapeng Mi Signed-off-by: Mingwei Zhang Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index db2fd4eedc90..47f1f0c7d3a7 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -614,6 +614,19 @@ static inline void nested_vmx_set_intercept_for_msr(st= ruct vcpu_vmx *vmx, msr_bitmap_l0, msr); } =20 +#define nested_vmx_merge_msr_bitmaps(msr, type) \ + nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, \ + msr_bitmap_l0, msr, type) + +#define nested_vmx_merge_msr_bitmaps_read(msr) \ + nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_R) + +#define nested_vmx_merge_msr_bitmaps_write(msr) \ + nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_W) + +#define nested_vmx_merge_msr_bitmaps_rw(msr) \ + nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_RW) + /* * Merge L0's and L1's MSR bitmap, return false to indicate that * we do not use the hardware. @@ -697,23 +710,13 @@ static inline bool nested_vmx_prepare_msr_bitmap(stru= ct kvm_vcpu *vcpu, * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through. */ #ifdef CONFIG_X86_64 - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_FS_BASE, MSR_TYPE_RW); - - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_GS_BASE, MSR_TYPE_RW); - - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_KERNEL_GS_BASE, MSR_TYPE_RW); + nested_vmx_merge_msr_bitmaps_rw(MSR_FS_BASE); + nested_vmx_merge_msr_bitmaps_rw(MSR_GS_BASE); + nested_vmx_merge_msr_bitmaps_rw(MSR_KERNEL_GS_BASE); #endif - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); - - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_IA32_PRED_CMD, MSR_TYPE_W); - - nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, - MSR_IA32_FLUSH_CMD, MSR_TYPE_W); + nested_vmx_merge_msr_bitmaps_rw(MSR_IA32_SPEC_CTRL); + nested_vmx_merge_msr_bitmaps_write(MSR_IA32_PRED_CMD); + nested_vmx_merge_msr_bitmaps_write(MSR_IA32_FLUSH_CMD); =20 nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_IA32_APERF, MSR_TYPE_R); --=20 2.50.1.565.gc32cd1483b-goog