From nobody Sun Oct 5 09:13:21 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14D0E2DE719 for ; Wed, 6 Aug 2025 19:58:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510317; cv=none; b=MLAYonbFAAWwC+QlDGeonsvToMmds30oEkPcuv0r2aGBIfuXsutbBDC+6XhtcRV8XJmfDNr12cTWxvmR407k1Eg9bL7OJAxy7TRdTriXhGtbJz+2jWNttHU+XCj6MFVV2Rgif0PiS/ebfR/RgGRtMjydk4wHtG/yg/LDNrhlv/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510317; c=relaxed/simple; bh=QVIn0+kukbkiW0o85fHutqEBFnL/lbFRNdNnmVngsXM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=nfKOcEyMNOAxpWmdaz41ntW6onv5KoFRaDnXR1mFJyY+u26wIPlTHNBUkhuq8NkGBlqRWQlhtdzTlRAoYgiGk3OmWXPJYHAhtSGVkltuSRk4bx6iQD5Pb5WWb4ywmz3EwWHjWLDZnrgvnhQaq25ctqPI45SRmJmJSIfF67Kp70o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=RiTWC4TC; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="RiTWC4TC" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-2400a932e59so2356685ad.1 for ; Wed, 06 Aug 2025 12:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1754510314; x=1755115114; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Pi5hsDnuks7nSFD8RayInQ9oz1eBhk4hTX7Cx/64BFI=; b=RiTWC4TCtRE/O8Sj808HlsXbva7/dbqhOWn5kIqyoN6RBax1pExeHUe5uPG6yHZmxX eKTC7+9tGMIqoJJrl9zLgUDu53zHWWna8iIrOB1DYm4bLuc6n4v4efo6ggGDvOkE5fwP BmGmMD5drl77+rv5Oz2LloWEfxE3xz5ed8Q6NqOnh5yLmZEtbehAiAYdjAyTnIjIZPXY 2ojQYxSwjkKj4tjJ1d9nwUdjTqNIxXpttRRY1oGwW2wprtgyS41ZgPUHrCs+J9wLvJ1C X6jZVGyXcoAwi3+GbOTWFDtrxelsHsn/I/jwNt66fXiAz8C3rLM/RuDtWBslJnAZj4At DF2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754510314; x=1755115114; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Pi5hsDnuks7nSFD8RayInQ9oz1eBhk4hTX7Cx/64BFI=; b=SvpKyq00F87u5GR6rju22s2TUcOsrc15mSDdA7LTpbCWmxEDHPT7P/oneziymIfc4P DqPbJPNip64LDojaXtUsFMpO89A61Ba/jG9I6CwguVUlsI3boxra/5f0P6TYH9aU+065 yQASUsCERkYkFx+a2JaV8oHpjkMYP9pYQSiMxQiGdL0TAm32m9jxKC1muTG2rQEcSJ5P nC6WE2aRHUPOqG0vDVCGdLE0wfFsqangDP5kB1I6dQM5LexwUf+sJxWAe6jWrhr6CPzh 8xb8eXwwWV/mLf8LA9EAtZ2tQ4Asp4W31hvfanZRCwmiuaGpZ8JBHK6kGPJg7hgWn/jp 8ByA== X-Forwarded-Encrypted: i=1; AJvYcCUgas79CdekzMcbIBLcIzDI2i547xtihDa/maV/9PdFYem70uDWPW33pNQSdsIA8eYWzXJKK5Zt4x/b370=@vger.kernel.org X-Gm-Message-State: AOJu0YxGRzQauB/ny+kunkYHxf/JuG0pUGLDh59Ioc4d/uCSZsJ0LZ2R bzqWMYQJSwoC0FHWRQHWfL0/YDFOzdt2Jm3HZUUylCS3srPGpSpIxOFjxoJKaYHVnQHPaNuCRBm +h1ppAA== X-Google-Smtp-Source: AGHT+IEJD5GH7UI5TAAlffejmtsOUdJu9B+mpPPWAxLwTCJvZJKLbNbFAds3hHNJ28h7v90ap7LjckKJrbQ= X-Received: from plhl7.prod.google.com ([2002:a17:903:1207:b0:235:f4e3:ba29]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:d581:b0:234:d7b2:2ac3 with SMTP id d9443c01a7336-2429f2eea48mr59065095ad.20.1754510314065; Wed, 06 Aug 2025 12:58:34 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 6 Aug 2025 12:56:58 -0700 In-Reply-To: <20250806195706.1650976-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> X-Mailer: git-send-email 2.50.1.565.gc32cd1483b-goog Message-ID: <20250806195706.1650976-37-seanjc@google.com> Subject: [PATCH v5 36/44] KVM: x86/pmu: Always stuff GuestOnly=1,HostOnly=0 for mediated PMCs on AMD From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sandipan Das On AMD platforms, there is no way to restore PerfCntrGlobalCtl at VM-Entry or clear it at VM-Exit. Since the register states will be restored before entering and saved after exiting guest context, the counters can keep ticking and even overflow leading to chaos while still in host context. To avoid this, intecept event selectors, which is already done by mediated PMU. In addition, always set the GuestOnly bit and clear the HostOnly bit for PMU selectors on AMD. Doing so allows the counters run only in guest context even if their enable bits are still set after VM exit and before host/guest PMU context switch. Signed-off-by: Sandipan Das Signed-off-by: Mingwei Zhang [sean: massage shortlog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/pmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 9641ef5d0dd7..a5e70a4e7647 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -165,7 +165,8 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) data &=3D ~pmu->reserved_bits; if (data !=3D pmc->eventsel) { pmc->eventsel =3D data; - pmc->eventsel_hw =3D data; + pmc->eventsel_hw =3D (data & ~AMD64_EVENTSEL_HOSTONLY) | + AMD64_EVENTSEL_GUESTONLY; kvm_pmu_request_counter_reprogram(pmc); } return 0; --=20 2.50.1.565.gc32cd1483b-goog