From nobody Sun Oct 5 09:07:17 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12A892D5426 for ; Wed, 6 Aug 2025 19:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510287; cv=none; b=OUrdwkB3m+tyysQSsDFJMmQJV2AlDNRPwfXTcmKPY941ebPp1mdBjLsR8q3flPU99/4t/6rfGXYaWKyXidBoZfF43qLOZ3hzFA3SOHZ8dgKQRe0KdXMmx+24qjvd9SlJ/Kt+9iHdmM6YPYrHpqi3Kmv5SY3FUGEengyJkWzRxFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754510287; c=relaxed/simple; bh=SrY28soq4e2umnXSFWFek5BM85G7hV4RrtHjWFxzyM0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=dxVpvqNKOCmG2oMPlFn7SbBStsxZUHZhViuCjrjEhTBeKR9slVl112LKVP9oBFEHRgwadkhx/9g1nyMNxzFqekFdtHDgegKJ3Ui4Djzf0bafXH89QqWJswpUCSClk+ag6h5odDDZ0t3a8FIAL+nqtGziDlXcbrf9PCjlKwm97WY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=lsTE+izp; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="lsTE+izp" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-76bf3e05024so226811b3a.2 for ; Wed, 06 Aug 2025 12:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1754510284; x=1755115084; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=GWdUZrt+U2ZtCbYKTsMlrHRvg1+poTmQboTMZxCN7ww=; b=lsTE+izpqSy/cIW9NFPPrDqdyCJ7ANLnG342H3Se9/7tbKtiDqfQV8CdT72T8q1Dma f9unfBmSGccU/nw47APfm8o7eRDLKo71U70iD3/PLyfAgbs3xkXhCMtDU9fL8QrjulxJ slg5Gj4GZvHbZBURxZgWDKhDmYsy6PRzphwnOorj3vfXlueyg5ycqh0ylwDUg596FOqv TfZOB7E5WE/B3XeDjSo3KnqJN9ci1xlqzxG6nmGxz8nXnvPoFyLnNqhRzAVrnTYQftoX A28Hh09NkVtz21gMeLq+12F6eMFAs+Bmp7H+s2C2YwmM3QM3Z3vAyavudU9Up9m/2J+O QuMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754510284; x=1755115084; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GWdUZrt+U2ZtCbYKTsMlrHRvg1+poTmQboTMZxCN7ww=; b=NIgk2uRbvEb/cCcfuTvd5kjdx8B6UFVz7lXFbMHyczzytffXvgaE4CEVFGy06WBYEJ LjOH8nqXa9noqi5rdaIDtw3HYOjydLH+hmjujin2NW0Fmf76UR00xYQ+nUS6jdlENJas vq+h5b8qmNU+7NsR7Y5zIpLTfkH/WDmKVuI56zJq3f/D3pej6sxwqIsUJetBwuIfV1/t 3cZPl60X/tY7B71U8f5jyzYK+xBQaRGRLwP38+/ZIkyhxBGRDinQHXJQEL5Mqx9tJcay eftzBPH6/xe3vv7Fj2ldy96jlip87n6Q6MIhx2HIWSDWlPpXAHNB5k0KXmN+5oKL6ZrB AO7A== X-Forwarded-Encrypted: i=1; AJvYcCVrpC/HrQ7DanbbhT9P1kwS5ubovkAAIPfUKducsmv1VCuvb01s/MaEkN9xiEsXYrzeD1ZeTDZOMCFEqDo=@vger.kernel.org X-Gm-Message-State: AOJu0YxcWsJq7FiYy//epHfe/VYWJxoLBM2xqoGVvu/hYBu+yg2R+qb8 pD3vbVzC9ZXXWneHFqYfW7ZyMTaufnDd75k1hNVnSbBTkz5iCIcqFPJ/ojBEDur0/01pa/glkn9 UAJj92A== X-Google-Smtp-Source: AGHT+IGuU+RWQRwCAfzWML148fgqdvdKW6alxUtwh3XwkGhhvD7y/3BjKg8jOpNbCUSNYHrZUCLfYMHRL8Y= X-Received: from pghd12.prod.google.com ([2002:a63:fd0c:0:b0:b42:2d66:cdc]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6300:8045:b0:240:43e9:6cb7 with SMTP id adf61e73a8af0-24043e97001mr56266637.45.1754510284410; Wed, 06 Aug 2025 12:58:04 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 6 Aug 2025 12:56:41 -0700 In-Reply-To: <20250806195706.1650976-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> X-Mailer: git-send-email 2.50.1.565.gc32cd1483b-goog Message-ID: <20250806195706.1650976-20-seanjc@google.com> Subject: [PATCH v5 19/44] KVM: x86/pmu: Implement Intel mediated PMU requirements and constraints From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Implement Intel PMU requirements and constraints for mediated PMU support. Require host PMU version 4+ so that PERF_GLOBAL_STATUS_SET can be used to precisely load the guest's status value into hardware, and require full- width writes so that KVM can precisely load guest counter values. Disable PEBS and LBRs if mediated PMU support is enabled, as they won't be supported in the initial implementation. Signed-off-by: Dapeng Mi Co-developed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang [sean: split to separate patch, add full-width writes dependency] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/capabilities.h | 3 ++- arch/x86/kvm/vmx/pmu_intel.c | 17 +++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 3 ++- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index 5316c27f6099..854e54c352f8 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -389,7 +389,8 @@ static inline bool vmx_pt_mode_is_host_guest(void) =20 static inline bool vmx_pebs_supported(void) { - return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; + return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept && + !enable_mediated_pmu; } =20 static inline bool cpu_has_notify_vmexit(void) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 07baff96300f..8df8d7b4f212 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -776,6 +776,20 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) } } =20 +static bool intel_pmu_is_mediated_pmu_supported(struct x86_pmu_capability = *host_pmu) +{ + u64 host_perf_cap =3D 0; + + if (boot_cpu_has(X86_FEATURE_PDCM)) + rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); + + /* + * Require v4+ for MSR_CORE_PERF_GLOBAL_STATUS_SET, and full-width + * writes so that KVM can precisely load guest counter values. + */ + return host_pmu->version >=3D 4 && host_perf_cap & PMU_CAP_FW_WRITES; +} + struct kvm_pmu_ops intel_pmu_ops __initdata =3D { .rdpmc_ecx_to_pmc =3D intel_rdpmc_ecx_to_pmc, .msr_idx_to_pmc =3D intel_msr_idx_to_pmc, @@ -787,6 +801,9 @@ struct kvm_pmu_ops intel_pmu_ops __initdata =3D { .reset =3D intel_pmu_reset, .deliver_pmi =3D intel_pmu_deliver_pmi, .cleanup =3D intel_pmu_cleanup, + + .is_mediated_pmu_supported =3D intel_pmu_is_mediated_pmu_supported, + .EVENTSEL_EVENT =3D ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS =3D KVM_MAX_NR_INTEL_GP_COUNTERS, .MIN_NR_GP_COUNTERS =3D 1, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ed10013dac95..8c6343494e62 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7795,7 +7795,8 @@ static __init u64 vmx_get_perf_capabilities(void) if (boot_cpu_has(X86_FEATURE_PDCM)) rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); =20 - if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) { + if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && + !enable_mediated_pmu) { x86_perf_get_lbr(&vmx_lbr_caps); =20 /* --=20 2.50.1.565.gc32cd1483b-goog