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Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sandipan Das Not all x86 processors have fixed counters. It may also be the case that a processor has only fixed counters and no general-purpose counters. Set the bit widths corresponding to each counter type only if such counters are available. Fixes: b3d9468a8bd2 ("perf, x86: Expose perf capability to other modules") Signed-off-by: Sandipan Das Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Mingwei Zhang Signed-off-by: Sean Christopherson --- arch/x86/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 9b0525b252f1..b8583a6962f1 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3125,8 +3125,8 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capab= ility *cap) cap->version =3D x86_pmu.version; cap->num_counters_gp =3D x86_pmu_num_counters(NULL); cap->num_counters_fixed =3D x86_pmu_num_counters_fixed(NULL); - cap->bit_width_gp =3D x86_pmu.cntval_bits; - cap->bit_width_fixed =3D x86_pmu.cntval_bits; + cap->bit_width_gp =3D cap->num_counters_gp ? x86_pmu.cntval_bits : 0; + cap->bit_width_fixed =3D cap->num_counters_fixed ? x86_pmu.cntval_bits : = 0; cap->events_mask =3D (unsigned int)x86_pmu.events_maskl; cap->events_mask_len =3D x86_pmu.events_mask_len; cap->pebs_ept =3D x86_pmu.pebs_ept; --=20 2.50.1.565.gc32cd1483b-goog