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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 5/7] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N} Date: Wed, 6 Aug 2025 20:55:53 +0100 Message-ID: <20250806195555.1372317-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded PFC_OEN define and obsolete per-SoC OEN helpers. Also drop redundant checks for the OEN offset in the suspend/resume paths, as all supported SoCs now provide a valid offset through the `regs.oen` field. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Grouped oen_pwpr_lock flag with other bools - Dropped redundant checks for OEN offset in suspend/resume paths - Updated the commit message to reflect the changes - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 68 ++++++++----------------- 1 file changed, 22 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 491cf5582b6c..d5eea8ae4cdc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -255,6 +254,7 @@ enum rzg2l_iolh_index { * @iolh_groupb_oi: IOLH group B output impedance specific values * @tint_start_index: the start index for the TINT interrupts * @drive_strength_ua: drive strength in uA is supported (otherwise mA is = supported) + * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable @@ -267,6 +267,7 @@ struct rzg2l_hwcfg { u16 iolh_groupb_oi[4]; u16 tint_start_index; bool drive_strength_ua; + bool oen_pwpr_lock; u8 func_base; u8 oen_max_pin; u8 oen_max_port; @@ -1083,10 +1084,11 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + const struct rzg2l_register_offsets *regs =3D &pctrl->data->hwcfg->regs; u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; + u8 val, pwpr; int bit; - u8 val; =20 if (!pctrl->data->pin_to_oen_bit) return -EINVAL; @@ -1101,7 +1103,13 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe val &=3D ~BIT(bit); else val |=3D BIT(bit); + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr =3D readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); + } writeb(val, pctrl->base + oen_offset); + if (pctrl->data->hwcfg->oen_pwpr_lock) + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1192,7 +1200,7 @@ static int rzv2h_bias_param_to_hw(enum pin_config_par= am param) return -EINVAL; } =20 -static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _= pin) +static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", "XSPI0_RESET0N", "XSPI0_CS0N", @@ -1206,41 +1214,7 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl = *pctrl, unsigned int _pin) } =20 /* Should not happen. */ - return 0; -} - -static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - u8 bit; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - - return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); -} - -static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - unsigned long flags; - u8 val, bit; - u8 pwpr; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + PFC_OEN); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - - pwpr =3D readb(pctrl->base + regs->pwpr); - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); - writeb(val, pctrl->base + PFC_OEN); - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; + return -EINVAL; } =20 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, @@ -3140,8 +3114,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) } =20 cache->qspi =3D readb(pctrl->base + QSPI); - if (pctrl->data->hwcfg->regs.oen) - cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3166,8 +3139,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); - if (pctrl->data->hwcfg->regs.oen) - writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); + writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3267,8 +3239,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, + .oen =3D 0x3c40, }, .tint_start_index =3D 17, + .oen_pwpr_lock =3D true, }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { @@ -3365,8 +3339,9 @@ static struct rzg2l_pinctrl_data r9a09g056_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, + .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3389,8 +3364,9 @@ static struct rzg2l_pinctrl_data r9a09g057_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, + .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.50.1