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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:04 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 3/7] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable Date: Wed, 6 Aug 2025 20:55:51 +0100 Message-ID: <20250806195555.1372317-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Refactor the RZG2L pinctrl driver to support reuse of the common rzg2l_read_oen() and rzg2l_write_oen() helpers across SoCs with different output-enable (OEN) bit mappings. Introduce a new `pin_to_oen_bit` callback in `struct rzg2l_pinctrl_data` to allow SoCs to provide custom logic for mapping a pin to its OEN bit. Update the generic OEN read/write paths to use this callback when present. With this change, SoCs like RZ/G3S can reuse the common OEN handling code by simply supplying their own `pin_to_oen_bit` implementation. The previously duplicated `rzg3s_oen_read()` and `rzg3s_oen_write()` functions are now removed. This improves maintainability and prepares the driver for supporting future SoCs with minimal duplication. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added blank line after if condition in rzg2l_read_oen() and rzg2l_write_o= en() - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 54 +++++++------------------ 1 file changed, 15 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index c45ae685fad3..cac7f2814376 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -296,6 +296,7 @@ struct rzg2l_pinctrl_data { #endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); + int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); @@ -1070,7 +1071,10 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctr= l, unsigned int _pin) { int bit; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return 0; + + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) return 0; =20 @@ -1084,9 +1088,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe int bit; u8 val; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return -EINVAL; + + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return bit; + return -EINVAL; =20 spin_lock_irqsave(&pctrl->lock, flags); val =3D readb(pctrl->base + oen_offset); @@ -1120,40 +1127,6 @@ static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl= *pctrl, unsigned int _pin) return bit; } =20 -static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - int bit; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return 0; - - return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); -} - -static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; - unsigned long flags; - int bit; - u8 val; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return bit; - - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + oen_offset); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - writeb(val, pctrl->base + oen_offset); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - static int rzg2l_hw_to_bias_param(unsigned int bias) { switch (bias) { @@ -3312,6 +3285,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3329,6 +3303,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .hwcfg =3D &rzg2l_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3345,8 +3320,9 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .hwcfg =3D &rzg3s_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, - .oen_read =3D &rzg3s_oen_read, - .oen_write =3D &rzg3s_oen_write, + .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; --=20 2.50.1