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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:02 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 1/7] pinctrl: renesas: rzg2l: Fix invalid unsigned return in rzg3s_oen_read() Date: Wed, 6 Aug 2025 20:55:49 +0100 Message-ID: <20250806195555.1372317-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar rzg3s_oen_read() returns a u32 value, but previously propagated a negative error code from rzg3s_pin_to_oen_bit(), resulting in an unintended large positive value due to unsigned conversion. This caused incorrect output-enable reporting for certain pins. Without this patch, pins P1_0-P1_4 and P7_0-P7_4 are incorrectly reported as "output enabled" in the pinconf-pins debugfs file. With this fix, only P1_0-P1_1 and P7_0-P7_1 are shown as "output enabled", which matches the hardware manual. Fix this by returning 0 when the OEN bit lookup fails, treating the pin as output-disabled by default. Fixes: a9024a323af2 ("pinctrl: renesas: rzg2l: Clean up and refactor OEN re= ad/write functions") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 2a10ae0bf5bd..af4a40ca0a98 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1124,7 +1124,7 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl= , unsigned int _pin) =20 bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return bit; + return 0; =20 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } --=20 2.50.1 From nobody Sun Oct 5 07:26:04 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA49F2BD5A1; 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:03 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset Date: Wed, 6 Aug 2025 20:55:50 +0100 Message-ID: <20250806195555.1372317-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare for supporting SoCs with varying OEN register locations by parameterizing the OEN offset in the rzg2l driver. Introduce an `oen` field in the rzg2l_register_offsets structure and update rzg2l_read_oen(), rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use this offset instead of the hard-coded ETH_MODE value. As part of this change, rename the field `eth_mode` in the register cache to `oen` to better reflect its general purpose and decouple the naming from a specific register. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Renamed `eth_mode` to `oen` in the rzg2l_pinctrl_reg_cache struct - Added a if condition to check if the OEN register offset is defined before reading/writing it in suspend/resume functions - Updated commit message v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 29 +++++++++++++++---------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index af4a40ca0a98..c45ae685fad3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define ETH_MODE (0x3018) #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ @@ -221,11 +220,13 @@ static const struct pin_config_item renesas_rzv2h_con= f_items[] =3D { * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset + * @oen: OEN register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; + u16 oen; }; =20 /** @@ -322,7 +323,7 @@ struct rzg2l_pinctrl_pin_settings { * @ien: IEN registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache - * @eth_mode: ETH_MODE register cache + * @oen: Output Enable register cache * @qspi: QSPI registers cache */ struct rzg2l_pinctrl_reg_cache { @@ -335,7 +336,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *pupd[2]; u8 sd_ch[2]; u8 eth_poc[2]; - u8 eth_mode; + u8 oen; u8 qspi; }; =20 @@ -1073,11 +1074,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1087,12 +1089,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); if (oen) val &=3D ~BIT(bit); else val |=3D BIT(bit); - writeb(val, pctrl->base + ETH_MODE); + writeb(val, pctrl->base + oen_offset); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1126,11 +1128,12 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1140,12 +1143,12 @@ static int rzg3s_oen_write(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:04 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 3/7] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable Date: Wed, 6 Aug 2025 20:55:51 +0100 Message-ID: <20250806195555.1372317-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Refactor the RZG2L pinctrl driver to support reuse of the common rzg2l_read_oen() and rzg2l_write_oen() helpers across SoCs with different output-enable (OEN) bit mappings. Introduce a new `pin_to_oen_bit` callback in `struct rzg2l_pinctrl_data` to allow SoCs to provide custom logic for mapping a pin to its OEN bit. Update the generic OEN read/write paths to use this callback when present. With this change, SoCs like RZ/G3S can reuse the common OEN handling code by simply supplying their own `pin_to_oen_bit` implementation. The previously duplicated `rzg3s_oen_read()` and `rzg3s_oen_write()` functions are now removed. This improves maintainability and prepares the driver for supporting future SoCs with minimal duplication. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added blank line after if condition in rzg2l_read_oen() and rzg2l_write_o= en() - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 54 +++++++------------------ 1 file changed, 15 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index c45ae685fad3..cac7f2814376 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -296,6 +296,7 @@ struct rzg2l_pinctrl_data { #endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); + int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); @@ -1070,7 +1071,10 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctr= l, unsigned int _pin) { int bit; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return 0; + + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) return 0; =20 @@ -1084,9 +1088,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe int bit; u8 val; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return -EINVAL; + + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return bit; + return -EINVAL; =20 spin_lock_irqsave(&pctrl->lock, flags); val =3D readb(pctrl->base + oen_offset); @@ -1120,40 +1127,6 @@ static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl= *pctrl, unsigned int _pin) return bit; } =20 -static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - int bit; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return 0; - - return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); -} - -static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; - unsigned long flags; - int bit; - u8 val; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return bit; - - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + oen_offset); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - writeb(val, pctrl->base + oen_offset); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - static int rzg2l_hw_to_bias_param(unsigned int bias) { switch (bias) { @@ -3312,6 +3285,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3329,6 +3303,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .hwcfg =3D &rzg2l_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3345,8 +3320,9 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .hwcfg =3D &rzg3s_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, - .oen_read =3D &rzg3s_oen_read, - .oen_write =3D &rzg3s_oen_write, + .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:05 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 4/7] pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E Date: Wed, 6 Aug 2025 20:55:52 +0100 Message-ID: <20250806195555.1372317-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/G3E pin controller does not advertise PIN_CFG_OEN capability, so there is no valid mapping for output-enable bits on this SoC. Remove the oen_read and oen_write callbacks from the RZ/G3E driver data to defer OEN support until PIN_CFG_OEN support is added. This is a preparatory change for future unification of OEN handling across the driver. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index cac7f2814376..491cf5582b6c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3344,8 +3344,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.50.1 From nobody Sun Oct 5 07:26:04 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB9C72BD5A8; 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 5/7] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N} Date: Wed, 6 Aug 2025 20:55:53 +0100 Message-ID: <20250806195555.1372317-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded PFC_OEN define and obsolete per-SoC OEN helpers. Also drop redundant checks for the OEN offset in the suspend/resume paths, as all supported SoCs now provide a valid offset through the `regs.oen` field. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Grouped oen_pwpr_lock flag with other bools - Dropped redundant checks for OEN offset in suspend/resume paths - Updated the commit message to reflect the changes - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 68 ++++++++----------------- 1 file changed, 22 insertions(+), 46 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 491cf5582b6c..d5eea8ae4cdc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -255,6 +254,7 @@ enum rzg2l_iolh_index { * @iolh_groupb_oi: IOLH group B output impedance specific values * @tint_start_index: the start index for the TINT interrupts * @drive_strength_ua: drive strength in uA is supported (otherwise mA is = supported) + * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable @@ -267,6 +267,7 @@ struct rzg2l_hwcfg { u16 iolh_groupb_oi[4]; u16 tint_start_index; bool drive_strength_ua; + bool oen_pwpr_lock; u8 func_base; u8 oen_max_pin; u8 oen_max_port; @@ -1083,10 +1084,11 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + const struct rzg2l_register_offsets *regs =3D &pctrl->data->hwcfg->regs; u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; + u8 val, pwpr; int bit; - u8 val; =20 if (!pctrl->data->pin_to_oen_bit) return -EINVAL; @@ -1101,7 +1103,13 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe val &=3D ~BIT(bit); else val |=3D BIT(bit); + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr =3D readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); + } writeb(val, pctrl->base + oen_offset); + if (pctrl->data->hwcfg->oen_pwpr_lock) + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1192,7 +1200,7 @@ static int rzv2h_bias_param_to_hw(enum pin_config_par= am param) return -EINVAL; } =20 -static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _= pin) +static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", "XSPI0_RESET0N", "XSPI0_CS0N", @@ -1206,41 +1214,7 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl = *pctrl, unsigned int _pin) } =20 /* Should not happen. */ - return 0; -} - -static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - u8 bit; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - - return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); -} - -static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - unsigned long flags; - u8 val, bit; - u8 pwpr; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + PFC_OEN); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - - pwpr =3D readb(pctrl->base + regs->pwpr); - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); - writeb(val, pctrl->base + PFC_OEN); - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; + return -EINVAL; } =20 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, @@ -3140,8 +3114,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) } =20 cache->qspi =3D readb(pctrl->base + QSPI); - if (pctrl->data->hwcfg->regs.oen) - cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3166,8 +3139,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); - if (pctrl->data->hwcfg->regs.oen) - writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); + writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3267,8 +3239,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, + .oen =3D 0x3c40, }, .tint_start_index =3D 17, + .oen_pwpr_lock =3D true, }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { @@ -3365,8 +3339,9 @@ static struct rzg2l_pinctrl_data r9a09g056_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, + .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:07 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 6/7] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC Date: Wed, 6 Aug 2025 20:55:54 +0100 Message-ID: <20250806195555.1372317-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for configuring the PFC_OEN register on the RZ/G3E SoC to enable output-enable control for specific pins. On this SoC, certain pins such as TXC_TXCLK need to support switching between input and output modes depending on the PHY interface mode (e.g., MII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the PFC_OEN register. This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1, PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these pin names to their respective OEN bit positions, and the corresponding callbacks are wired into the RZ/G3E SoC configuration using the generic rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO configuration for the PB, PE, and PL ports is updated to use the variable port pack macro, enabling per-pin configuration necessary for OEN handling. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added Reviewed-by tag from Geert. v1->v2: - Adapted the code to use the new unified OEN handling --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 61 +++++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index d5eea8ae4cdc..9fb9e6d2c6d5 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -397,6 +397,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), @@ -405,6 +413,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), @@ -424,6 +440,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), }; =20 static const u64 r9a09g057_variable_pin_cfg[] =3D { @@ -1200,23 +1224,39 @@ static int rzv2h_bias_param_to_hw(enum pin_config_p= aram param) return -EINVAL; } =20 -static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigne= d int _pin, + const char * const pin_names[], unsigned int count) { - static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", - "XSPI0_RESET0N", "XSPI0_CS0N", - "XSPI0_CKN", "XSPI0_CKP" }; const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[_pin]; unsigned int i; =20 - for (i =3D 0; i < ARRAY_SIZE(pin_names); i++) { + for (i =3D 0; i < count; i++) { if (!strcmp(pin_desc->name, pin_names[i])) return i; } =20 - /* Should not happen. */ return -EINVAL; } =20 +static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + static const char * const pin_names[] =3D { + "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", + "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" + }; + + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_= names)); +} + +static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + static const char * const pin_names[] =3D { + "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" + }; + + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_= names)); +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -2008,17 +2048,17 @@ static const u64 r9a09g047_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ - RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ - RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ - RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 0x0, 0x0, @@ -3318,6 +3358,9 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, + .pin_to_oen_bit =3D &rzg3e_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; 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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b79c3bf93dsm24137782f8f.27.2025.08.06.12.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 12:56:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 7/7] pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks Date: Wed, 6 Aug 2025 20:55:55 +0100 Message-ID: <20250806195555.1372317-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250806195555.1372317-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Remove oen_read and oen_write callbacks from rzg2l_pinctrl_data as all SoCs now use the same rzg2l_read_oen() and rzg2l_write_oen() functions directly. Change rzg2l_read_oen() return type to int for proper error reporting and update callers to handle errors consistently. This simplifies the code by removing redundant callbacks and ensures uniform OEN handling across all supported SoCs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3: - Added Reviewed-by tag from Geert. v1->v2: - New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 35 +++++++------------------ 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 9fb9e6d2c6d5..5eebe12c4595 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -298,8 +298,6 @@ struct rzg2l_pinctrl_data { void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); - u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); - int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); int (*bias_param_to_hw)(enum pin_config_param param); }; @@ -1092,16 +1090,16 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctr= l *pctrl, unsigned int _pin) return -EINVAL; } =20 -static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { int bit; =20 if (!pctrl->data->pin_to_oen_bit) - return 0; + return -EOPNOTSUPP; =20 bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return 0; + return -EINVAL; =20 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } @@ -1115,7 +1113,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctr= l, unsigned int _pin, u8 oe int bit; =20 if (!pctrl->data->pin_to_oen_bit) - return -EINVAL; + return -EOPNOTSUPP; =20 bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) @@ -1298,11 +1296,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl= _dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: if (!(cfg & PIN_CFG_OEN)) return -EINVAL; - if (!pctrl->data->oen_read) - return -EOPNOTSUPP; - arg =3D pctrl->data->oen_read(pctrl, _pin); - if (!arg) - return -EINVAL; + ret =3D rzg2l_read_oen(pctrl, _pin); + if (ret < 0) + return ret; + arg =3D ret; break; =20 case PIN_CONFIG_POWER_SOURCE: @@ -1461,9 +1458,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: if (!(cfg & PIN_CFG_OEN)) return -EINVAL; - if (!pctrl->data->oen_write) - return -EOPNOTSUPP; - ret =3D pctrl->data->oen_write(pctrl, _pin, !!arg); + ret =3D rzg2l_write_oen(pctrl, _pin, !!arg); if (ret) return ret; break; @@ -3300,8 +3295,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3318,8 +3311,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3335,8 +3326,6 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3359,8 +3348,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzg3e_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3383,8 +3370,6 @@ static struct rzg2l_pinctrl_data r9a09g056_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3408,8 +3393,6 @@ static struct rzg2l_pinctrl_data r9a09g057_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.50.1