From nobody Sun Oct 5 09:04:14 2025 Received: from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EAC928C027; Wed, 6 Aug 2025 15:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754492709; cv=none; b=czFK0CssLQzxCPG+FX+yTIr4fnvLck7mqD8HsHCP4ebzgprN1qdsLWCmG6vnQfyH2E/YyJyHPj3pvKLLoI2CI05OiymjD7w0kF+pmpAB4pyBjtg94ZqAnZiubCT09InZMe9AqhX5UFworas5Q6c9vb54jNtOUOiBovwmx0PLJUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754492709; c=relaxed/simple; bh=fuYMrpOrJ6nZYYv8eCAIvjIUrE+nnAyZf5ORW7jxh7E=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ib/i7wPuKipgwDS+ZVg27QMvmth4bJP4aAD3HeCsvFN/4Oocji5SDtdSAbHzuBXKTalg9ruGINeqshdfs6O92pRZ0SmpOQYcwV1RRpbjassl+todsnoC0HAj97ZHUmqqrPtmLaRhrl+za41Ug4bndoKaVfEvVHv25WcQPVvUwks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=CIzsY2/2; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=hDiHlE3B; arc=none smtp.client-ip=80.241.56.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="CIzsY2/2"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="hDiHlE3B" Received: from smtp202.mailbox.org (smtp202.mailbox.org [10.196.197.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-201.mailbox.org (Postfix) with ESMTPS id 4bxtrK482Rz9sJ3; Wed, 6 Aug 2025 17:05:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1754492705; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=0Xb1gcwOb+OUSeItxSM+cReVbxFeztwB6ynzPiFVKds=; b=CIzsY2/2CjVfo4AAXd6QHgF44FBCTgikJgExkKDsstk8PnzMJOq4vki55L6So+wtMCvmZN 9eouqSNY3YmR68VG/sUkY3B/BKY1fCWSPFKgJFSu6lnzXMA43F77JHku6DSkyP7vXTAz2l X4cYuMOfI7s2LPAq5FV9pZ+kYCloDWO/xEdDVkGnM+n9X7mjFdkZF6asacR0/fT6AzP8oy Ig4MB0wl8/o+Y5rFR1iI4oatvd43v7N9HdAX3ar5u90LkSOrZRPWIQs91qk6Aoc4Fjt8eH BpvjCtFstsEAv4cQ/sy8eXworv6Vknuf89p4B7xxH0ZMT4tvbxQGw3wvocCiwA== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1754492703; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=0Xb1gcwOb+OUSeItxSM+cReVbxFeztwB6ynzPiFVKds=; b=hDiHlE3Bz+3lc6yOmzScT+/c+L9bOngw8Wa6FY6z+fAtNJwqE8ODgiF8agWM7JgX58X99B sYNPlidsKTACr1ptiA+tgGnXQeZyhFwuEuKgrP1ZI+AL4l/DlgK1F9ehI9jPSt+/snaS1V CuDLZVjVjcVCxQH9NAysCZGu3Xr008YG4jyGyJjRsklWOPcjQ6BUVKBBb+QmevX9G5b53G SqrTXhTz5EUcvKT69kCZPL/+rtwlR+9xk8gcaALjfELWPXeKmE+ovwnvKGYrsaxsMaPPX1 nvleB9dYT6M5RmTcYwO8wuib42T59pJ86m0fSPbjXO6VtrfjBfp+zBVaJo7WFA== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2] ARM: dts: renesas: Add boot phase tags marking to Renesas RZ/A1 Date: Wed, 6 Aug 2025 17:04:27 +0200 Message-ID: <20250806150448.9669-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: a9ff50ae2e0858919c0 X-MBO-RS-META: gemjm8p8bjmrjzrawdaz3m1u61rf8pm4 Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yam= l) to describe various node usage during boot phases with DT. Add bootph-all f= or all nodes that are used in the bootloader on Renesas RZ/A1 SoC. All SoC require BSC bus, PFC pin control and OSTM0 timer access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains the PFC and OSTM IPs. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Drop blank newline arount bootph-all , move ostm bootph-all to board DTs --- arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 4 +++- arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 4 +++- arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 3 +++ arch/arm/boot/dts/renesas/r7s72100.dtsi | 3 +++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/= dts/renesas/r7s72100-genmai.dts index c81840dfb7da..3c3756509714 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -203,6 +203,7 @@ &mtu2 { }; =20 &ostm0 { + bootph-all; status =3D "okay"; }; =20 @@ -258,6 +259,7 @@ mmcif_pins: mmcif { }; =20 scif2_pins: serial2 { + bootph-all; /* P3_0 as TxD2; P3_2 as RxD2 */ pinmux =3D , ; }; @@ -286,7 +288,7 @@ &rtc { &scif2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&scif2_pins>; - + bootph-all; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boo= t/dts/renesas/r7s72100-gr-peach.dts index 9d29861f23f1..23ddec217685 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts @@ -59,6 +59,7 @@ led1 { =20 &pinctrl { scif2_pins: serial2 { + bootph-all; /* P6_2 as RxD2; P6_3 as TxD2 */ pinmux =3D , ; }; @@ -99,6 +100,7 @@ &mtu2 { }; =20 &ostm0 { + bootph-all; status =3D "okay"; }; =20 @@ -109,7 +111,7 @@ &ostm1 { &scif2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&scif2_pins>; - + bootph-all; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot= /dts/renesas/r7s72100-rskrza1.dts index 25c6d0c78828..91178fb9e721 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -199,6 +199,7 @@ keyboard_pins: keyboard { =20 /* Serial Console */ scif2_pins: serial2 { + bootph-all; pinmux =3D , /* TxD2 */ ; /* RxD2 */ }; @@ -264,6 +265,7 @@ &sdhi1 { }; =20 &ostm0 { + bootph-all; status =3D "okay"; }; =20 @@ -278,6 +280,7 @@ &rtc { &scif2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&scif2_pins>; + bootph-all; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/re= nesas/r7s72100.dtsi index 1a866dbaf5e9..a1e4e9ac8f62 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -41,6 +41,7 @@ bsc: bus { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0 0 0x18000000>; + bootph-all; }; =20 cpus { @@ -107,6 +108,7 @@ soc { #address-cells =3D <1>; #size-cells =3D <1>; ranges; + bootph-all; =20 L2: cache-controller@3ffff000 { compatible =3D "arm,pl310-cache"; @@ -557,6 +559,7 @@ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 =20 pinctrl: pinctrl@fcfe3000 { compatible =3D "renesas,r7s72100-ports"; + bootph-all; =20 reg =3D <0xfcfe3000 0x4230>; =20 --=20 2.47.2