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charset="utf-8" Both PHYs can use an alternate reference differential clock, add the clocks to the DT bindings Signed-off-by: Rick Wertenbroek --- .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml = b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index d7de8b527c5c..b747930b18f1 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -20,11 +20,11 @@ properties: =20 clocks: minItems: 1 - maxItems: 3 + maxItems: 5 =20 clock-names: minItems: 1 - maxItems: 3 + maxItems: 5 =20 data-lanes: description: which lanes (by position) should be mapped to which @@ -82,10 +82,15 @@ allOf: then: properties: clocks: - maxItems: 1 + minItems: 1 + maxItems: 5 clock-names: items: - const: pclk + - const: phy0_ref_alt_p + - const: phy0_ref_alt_m + - const: phy1_ref_alt_p + - const: phy1_ref_alt_m else: properties: clocks: --=20 2.25.1 From nobody Sun Oct 5 09:06:16 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9713428C2B6; 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Wed, 06 Aug 2025 06:38:32 -0700 (PDT) Received: from A13PC04R.einet.ad.eivd.ch ([185.144.39.75]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a21c10asm1113170666b.116.2025.08.06.06.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 06:38:32 -0700 (PDT) From: Rick Wertenbroek To: Cc: rick.wertenbroek@heig-vd.ch, dlemoal@kernel.org, alberto.dassatti@heig-vd.ch, Rick Wertenbroek , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] phy: rockchip-snps-pcie3: add support for rockchip,phy-ref-use-pad Date: Wed, 6 Aug 2025 15:38:22 +0200 Message-Id: <20250806133824.525871-3-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250806133824.525871-1-rick.wertenbroek@gmail.com> References: <20250806133824.525871-1-rick.wertenbroek@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" >From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "ref_use_pad" "Select reference clock connected to ref_pad_clk_p/ref_pad_clk_m. Selects the external ref_pad_clk_p and ref_pad_clk_m inputs as the reference clock source when asserted. When de-asserted, ref_alt_clk_p and ref_alt_clk_m are the sources of the reference clock." The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. Add support for the device tree property rockchip,phy-ref-use-pad, such that the PCIe PHY can be used on boards where there is no PCIe reference clock generated or connected to the external pad, by setting this property to 0 so that the internal clock is used. DT bindings for internal clocks are CLK_PHY0_REF_ALT_P/M and CLK_PHY1_REF_ALT_P/M and clock rate should be set to 100MHz in the RK3588 cru clock controller (PLL_PPLL). Example DT overlay where PHY0 uses internal clock (the first clock of the cru (PLL_PPLL) must be set to 100MHz, other values are copied from rk3588-base.dtsi) and PHY1 uses the external pad (the default): --- &cru { assigned-clock-rates =3D <100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, <800000000>, <100000000>, <400000000>, <100000000>, <200000000>, <500000000>, <375000000>, <150000000>, <200000000>; }; &pcie30phy { rockchip,rx-common-refclk-mode =3D <0 0 1 1>; rockchip,phy-ref-use-pad =3D <0 1>; clocks =3D <&cru PCLK_PCIE_COMBO_PIPE_PHY>, <&cru CLK_PHY0_REF_ALT_= P>, <&cru CLK_PHY0_REF_ALT_M>, <&cru CLK_PHY1_REF_ALT_= P>, <&cru CLK_PHY1_REF_ALT_M>; clock-names =3D "pclk", "phy0_ref_alt_p", "phy0_ref_alt_m", "phy1_ref_alt_p", "phy1_ref_alt_m"; }; --- Signed-off-by: Rick Wertenbroek --- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/r= ockchip/phy-rockchip-snps-pcie3.c index 4e8ffd173096..0859c7960167 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -33,6 +33,8 @@ /* Register for RK3588 */ #define PHP_GRF_PCIESEL_CON 0x100 #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 +#define RK3588_PCIE3PHY_GRF_PHY0_CONTROL6 0x118 +#define RK3588_PCIE3PHY_GRF_PHY1_CONTROL6 0x218 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 #define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004 @@ -44,6 +46,8 @@ #define RK3588_BIFURCATION_LANE_0_1 BIT(0) #define RK3588_BIFURCATION_LANE_2_3 BIT(1) #define RK3588_LANE_AGGREGATION BIT(2) +#define RK3588_PHY_REF_USE_PAD_EN ((BIT(2) << 16 | BIT(2))) +#define RK3588_PHY_REF_USE_PAD_DIS ((BIT(2) << 16)) #define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7)) #define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16) #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) @@ -67,6 +71,7 @@ struct rockchip_p3phy_priv { int num_lanes; u32 lanes[4]; u32 rx_cmn_refclk_mode[4]; + u32 phy_ref_use_pad[2]; }; =20 struct rockchip_p3phy_ops { @@ -157,6 +162,14 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_= p3phy_priv *priv) priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN : RK3588_RX_CMN_REFCLK_MODE_DIS); =20 + /* Select PHY reference clock, external pad or internal clock */ + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_CONTROL6, + priv->phy_ref_use_pad[0] ? RK3588_PHY_REF_USE_PAD_EN : + RK3588_PHY_REF_USE_PAD_DIS); + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_CONTROL6, + priv->phy_ref_use_pad[1] ? RK3588_PHY_REF_USE_PAD_EN : + RK3588_PHY_REF_USE_PAD_DIS); + /* Deassert PCIe PMA output clamp mode */ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24= )); =20 @@ -312,6 +325,25 @@ static int rockchip_p3phy_probe(struct platform_device= *pdev) return ret; } =20 + ret =3D of_property_read_variable_u32_array(dev->of_node, + "rockchip,phy-ref-use-pad", + priv->phy_ref_use_pad, 1, + ARRAY_SIZE(priv->phy_ref_use_pad)); + + /* + * if no rockhip,phy-use-internal-clk, assume PHY uses pad for the + * reference clock in order to be DT backwards compatible. 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charset="utf-8" >From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "ref_use_pad" "Select reference clock connected to ref_pad_clk_p/ref_pad_clk_m. Selects the external ref_pad_clk_p and ref_pad_clk_m inputs as the reference clock source when asserted. When de-asserted, ref_alt_clk_p and ref_alt_clk_m are the sources of the reference clock." The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. Add support for the device tree property rockchip,phy-ref-use-pad, such that the PCIe PHY can be used on boards where there is no PCIe reference clock generated or connected to the external pad, by setting this property to 0 so that the internal clock is used. DT bindings for internal clocks are CLK_PHY0_REF_ALT_P/M and CLK_PHY1_REF_ALT_P/M and clock rate should be set to 100MHz in the RK3588 cru clock controller (PLL_PPLL). Example DT overlay where PHY0 uses internal clock (the first clock of the cru (PLL_PPLL) must be set to 100MHz, other values are copied from rk3588-base.dtsi) and PHY1 uses the external pad (the default): --- &cru { assigned-clock-rates =3D <100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, <800000000>, <100000000>, <400000000>, <100000000>, <200000000>, <500000000>, <375000000>, <150000000>, <200000000>; }; &pcie30phy { rockchip,rx-common-refclk-mode =3D <0 0 1 1>; rockchip,phy-ref-use-pad =3D <0 1>; clocks =3D <&cru PCLK_PCIE_COMBO_PIPE_PHY>, <&cru CLK_PHY0_REF_ALT_= P>, <&cru CLK_PHY0_REF_ALT_M>, <&cru CLK_PHY1_REF_ALT_= P>, <&cru CLK_PHY1_REF_ALT_M>; clock-names =3D "pclk", "phy0_ref_alt_p", "phy0_ref_alt_m", "phy1_ref_alt_p", "phy1_ref_alt_m"; }; --- Signed-off-by: Rick Wertenbroek --- .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml = b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index b747930b18f1..d9b9d7eabb81 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -67,6 +67,16 @@ properties: minimum: 0 maximum: 1 =20 + rockchip,phy-ref-use-pad: + description: which PHY should use the external pad as PCIe reference c= lock. + 1 means use pad (default), 0 means use internal clock (PLL_PPLL). + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + required: - compatible - reg --=20 2.25.1