From nobody Sun Oct 5 10:51:12 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A2E128A1CE; Wed, 6 Aug 2025 09:00:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754470807; cv=none; b=uI6AqFCSSgYLp1ABSkP7KeYPCbnNbVhF/13k8G+1Y12oROgSGGBLjAwb7lZaFk1wg28WwWjrMgC02sAOHi1MrX7tzvluKr9sMswcyIiTtv87HaeKMeBfx65S3yfxjuKivZxPzS8isfVE3eMi+VBK6csjogeEhQVq73SdMxojFIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754470807; c=relaxed/simple; bh=gQ2VxAfH8pJtdmB8Nedfhcy6YYVctPFDpgFOyKBw13I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AwfXGlPLTL1X2a2nPCHxTh6whUnm6ugZD/20nH0FNNw2sUYNiUY/T0DjbU/h6clq9+ZIugrUK2qmhCn4WB5y3U3WcW+TfiUcCuVhWbilYFX67LyYHhadYCIiIsew9Jxr7ljswndhRzaSDoIkqXpKFmLZWFWg7Td2kESlu0yCMKw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qW9Aup5d; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qW9Aup5d" X-UUID: bac16b1a72a311f08871991801538c65-20250806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WfV6pBVG6f2M0H5LFLSxjS1en7Og6Q3bLsQWlgl7MfQ=; b=qW9Aup5dZq4QhanSf4CVTbsFNnWYvCOzIZGpw9u3kOFV7L3a3abUQcVluUGNscsm7HH0oaAD5OE7Sm6BbAcDakgTrTUTaBVB8Fh3YBH8SfLeDHP1iiafRLeKNDpYdpCJYK5Q44sW4eCWugePpYttBJWqmwjnwMSzg+1AIevJVp0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.2,REQID:1bb69f55-7c49-489d-8beb-04af11eb0913,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:9eb4ff7,CLOUDID:d14c2d09-aadc-4681-92d7-012627504691,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: bac16b1a72a311f08871991801538c65-20250806 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1476205335; Wed, 06 Aug 2025 16:59:58 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Wed, 6 Aug 2025 16:59:56 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Wed, 6 Aug 2025 16:59:55 +0800 From: Friday Yang To: Yong Wu , Krzysztof Kozlowski , "Rob Herring" , Conor Dooley , "Matthias Brugger" , AngeloGioacchino Del Regno , Philipp Zabel CC: Friday Yang , , , , , Subject: [PATCH v10 2/2] memory: mtk-smi: mt8188: Add SMI reset and clamp for MT8188 Date: Wed, 6 Aug 2025 16:59:36 +0800 Message-ID: <20250806085946.11383-3-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250806085946.11383-1-friday.yang@mediatek.com> References: <20250806085946.11383-1-friday.yang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To prevent handling glitch signals during MTCMOS on/off transitions, SMI requires clamp and reset operations. Parse the reset settings for SMI LARBs and the clamp settings for the SMI Sub-Common. Register genpd callback for the SMI LARBs located in image, camera and IPE subsystems, and apply reset and clamp operations within the callback. Signed-off-by: Friday Yang --- drivers/memory/mtk-smi.c | 129 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 733e22f695ab..acc8904dd117 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -10,11 +10,15 @@ #include #include #include +#include #include #include #include #include +#include #include +#include +#include #include #include #include @@ -34,6 +38,8 @@ #define SMI_FIFO_TH1 0x238 #define SMI_FIFO_TH2 0x23c #define SMI_DCM 0x300 +#define SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define SMI_COMMON_CLAMP_EN_CLR 0x3c8 #define SMI_DUMMY 0x444 =20 /* SMI LARB */ @@ -134,6 +140,7 @@ struct mtk_smi_larb_gen { unsigned int larb_direct_to_common_mask; unsigned int flags_general; const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; + const u8 *clamp_port; }; =20 struct mtk_smi { @@ -150,6 +157,7 @@ struct mtk_smi { }; =20 struct mtk_smi_larb { /* larb: local arbiter */ + struct device *dev; struct mtk_smi smi; void __iomem *base; struct device *smi_common_dev; /* common or sub-common dev */ @@ -157,6 +165,10 @@ struct mtk_smi_larb { /* larb: local arbiter */ int larbid; u32 *mmu; unsigned char *bank; + struct regmap *smi_comm_syscon; /* smi-comm or sub-comm */ + u8 smi_comm_in_port_id; /* smi-comm or sub-comm */ + struct notifier_block nb; + struct reset_control *rst_con; }; =20 static int @@ -478,6 +490,19 @@ static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PO= RT_NR_MAX] =3D { [28] =3D {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, }; =20 +static const u8 mtk_smi_larb_clamp_port_mt8188[MTK_LARB_NR_MAX] =3D { + [9] =3D BIT(1), /* larb10 */ + [10] =3D BIT(2), /* larb11a */ + [11] =3D BIT(2), /* larb11b */ + [12] =3D BIT(3), /* larb11c */ + [13] =3D BIT(0), /* larb12 */ + [16] =3D BIT(1), /* larb15 */ + [17] =3D BIT(2), /* larb16a */ + [18] =3D BIT(2), /* larb16b */ + [19] =3D BIT(3), /* larb17a */ + [20] =3D BIT(3), /* larb17b */ +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 =3D { .port_in_larb =3D { LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, @@ -531,6 +556,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt818= 8 =3D { .flags_general =3D MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW= _FLAG | MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, .ostd =3D mtk_smi_larb_mt8188_ostd, + .clamp_port =3D mtk_smi_larb_clamp_port_mt8188, }; =20 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 =3D { @@ -582,6 +608,45 @@ static void mtk_smi_larb_sleep_ctrl_disable(struct mtk= _smi_larb *larb) writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); } =20 +static int mtk_smi_larb_clamp_protect_enable(struct device *dev, bool enab= le) +{ + struct mtk_smi_larb *larb =3D dev_get_drvdata(dev); + u32 reg; + int ret; + + /* smi_comm_syscon may be NULL if the subsys doesn't have bus glitch issu= es */ + if (!larb->smi_comm_syscon) + return -EINVAL; + + reg =3D enable ? SMI_COMMON_CLAMP_EN_SET : SMI_COMMON_CLAMP_EN_CLR; + + ret =3D regmap_write(larb->smi_comm_syscon, reg, larb->smi_comm_in_port_i= d); + if (ret) + dev_err(dev, "Unable to %s clamp for input port %d: %d\n", + enable ? "enable" : "disable", + larb->smi_comm_in_port_id, ret); + + return ret; +} + +static int mtk_smi_genpd_callback(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct mtk_smi_larb *larb =3D container_of(nb, struct mtk_smi_larb, nb); + struct device *dev =3D larb->dev; + + if (flags =3D=3D GENPD_NOTIFY_PRE_ON || flags =3D=3D GENPD_NOTIFY_PRE_OFF= ) { + /* disable related SMI sub-common port */ + mtk_smi_larb_clamp_protect_enable(dev, true); + } else if (flags =3D=3D GENPD_NOTIFY_ON) { + /* enable related SMI sub-common port */ + reset_control_reset(larb->rst_con); + mtk_smi_larb_clamp_protect_enable(dev, false); + } + + return NOTIFY_OK; +} + static int mtk_smi_device_link_common(struct device *dev, struct device **= com_dev) { struct platform_device *smi_com_pdev; @@ -638,6 +703,51 @@ static int mtk_smi_dts_clk_init(struct device *dev, st= ruct mtk_smi *smi, return ret; } =20 +static int mtk_smi_larb_parse_clamp_optional(struct mtk_smi_larb *larb) +{ + struct device *dev =3D larb->dev; + const struct mtk_smi_larb_gen *larb_gen =3D larb->larb_gen; + u32 larb_id; + int ret; + + /* + * Only SMI LARBs in camera, image and IPE subsys need to + * apply clamp and reset operations, others can be skipped. + */ + ret =3D of_property_read_u32(dev->of_node, "mediatek,larb-id", &larb_id); + if (ret || !larb_gen->clamp_port || !larb_gen->clamp_port[larb_id]) + return 0; + + larb->smi_comm_in_port_id =3D larb_gen->clamp_port[larb_id]; + larb->smi_comm_syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "mediatek,smi"); + if (IS_ERR(larb->smi_comm_syscon)) { + larb->smi_comm_syscon =3D NULL; + return dev_err_probe(dev, -EINVAL, + "Unknown clamp port for larb %d\n", larb_id); + } + + return 0; +} + +static int mtk_smi_larb_parse_reset_optional(struct mtk_smi_larb *larb) +{ + struct device *dev =3D larb->dev; + int ret; + + larb->rst_con =3D devm_reset_control_get_optional_exclusive(dev, "larb"); + if (!larb->rst_con) + return 0; + + larb->nb.notifier_call =3D mtk_smi_genpd_callback; + ret =3D dev_pm_genpd_add_notifier(dev, &larb->nb); + if (ret) + return dev_err_probe(dev, -EINVAL, + "Failed to add genpd callback %d\n", ret); + + return 0; +} + static int mtk_smi_larb_probe(struct platform_device *pdev) { struct mtk_smi_larb *larb; @@ -648,6 +758,7 @@ static int mtk_smi_larb_probe(struct platform_device *p= dev) if (!larb) return -ENOMEM; =20 + larb->dev =3D dev; larb->larb_gen =3D of_device_get_match_data(dev); larb->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(larb->base)) @@ -664,6 +775,14 @@ static int mtk_smi_larb_probe(struct platform_device *= pdev) if (ret < 0) return ret; =20 + ret =3D mtk_smi_larb_parse_clamp_optional(larb); + if (ret) + goto err_link_remove; + + ret =3D mtk_smi_larb_parse_reset_optional(larb); + if (ret) + goto err_link_remove; + pm_runtime_enable(dev); platform_set_drvdata(pdev, larb); ret =3D component_add(dev, &mtk_smi_larb_component_ops); @@ -673,6 +792,7 @@ static int mtk_smi_larb_probe(struct platform_device *p= dev) =20 err_pm_disable: pm_runtime_disable(dev); +err_link_remove: device_link_remove(dev, larb->smi_common_dev); return ret; } @@ -681,6 +801,9 @@ static void mtk_smi_larb_remove(struct platform_device = *pdev) { struct mtk_smi_larb *larb =3D platform_get_drvdata(pdev); =20 + if (larb->nb.notifier_call) + dev_pm_genpd_remove_notifier(&pdev->dev); + device_link_remove(&pdev->dev, larb->smi_common_dev); pm_runtime_disable(&pdev->dev); component_del(&pdev->dev, &mtk_smi_larb_component_ops); @@ -803,6 +926,11 @@ static const struct mtk_smi_common_plat mtk_smi_common= _mt8188_vpp =3D { .init =3D mtk_smi_common_mt8195_init, }; =20 +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8188 =3D { + .type =3D MTK_SMI_GEN2_SUB_COMM, + .has_gals =3D true, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 =3D { .type =3D MTK_SMI_GEN2, .has_gals =3D true, @@ -847,6 +975,7 @@ static const struct of_device_id mtk_smi_common_of_ids[= ] =3D { {.compatible =3D "mediatek,mt8186-smi-common", .data =3D &mtk_smi_common_= mt8186}, {.compatible =3D "mediatek,mt8188-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8188_vdo}, {.compatible =3D "mediatek,mt8188-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8188_vpp}, + {.compatible =3D "mediatek,mt8188-smi-sub-common", .data =3D &mtk_smi_sub= _common_mt8188}, {.compatible =3D "mediatek,mt8192-smi-common", .data =3D &mtk_smi_common_= mt8192}, {.compatible =3D "mediatek,mt8195-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8195_vdo}, {.compatible =3D "mediatek,mt8195-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8195_vpp}, --=20 2.46.0