From nobody Sun Oct 5 09:07:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A06921CFEF; Wed, 6 Aug 2025 08:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468052; cv=none; b=n85iWu7RQ9JxNmHC/QLtuJFS6HkriMD2Ugnyz5tTFnBESqLFAiCOix3eXmoTtB2XK47DTWf4nSC9FfwNK8LKkoRcfyZgdaS62kTwiZ6RUYt4MdTR9ZhBxmeLLct5gwwnda5bzKeD0w2Gli3HMwqs9p4NtcW25ohSkop7VUqsm5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468052; c=relaxed/simple; bh=xAgcVzPGMizjBmMHVeIIS14F+79ugFsiTAhfGR0IMHk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dHqfMkQQ7RuanVoMxcXw5lUaZumIwXSAG8csvNym2FZj8sU4vOZv9Qh5NE7ezhniXXhwlU8qN5W6daqFKVmoyK8N0T4gv0TI7Z5DxwM9IAWxJz08d+jeuWGAiGrdFvU2b83iUtpdzc5QMjgxouG1nqy1XkU2Rk2H26AxGd1taTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MPc67Cyr; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MPc67Cyr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754468050; x=1786004050; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xAgcVzPGMizjBmMHVeIIS14F+79ugFsiTAhfGR0IMHk=; b=MPc67CyrwZcKiQIOiTcLbhiRmSZhdjQi9CNpv4Ul3JR1bI1Q1D+03Y54 s8SC097HmZCDm4IP6ysz9FnFltJUbC31p1EK8dXNijBIiu0cjLJMKbpg5 4PpEgle8UY7CwTj+5b+J9mWnYxp7Byvfod+f8VzA18fNc+87cpC6SbflS 0j930zbBzxVEkIxTIG6kSklBy5AFbVF4XJT3dlSTAaRHuqwNvsPCPfK0p uZcHvJcOaG5aLAo/BDu0FlQjUZvZ7aDxqVj0cOyNQg3V68RItwW6cAt+r hHUS1JpHftSBAoesrswh31UyLPpXdbXKM9XauiyJlbzCa4D0UVoBbg6pM g==; X-CSE-ConnectionGUID: ATnsr2KkRKm5ARAYP6EGNA== X-CSE-MsgGUID: fDJoS2aKSaKtjtm5uInQJg== X-IronPort-AV: E=McAfee;i="6800,10657,11513"; a="56853632" X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="56853632" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:10 -0700 X-CSE-ConnectionGUID: 7ghzxRoHQv2UhgWCby6oBg== X-CSE-MsgGUID: PP3+hXJWTquXNTAhqjkN8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="169168417" Received: from sschumil-mobl2.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.125]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:04 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v11 1/5] x86/sgx: Introduce functions to count the sgx_(vepc_)open() Date: Wed, 6 Aug 2025 11:11:52 +0300 Message-ID: <20250806081344.404004-2-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806081344.404004-1-elena.reshetova@intel.com> References: <20250806081344.404004-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently SGX does not have a global counter to count the active users from userspace or hypervisor. Define placeholder functions sgx_inc/dec_usage_count() that are used to increment and decrement such a counter. Also, wire the call sites for these functions. For the latter, in order to introduce the counting of active sgx users on top of clean functions that allocate vepc structures, covert existing sgx_(vepc_)open() to __sgx_(vepc_)open(). The definition of the counter itself and the actual implementation of these two functions comes next. The counter will be used by the driver that would be attempting to call EUPDATESVN SGX instruction only when incrementing from zero. Note: the sgx_inc_usage_count() prototype is defined to return int for the cleanliness of the follow-up patches despite always returning zero in this patch. When the EUPDATESVN SGX instruction will be enabled in the follow-up patch, the sgx_inc_usage_count() will start to return the actual return code. Suggested-by: Sean Christopherson Signed-off-by: Elena Reshetova Reviewed-by: Jarkko Sakkinen --- arch/x86/kernel/cpu/sgx/driver.c | 19 ++++++++++++++++++- arch/x86/kernel/cpu/sgx/encl.c | 1 + arch/x86/kernel/cpu/sgx/main.c | 10 ++++++++++ arch/x86/kernel/cpu/sgx/sgx.h | 3 +++ arch/x86/kernel/cpu/sgx/virt.c | 20 +++++++++++++++++++- 5 files changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/driver.c b/arch/x86/kernel/cpu/sgx/dri= ver.c index 7f8d1e11dbee..79d6020dfe9c 100644 --- a/arch/x86/kernel/cpu/sgx/driver.c +++ b/arch/x86/kernel/cpu/sgx/driver.c @@ -14,7 +14,7 @@ u64 sgx_attributes_reserved_mask; u64 sgx_xfrm_reserved_mask =3D ~0x3; u32 sgx_misc_reserved_mask; =20 -static int sgx_open(struct inode *inode, struct file *file) +static int __sgx_open(struct inode *inode, struct file *file) { struct sgx_encl *encl; int ret; @@ -41,6 +41,23 @@ static int sgx_open(struct inode *inode, struct file *fi= le) return 0; } =20 +static int sgx_open(struct inode *inode, struct file *file) +{ + int ret; + + ret =3D sgx_inc_usage_count(); + if (ret) + return ret; + + ret =3D __sgx_open(inode, file); + if (ret) { + sgx_dec_usage_count(); + return ret; + } + + return 0; +} + static int sgx_release(struct inode *inode, struct file *file) { struct sgx_encl *encl =3D file->private_data; diff --git a/arch/x86/kernel/cpu/sgx/encl.c b/arch/x86/kernel/cpu/sgx/encl.c index 308dbbae6c6e..cf149b9f4916 100644 --- a/arch/x86/kernel/cpu/sgx/encl.c +++ b/arch/x86/kernel/cpu/sgx/encl.c @@ -765,6 +765,7 @@ void sgx_encl_release(struct kref *ref) WARN_ON_ONCE(encl->secs.epc_page); =20 kfree(encl); + sgx_dec_usage_count(); } =20 /* diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 2de01b379aa3..3a5cbd1c170e 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -917,6 +917,16 @@ int sgx_set_attribute(unsigned long *allowed_attribute= s, } EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 +int sgx_inc_usage_count(void) +{ + return 0; +} + +void sgx_dec_usage_count(void) +{ + return; +} + static int __init sgx_init(void) { int ret; diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index d2dad21259a8..f5940393d9bd 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -102,6 +102,9 @@ static inline int __init sgx_vepc_init(void) } #endif =20 +int sgx_inc_usage_count(void); +void sgx_dec_usage_count(void); + void sgx_update_lepubkeyhash(u64 *lepubkeyhash); =20 #endif /* _X86_SGX_H */ diff --git a/arch/x86/kernel/cpu/sgx/virt.c b/arch/x86/kernel/cpu/sgx/virt.c index 7aaa3652e31d..b649c0610019 100644 --- a/arch/x86/kernel/cpu/sgx/virt.c +++ b/arch/x86/kernel/cpu/sgx/virt.c @@ -255,10 +255,11 @@ static int sgx_vepc_release(struct inode *inode, stru= ct file *file) xa_destroy(&vepc->page_array); kfree(vepc); =20 + sgx_dec_usage_count(); return 0; } =20 -static int sgx_vepc_open(struct inode *inode, struct file *file) +static int __sgx_vepc_open(struct inode *inode, struct file *file) { struct sgx_vepc *vepc; =20 @@ -273,6 +274,23 @@ static int sgx_vepc_open(struct inode *inode, struct f= ile *file) return 0; } =20 +static int sgx_vepc_open(struct inode *inode, struct file *file) +{ + int ret; + + ret =3D sgx_inc_usage_count(); + if (ret) + return ret; + + ret =3D __sgx_vepc_open(inode, file); + if (ret) { + sgx_dec_usage_count(); + return ret; + } + + return 0; +} + static long sgx_vepc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { --=20 2.45.2 From nobody Sun Oct 5 09:07:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF11E221275; Wed, 6 Aug 2025 08:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468061; cv=none; b=VVHOpCkq6r3LUc65wZeH+eqLrB18eiGv6HcQ5t/FLkPYRD/suoFVpIpcawRDnkvWzhiL2YbwZ8nhqpyGOUqUVv78HhFnwUxMlctCnTo6Yt81dssDdh1xjk1yYPcoC0AtUaypYYJTwdSWsgCaEhRPS15xtMz3PivsnlvIEeN+NMU= ARC-Message-Signature: i=1; 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d="scan'208";a="169168476" Received: from sschumil-mobl2.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.125]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:10 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova , Dave Hansen Subject: [PATCH v11 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag Date: Wed, 6 Aug 2025 11:11:53 +0300 Message-ID: <20250806081344.404004-3-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806081344.404004-1-elena.reshetova@intel.com> References: <20250806081344.404004-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is supported. This will be used by SGX driver to perform CPU SVN updates. Reviewed-by: Dave Hansen Signed-off-by: Elena Reshetova Reviewed-by: Jarkko Sakkinen --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 602957dd2609..830d24ff1ada 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -494,6 +494,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..3d9f49ad0efd 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, + { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 }, { X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 }, { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..d13444d11ba0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, + { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 }, { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ee176236c2be..78c3894c17c1 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -487,6 +487,7 @@ #define X86_FEATURE_PREFER_YMM (21*32+ 8) /* Avoid ZMM registers due to d= ownclocking */ #define X86_FEATURE_APX (21*32+ 9) /* Advanced Performance Extensions */ #define X86_FEATURE_INDIRECT_THUNK_ITS (21*32+10) /* Use thunk for indirec= t branches in lower half of cacheline */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) --=20 2.45.2 From nobody Sun Oct 5 09:07:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8648220F3F; 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a="56853647" X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="56853647" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:24 -0700 X-CSE-ConnectionGUID: RBQS5ZuSR5OUT+lC1L6jEg== X-CSE-MsgGUID: BNpT2Q5mSKmq9gr30eJheQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="169168499" Received: from sschumil-mobl2.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.125]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:18 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v11 3/5] x86/sgx: Define error codes for use by ENCLS[EUPDATESVN] Date: Wed, 6 Aug 2025 11:11:54 +0300 Message-ID: <20250806081344.404004-4-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806081344.404004-1-elena.reshetova@intel.com> References: <20250806081344.404004-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add error codes for ENCLS[EUPDATESVN], then SGX CPUSVN update process can know the execution state of EUPDATESVN and notify userspace. Signed-off-by: Elena Reshetova Reviewed-by: Jarkko Sakkinen --- arch/x86/include/asm/sgx.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h index 6a0069761508..2da5b3b117a1 100644 --- a/arch/x86/include/asm/sgx.h +++ b/arch/x86/include/asm/sgx.h @@ -73,6 +73,10 @@ enum sgx_encls_function { * public key does not match IA32_SGXLEPUBKEYHASH. * %SGX_PAGE_NOT_MODIFIABLE: The EPC page cannot be modified because it * is in the PENDING or MODIFIED state. + * %SGX_INSUFFICIENT_ENTROPY: Insufficient entropy in RNG. + * %SGX_NO_UPDATE: EUPDATESVN could not update the CPUSVN because the + * current SVN was not newer than CPUSVN. This is the most + * common error code returned by EUPDATESVN. * %SGX_UNMASKED_EVENT: An unmasked event, e.g. INTR, was received */ enum sgx_return_code { @@ -81,6 +85,8 @@ enum sgx_return_code { SGX_CHILD_PRESENT =3D 13, SGX_INVALID_EINITTOKEN =3D 16, SGX_PAGE_NOT_MODIFIABLE =3D 20, + SGX_INSUFFICIENT_ENTROPY =3D 29, + SGX_NO_UPDATE =3D 31, SGX_UNMASKED_EVENT =3D 128, }; =20 --=20 2.45.2 From nobody Sun Oct 5 09:07:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A221223DCB; Wed, 6 Aug 2025 08:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468072; cv=none; b=Gh55PXmUhHkmTtm2FDKc8Plk3XFhc80gDmXtVd/USnjJ8YgXA6WIEWTkNiiWTQRHE2NHATt+iyrKC5fpfjjenORVIf0JQvf09nZjY1WueExxbWj4Cia0sogwSHEclgcQwcHRM0pJzTleNOuZgZFV6uAzcaVG6BxEN9I6Wz/dcgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468072; c=relaxed/simple; bh=fcqlzyuS/YzqYrSmE4OP/INq3SU1BAdodt9l/bO7U3E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sci81OD7o4pRxO9mmaPCGUr190oehDHvROKqetpThNNiMqIej351+2JjoXI5doyi3Vq0dTbEe84jNLtwcLgPr7NTfoWxWf1/Ouae8W63R9mkLeh+PrUt15TTu+MEOwGidULBxPCqdAjLxjUTUgxhi0lycFq4KPP/Z8On9Kcu8hc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lQVM80pL; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lQVM80pL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754468070; x=1786004070; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fcqlzyuS/YzqYrSmE4OP/INq3SU1BAdodt9l/bO7U3E=; b=lQVM80pLzwXhLo8X+ZBLKPYDtvGYBKqUFlbJW3V5u4HiKhU6oqGnRmVn zo1duVEM7nVn1mAT4Dpm6wv+rj69LaimV3Lls0MEhKIbJWYh+t46llVWY aCCvEb3FLfFEeLIgscg5y0z54Ox4qUrNAzz7SuMIYEFwxkqKAado/leTN GWXqc01j0XvWWhb5nz7g2TWUi3IkO9aB3b+vxF5gii6e3XDZveIguFhvm /CFatL3nA9h+JhlUeyNvueqvmjBNzWjOGMBPTflVmZMtwU10YmO/QEJnn qKCzu+bPlNlojPQ0fRO3yQieMdZRsUwiqzay5l0IyCDV41VowYkHTqwQ/ g==; X-CSE-ConnectionGUID: HONEu1rSTl6YPsnVmgiFKg== X-CSE-MsgGUID: 05+xIxhGS0a3OqUJzt6oYw== X-IronPort-AV: E=McAfee;i="6800,10657,11513"; a="56853679" X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="56853679" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:30 -0700 X-CSE-ConnectionGUID: DqyY1v7wQbeQRAm/Nz1g0Q== X-CSE-MsgGUID: KN1iY1X8SjC+8m8Z9bVh+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="169168529" Received: from sschumil-mobl2.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.125]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:23 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v11 4/5] x86/sgx: Implement ENCLS[EUPDATESVN] Date: Wed, 6 Aug 2025 11:11:55 +0300 Message-ID: <20250806081344.404004-5-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806081344.404004-1-elena.reshetova@intel.com> References: <20250806081344.404004-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All running enclaves and cryptographic assets (such as internal SGX encryption keys) are assumed to be compromised whenever an SGX-related microcode update occurs. To mitigate this assumed compromise the new supervisor SGX instruction ENCLS[EUPDATESVN] can generate fresh cryptographic assets. Before executing EUPDATESVN, all SGX memory must be marked as unused. This requirement ensures that no potentially compromised enclave survives the update and allows the system to safely regenerate cryptographic assets. Add the method to perform ENCLS[EUPDATESVN]. However, until the follow up patch that wires calling sgx_update_svn() from sgx_inc_usage_count(), this code is not reachable. Signed-off-by: Elena Reshetova Reviewed-by: Jarkko Sakkinen --- arch/x86/include/asm/sgx.h | 31 +++++++------- arch/x86/kernel/cpu/sgx/encls.h | 5 +++ arch/x86/kernel/cpu/sgx/main.c | 73 +++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h index 2da5b3b117a1..0e13678f9cbd 100644 --- a/arch/x86/include/asm/sgx.h +++ b/arch/x86/include/asm/sgx.h @@ -28,21 +28,22 @@ #define SGX_CPUID_EPC_MASK GENMASK(3, 0) =20 enum sgx_encls_function { - ECREATE =3D 0x00, - EADD =3D 0x01, - EINIT =3D 0x02, - EREMOVE =3D 0x03, - EDGBRD =3D 0x04, - EDGBWR =3D 0x05, - EEXTEND =3D 0x06, - ELDU =3D 0x08, - EBLOCK =3D 0x09, - EPA =3D 0x0A, - EWB =3D 0x0B, - ETRACK =3D 0x0C, - EAUG =3D 0x0D, - EMODPR =3D 0x0E, - EMODT =3D 0x0F, + ECREATE =3D 0x00, + EADD =3D 0x01, + EINIT =3D 0x02, + EREMOVE =3D 0x03, + EDGBRD =3D 0x04, + EDGBWR =3D 0x05, + EEXTEND =3D 0x06, + ELDU =3D 0x08, + EBLOCK =3D 0x09, + EPA =3D 0x0A, + EWB =3D 0x0B, + ETRACK =3D 0x0C, + EAUG =3D 0x0D, + EMODPR =3D 0x0E, + EMODT =3D 0x0F, + EUPDATESVN =3D 0x18, }; =20 /** diff --git a/arch/x86/kernel/cpu/sgx/encls.h b/arch/x86/kernel/cpu/sgx/encl= s.h index 99004b02e2ed..d9160c89a93d 100644 --- a/arch/x86/kernel/cpu/sgx/encls.h +++ b/arch/x86/kernel/cpu/sgx/encls.h @@ -233,4 +233,9 @@ static inline int __eaug(struct sgx_pageinfo *pginfo, v= oid *addr) return __encls_2(EAUG, pginfo, addr); } =20 +/* Attempt to update CPUSVN at runtime. */ +static inline int __eupdatesvn(void) +{ + return __encls_ret_1(EUPDATESVN, ""); +} #endif /* _X86_ENCLS_H */ diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 3a5cbd1c170e..d8c42524b590 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "driver.h" #include "encl.h" #include "encls.h" @@ -917,6 +918,78 @@ int sgx_set_attribute(unsigned long *allowed_attribute= s, } EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 +/* Counter to count the active SGX users */ +static int sgx_usage_count; + +/** + * sgx_update_svn() - Attempt to call ENCLS[EUPDATESVN]. + * This instruction attempts to update CPUSVN to the + * currently loaded microcode update SVN and generate new + * cryptographic assets. + * Return: + * 0: Success or not supported + * -EAGAIN: Can be safely retried, failure is due to lack of + * entropy in RNG. + * -EIO: Unexpected error, retries are not advisable. + */ +static int __maybe_unused sgx_update_svn(void) +{ + int ret; + + /* + * If EUPDATESVN is not available, it is ok to + * silently skip it to comply with legacy behavior. + */ + if (!cpu_feature_enabled(X86_FEATURE_SGX_EUPDATESVN)) + return 0; + + /* + * EPC is guaranteed to be empty when there are no users. + * Ensure we are on our first user before proceeding further. + */ + WARN(sgx_usage_count !=3D 1, "Elevated usage count when calling EUPDATESV= N\n"); + + for (int i =3D 0; i < RDRAND_RETRY_LOOPS; i++) { + ret =3D __eupdatesvn(); + + /* Stop on success or unexpected errors: */ + if (ret !=3D SGX_INSUFFICIENT_ENTROPY) + break; + } + + switch (ret) { + /* + * SVN successfully updated. + * Let users know when the update was successful. + */ + case 0: + pr_info("SVN updated successfully\n"); + return 0; + /* + * SVN update failed since the current SVN is + * not newer than CPUSVN. This is the most + * common case and indicates no harm. + */ + case SGX_NO_UPDATE: + return 0; + /* + * SVN update failed due to lack of entropy in DRNG. + * Indicate to userspace that it should retry. + */ + case SGX_INSUFFICIENT_ENTROPY: + return -EAGAIN; + default: + break; + } + + /* + * EUPDATESVN was called when EPC is empty, all other error + * codes are unexpected. + */ + ENCLS_WARN(ret, "EUPDATESVN"); + return -EIO; +} + int sgx_inc_usage_count(void) { return 0; --=20 2.45.2 From nobody Sun Oct 5 09:07:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BEA3223DCB; Wed, 6 Aug 2025 08:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468080; cv=none; b=E8aNMg0TqERV/J0Um3qiGdanJRFLF9CIDTX1AVY62jOw7mD/Z5rFHW1GJRqk3zkxHKcqoONV1edZpXwqod+lzSIZZJhSmiGAx0FGzAXXEx+P87POE7BgDxQqgq7xHkU/0MQBfiiZxK+W3nQkL4E7l/zibho4Y+7JPFCATSfb4t4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754468080; c=relaxed/simple; bh=SxCU4TucgzhtSAI2BWtrWX3S2pYMUQHVykQovHNThKs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZqroZZbAvs3bB5qD/Je66f13lWDyPO5LWPgJ67ClZyk7nOTyRgHv/LmZN64IU7oy8zVVtTp0sJhyPLQDN7Zo+TAd6MolwGy332yHHsigvtMURfVmZIUNr+ZRX0SxmH7oc14eIIz7WB3jNEy3Vyrvp3Q394Au7l+m+8wgb6yM/wI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YVVH5EFw; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YVVH5EFw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754468079; x=1786004079; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SxCU4TucgzhtSAI2BWtrWX3S2pYMUQHVykQovHNThKs=; b=YVVH5EFwncmvao4kFvVmvT/yndUYlk/loqv7VuftU+/y7gnJO5+uTc9Q wro5qarH4Gr2IxMBRXdbZm022W/9zTdtUmuYm3958J9D396CzOr0ulGjd b2wrpkcsDVb2oSR/a1eiBA5ntUFn3DHqxTtULz4mW88kZ6GXzay+7D26k GhR4yKFdJn50hRgOQ+U0odd55ZqD0Git3M8YxorLB7+waPqR2qtsKJuw0 XAuTnES0JuUpf59MPs1EFWkjtNLelwfBqKI7L4UNeXEFwwDhos6vuR7n/ B8FwxQLyvgIKFA5JR1hl5TPvG0d60FnjIq/y3GKYcBQwb6MK8rcfFGsYh g==; X-CSE-ConnectionGUID: tm/9MNgFRdmmH0HYv71GpQ== X-CSE-MsgGUID: atf+G4OQT/abFflWbS5vdw== X-IronPort-AV: E=McAfee;i="6800,10657,11513"; a="56853724" X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="56853724" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:37 -0700 X-CSE-ConnectionGUID: a3uPE6YBTP+zd0gYq+f6jA== X-CSE-MsgGUID: akXaskC/SHGx6A9S1w9JKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,268,1747724400"; d="scan'208";a="169168559" Received: from sschumil-mobl2.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.244.125]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2025 01:14:30 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v11 5/5] x86/sgx: Enable automatic SVN updates for SGX enclaves Date: Wed, 6 Aug 2025 11:11:56 +0300 Message-ID: <20250806081344.404004-6-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806081344.404004-1-elena.reshetova@intel.com> References: <20250806081344.404004-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable =3D=3D Background =3D=3D ENCLS[EUPDATESVN] is a new SGX instruction [1] which allows enclave attestation to include information about updated microcode SVN without a reboot. Before an EUPDATESVN operation can be successful, all SGX memory (aka. EPC) must be marked as =E2=80=9Cunused=E2=80=9D in the SGX hardware m= etadata (aka.EPCM). This requirement ensures that no compromised enclave can survive the EUPDATESVN procedure and provides an opportunity to generate new cryptographic assets. =3D=3D Solution =3D=3D Attempt to execute ENCLS[EUPDATESVN] every time the first file descriptor is obtained via sgx_(vepc_)open(). In the most common case the microcode SVN is already up-to-date, and the operation succeeds without updating SVN. Note: while in such cases the underlying CR_BASE_KEY is regenrated, it does not affect enclaves' visible keys obtained via EGETKEY instruction. If it fails with any other error code than SGX_INSUFFICIENT_ENTROPY, this is considered unexpected and the *open() returns an error. This should not happen in practice. On contrary, SGX_INSUFFICIENT_ENTROPY might happen due to a pressure on the system's DRNG (RDSEED) and therefore the *open() can be safely retried to allow normal enclave operation. [1] Runtime Microcode Updates with Intel Software Guard Extensions, https://cdrdv2.intel.com/v1/dl/getContent/648682 Signed-off-by: Elena Reshetova Reviewed-by: Jarkko Sakkinen --- arch/x86/kernel/cpu/sgx/main.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index d8c42524b590..b6f024802026 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -932,7 +932,7 @@ static int sgx_usage_count; * entropy in RNG. * -EIO: Unexpected error, retries are not advisable. */ -static int __maybe_unused sgx_update_svn(void) +static int sgx_update_svn(void) { int ret; =20 @@ -990,14 +990,22 @@ static int __maybe_unused sgx_update_svn(void) return -EIO; } =20 +/* Mutex to ensure no concurrent EPC accesses during EUPDATESVN */ +static DEFINE_MUTEX(sgx_svn_lock); + int sgx_inc_usage_count(void) { + guard(mutex)(&sgx_svn_lock); + + if (sgx_usage_count++ =3D=3D 0) + return sgx_update_svn(); + return 0; } =20 void sgx_dec_usage_count(void) { - return; + sgx_usage_count--; } =20 static int __init sgx_init(void) --=20 2.45.2