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([141.11.79.172]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfcf531sm14068499b3a.92.2025.08.05.19.05.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 19:05:41 -0700 (PDT) From: ChenMiao To: Linux Kernel Cc: Linux OpenRISC , chenmiao , Jonas Bonn , Stefan Kristiansson , Stafford Horne , "Mike Rapoport (Microsoft)" , Geert Uytterhoeven , Arnd Bergmann , Luis Chamberlain , Sahil Siddiq , Johannes Berg , Nicolas Schier , Masahiro Yamada , Dave Hansen , Andrew Morton Subject: [PATCH v2 1/2] openrisc: Add text patching API support Date: Wed, 6 Aug 2025 02:05:03 +0000 Message-ID: <20250806020520.570988-2-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806020520.570988-1-chenmiao.ku@gmail.com> References: <20250806020520.570988-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao We need a text patching mechanism to ensure that in the subsequent implementation of jump_label, the code can be modified to the correct location. Therefore, FIX_TEXT_POKE0 has been added as a mapping area. And, I create a new file named insn-def.h to define the or1k insn macro size and more define in the future. Among these changes, we implement patch_map and support the patch_insn_write API for single instruction writing. - V2: We modify the patch_insn_write(void *addr, const void *insn) API to patch_insn_write(void *addr, u32 insn), derectly support a single u32 instruction write to map memory. Link: https://lore.kernel.org/openrisc/aJIC8o1WmVHol9RY@antec/T/#t Signed-off-by: chenmiao --- arch/openrisc/include/asm/Kbuild | 1 - arch/openrisc/include/asm/fixmap.h | 1 + arch/openrisc/include/asm/insn-def.h | 12 ++++ arch/openrisc/include/asm/text-patching.h | 13 ++++ arch/openrisc/kernel/Makefile | 1 + arch/openrisc/kernel/patching.c | 79 +++++++++++++++++++++++ arch/openrisc/mm/init.c | 2 +- 7 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 arch/openrisc/include/asm/insn-def.h create mode 100644 arch/openrisc/include/asm/text-patching.h create mode 100644 arch/openrisc/kernel/patching.c diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/K= build index 2b1a6b00cdac..cef49d60d74c 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -9,4 +9,3 @@ generic-y +=3D spinlock.h generic-y +=3D qrwlock_types.h generic-y +=3D qrwlock.h generic-y +=3D user.h -generic-y +=3D text-patching.h diff --git a/arch/openrisc/include/asm/fixmap.h b/arch/openrisc/include/asm= /fixmap.h index aaa6a26a3e92..74000215064d 100644 --- a/arch/openrisc/include/asm/fixmap.h +++ b/arch/openrisc/include/asm/fixmap.h @@ -28,6 +28,7 @@ =20 enum fixed_addresses { FIX_EARLYCON_MEM_BASE, + FIX_TEXT_POKE0, __end_of_fixed_addresses }; =20 diff --git a/arch/openrisc/include/asm/insn-def.h b/arch/openrisc/include/a= sm/insn-def.h new file mode 100644 index 000000000000..dc8d16db1579 --- /dev/null +++ b/arch/openrisc/include/asm/insn-def.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + */ + +#ifndef __ASM_INSN_DEF_H +#define __ASM_INSN_DEF_H + +/* or1k instructions are always 32 bits. */ +#define OPENRISC_INSN_SIZE 4 + +#endif /* __ASM_INSN_DEF_H */ diff --git a/arch/openrisc/include/asm/text-patching.h b/arch/openrisc/incl= ude/asm/text-patching.h new file mode 100644 index 000000000000..bffe828288c3 --- /dev/null +++ b/arch/openrisc/include/asm/text-patching.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + */ + +#ifndef _ASM_PATCHING_H_ +#define _ASM_PATCHING_H_ + +#include + +int patch_insn_write(void *addr, u32 insn); + +#endif /* _ASM_PATCHING_H_ */ diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index 58e6a1b525b7..f0957ce16d6b 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -13,5 +13,6 @@ obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o obj-$(CONFIG_MODULES) +=3D module.o obj-$(CONFIG_OF) +=3D prom.o +obj-y +=3D patching.o =20 clean: diff --git a/arch/openrisc/kernel/patching.c b/arch/openrisc/kernel/patchin= g.c new file mode 100644 index 000000000000..c9a30f0d1193 --- /dev/null +++ b/arch/openrisc/kernel/patching.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2020 SiFive + * Copyright (C) 2025 Chen Miao + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static DEFINE_RAW_SPINLOCK(patch_lock); + +static inline bool is_exit_text(uintptr_t addr) +{ + /* Now Have NO Mechanism to do */ + return true; +} + +static __always_inline void *patch_map(void *addr, int fixmap) +{ + uintptr_t uaddr =3D (uintptr_t) addr; + phys_addr_t phys; + + if (core_kernel_text(uaddr) || is_exit_text(uaddr)) { + phys =3D __pa_symbol(addr); + } else { + struct page *page =3D vmalloc_to_page(addr); + BUG_ON(!page); + phys =3D page_to_phys(page) + offset_in_page(addr); + } + + return (void *)set_fixmap_offset(fixmap, phys); +} + +static void patch_unmap(int fixmap) +{ + clear_fixmap(fixmap); +} + +static int __patch_insn_write(void *addr, u32 insn) +{ + void *waddr =3D addr; + unsigned long flags =3D 0; + int ret; + + raw_spin_lock_irqsave(&patch_lock, flags); + + waddr =3D patch_map(addr, FIX_TEXT_POKE0); + + ret =3D copy_to_kernel_nofault(waddr, &insn, OPENRISC_INSN_SIZE); + local_icache_range_inv((unsigned long)waddr, + (unsigned long)waddr + OPENRISC_INSN_SIZE); + + patch_unmap(FIX_TEXT_POKE0); + + raw_spin_unlock_irqrestore(&patch_lock, flags); + + return ret; +} + +int patch_insn_write(void *addr, u32 insn) +{ + u32 *tp =3D addr; + int ret; + + if ((uintptr_t) tp & 0x3) + return -EINVAL; + + ret =3D __patch_insn_write(tp, insn); + + return ret; +} diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index e4904ca6f0a0..b5925710f954 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -226,7 +226,7 @@ static int __init map_page(unsigned long va, phys_addr_= t pa, pgprot_t prot) return 0; } =20 -void __init __set_fixmap(enum fixed_addresses idx, +void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) { unsigned long address =3D __fix_to_virt(idx); --=20 2.45.2 From nobody Sun Oct 5 09:10:54 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7422A38DDB; Wed, 6 Aug 2025 02:05:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([141.11.79.172]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfcf531sm14068499b3a.92.2025.08.05.19.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 19:05:54 -0700 (PDT) From: ChenMiao To: Linux Kernel Cc: Linux OpenRISC , chenmiao , Jonathan Corbet , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Peter Zijlstra , Josh Poimboeuf , Jason Baron , Steven Rostedt , Ard Biesheuvel , Masahiro Yamada , Sahil Siddiq , Nicolas Schier , Johannes Berg , linux-doc@vger.kernel.org Subject: [PATCH v2 2/2] openrisc: Add jump label support Date: Wed, 6 Aug 2025 02:05:04 +0000 Message-ID: <20250806020520.570988-3-chenmiao.ku@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250806020520.570988-1-chenmiao.ku@gmail.com> References: <20250806020520.570988-1-chenmiao.ku@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: chenmiao Implemented the full functionality of jump_label, of course, with text patching supported by just one API. By the way, add new macro OPENRISC_INSN_NOP in insn-def.h to use. - V2: using the patch_insn_write(void *addr, u32 insn) not the const void *insn. Link: https://lore.kernel.org/openrisc/aJIC8o1WmVHol9RY@antec/T/#t Signed-off-by: chenmiao --- .../core/jump-labels/arch-support.txt | 2 +- arch/openrisc/Kconfig | 2 + arch/openrisc/configs/or1ksim_defconfig | 19 ++---- arch/openrisc/configs/virt_defconfig | 1 + arch/openrisc/include/asm/insn-def.h | 3 + arch/openrisc/include/asm/jump_label.h | 68 +++++++++++++++++++ arch/openrisc/kernel/Makefile | 1 + arch/openrisc/kernel/jump_label.c | 53 +++++++++++++++ arch/openrisc/kernel/setup.c | 2 + 9 files changed, 138 insertions(+), 13 deletions(-) create mode 100644 arch/openrisc/include/asm/jump_label.h create mode 100644 arch/openrisc/kernel/jump_label.c diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Doc= umentation/features/core/jump-labels/arch-support.txt index ccada815569f..683de7c15058 100644 --- a/Documentation/features/core/jump-labels/arch-support.txt +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -17,7 +17,7 @@ | microblaze: | TODO | | mips: | ok | | nios2: | TODO | - | openrisc: | TODO | + | openrisc: | ok | | parisc: | ok | | powerpc: | ok | | riscv: | ok | diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index b38fee299bc4..9156635dd264 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -24,6 +24,8 @@ config OPENRISC select GENERIC_PCI_IOMAP select GENERIC_IOREMAP select GENERIC_CPU_DEVICES + select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_PCI select HAVE_UID16 select HAVE_PAGE_SIZE_8KB diff --git a/arch/openrisc/configs/or1ksim_defconfig b/arch/openrisc/config= s/or1ksim_defconfig index 59fe33cefba2..769705ac24d5 100644 --- a/arch/openrisc/configs/or1ksim_defconfig +++ b/arch/openrisc/configs/or1ksim_defconfig @@ -3,26 +3,23 @@ CONFIG_LOG_BUF_SHIFT=3D14 CONFIG_BLK_DEV_INITRD=3Dy # CONFIG_RD_GZIP is not set CONFIG_EXPERT=3Dy -# CONFIG_KALLSYMS is not set # CONFIG_EPOLL is not set # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLUB=3Dy -CONFIG_SLUB_TINY=3Dy -CONFIG_MODULES=3Dy -# CONFIG_BLOCK is not set +# CONFIG_KALLSYMS is not set CONFIG_BUILTIN_DTB_NAME=3D"or1ksim" CONFIG_HZ_100=3Dy +CONFIG_JUMP_LABEL=3Dy +CONFIG_MODULES=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set CONFIG_NET=3Dy CONFIG_PACKET=3Dy CONFIG_UNIX=3Dy CONFIG_INET=3Dy -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set CONFIG_TCP_CONG_ADVANCED=3Dy # CONFIG_TCP_CONG_BIC is not set @@ -35,7 +32,6 @@ CONFIG_DEVTMPFS=3Dy CONFIG_DEVTMPFS_MOUNT=3Dy # CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set -CONFIG_PROC_DEVICETREE=3Dy CONFIG_NETDEVICES=3Dy CONFIG_ETHOC=3Dy CONFIG_MICREL_PHY=3Dy @@ -53,4 +49,3 @@ CONFIG_SERIAL_OF_PLATFORM=3Dy # CONFIG_DNOTIFY is not set CONFIG_TMPFS=3Dy CONFIG_NFS_FS=3Dy -# CONFIG_ENABLE_MUST_CHECK is not set diff --git a/arch/openrisc/configs/virt_defconfig b/arch/openrisc/configs/v= irt_defconfig index c1b69166c500..4a80c5794877 100644 --- a/arch/openrisc/configs/virt_defconfig +++ b/arch/openrisc/configs/virt_defconfig @@ -12,6 +12,7 @@ CONFIG_NR_CPUS=3D8 CONFIG_SMP=3Dy CONFIG_HZ_100=3Dy # CONFIG_OPENRISC_NO_SPR_SR_DSX is not set +CONFIG_JUMP_LABEL=3Dy # CONFIG_COMPAT_BRK is not set CONFIG_NET=3Dy CONFIG_PACKET=3Dy diff --git a/arch/openrisc/include/asm/insn-def.h b/arch/openrisc/include/a= sm/insn-def.h index dc8d16db1579..2ccdbb37c27c 100644 --- a/arch/openrisc/include/asm/insn-def.h +++ b/arch/openrisc/include/asm/insn-def.h @@ -9,4 +9,7 @@ /* or1k instructions are always 32 bits. */ #define OPENRISC_INSN_SIZE 4 =20 +/* or1k nop instruction code */ +#define OPENRISC_INSN_NOP 0x15000000U + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/openrisc/include/asm/jump_label.h b/arch/openrisc/include= /asm/jump_label.h new file mode 100644 index 000000000000..03afca9c3a1f --- /dev/null +++ b/arch/openrisc/include/asm/jump_label.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Chen Miao + * + * Based on arch/arm/include/asm/jump_label.h + */ +#ifndef __ASM_JUMP_LABEL_H +#define __ASM_JUMP_LABEL_H + +#ifndef __ASSEMBLY__ + +#include +#include + +#define HAVE_JUMP_LABEL_BATCH + +#define JUMP_LABEL_NOP_SIZE OPENRISC_INSN_SIZE + +/* + * should aligned 4 + * for jump_label relative + * entry.code =3D nop.addr - . -> return false + * entry.target =3D l_yes - . -> return true + * entry.key =3D key - . + */ +#define JUMP_TABLE_ENTRY(key, label) \ + ".pushsection __jump_table, \"aw\" \n\t" \ + ".align 4 \n\t" \ + ".long 1b - ., " label " - . \n\t" \ + ".long " key " - . \n\t" \ + ".popsection \n\t" + +#define ARCH_STATIC_BRANCH_ASM(key, label) \ + ".align 4 \n\t" \ + "1: l.nop \n\t" \ + " l.nop \n\t" \ + JUMP_TABLE_ENTRY(key, label) + +static __always_inline bool arch_static_branch(struct static_key *const ke= y, + const bool branch) +{ + asm goto (ARCH_STATIC_BRANCH_ASM("%0", "%l[l_yes]") + ::"i"(&((char *)key)[branch])::l_yes); + + return false; +l_yes: + return true; +} + +#define ARCH_STATIC_BRANCH_JUMP_ASM(key, label) \ + ".align 4 \n\t" \ + "1: l.j " label " \n\t" \ + " l.nop \n\t" \ + JUMP_TABLE_ENTRY(key, label) + +static __always_inline bool +arch_static_branch_jump(struct static_key *const key, const bool branch) +{ + asm goto (ARCH_STATIC_BRANCH_JUMP_ASM("%0", "%l[l_yes]") + ::"i"(&((char *)key)[branch])::l_yes); + + return false; +l_yes: + return true; +} + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_JUMP_LABEL_H */ diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index f0957ce16d6b..19e0eb94f2eb 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -9,6 +9,7 @@ obj-y :=3D head.o setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ sys_call_table.o unwinder.o cacheinfo.o =20 +obj-$(CONFIG_JUMP_LABEL) +=3D jump_label.o obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o obj-$(CONFIG_MODULES) +=3D module.o diff --git a/arch/openrisc/kernel/jump_label.c b/arch/openrisc/kernel/jump_= label.c new file mode 100644 index 000000000000..ce259ba30258 --- /dev/null +++ b/arch/openrisc/kernel/jump_label.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Chen Miao + * + * Based on arch/arm/kernel/jump_label.c + */ +#include +#include +#include +#include +#include +#include + +bool arch_jump_label_transform_queue(struct jump_entry *entry, + enum jump_label_type type) +{ + void *addr =3D (void *)jump_entry_code(entry); + u32 insn; + + if (type =3D=3D JUMP_LABEL_JMP) { + long offset; + + offset =3D jump_entry_target(entry) - jump_entry_code(entry); + /* + * The actual maximum range of the l.j instruction's offset is -134,217,= 728 + * ~ 134,217,724 (sign 26-bit imm). + * For the original jump range, we need to right-shift N by 2 to obtain = the + * instruction's offset. + */ + if (unlikely(offset < -134217728 || offset > 134217724)) { + WARN_ON_ONCE(true); + } + /* 26bit imm mask */ + offset =3D (offset >> 2) & 0x03ffffff; + + insn =3D offset; + } else { + insn =3D OPENRISC_INSN_NOP; + } + + if (early_boot_irqs_disabled) { + copy_to_kernel_nofault(addr, &insn, sizeof(insn)); + } else { + patch_insn_write(addr, insn); + } + return true; +} + +void arch_jump_label_transform_apply(void) +{ + // flush + kick_all_cpus_sync(); +} diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index a9fb9cc6779e..000a9cc10e6f 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -249,6 +249,8 @@ void __init setup_arch(char **cmdline_p) initrd_below_start_ok =3D 1; } #endif + /* perform jump_table sorting before paging_init locks down read only mem= ory */ + jump_label_init(); =20 /* paging_init() sets up the MMU and marks all pages as reserved */ paging_init(); --=20 2.45.2