From nobody Sun Oct 5 09:10:56 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49E8A1E25E8; Wed, 6 Aug 2025 17:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.205.8.231 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754501716; cv=none; b=TdDyG5f0I7nz9J+18l3DKfkeVtiRFBhqhM4HY5Uo9GzySHQBwRMHbFs3hUiPwiHrY+9sw9ZAlQACFnfdEYkbGLFyTkDDX5YNLfBV212YrQ5cwvfzD9u31vMGfmlXNxOHyk4/F0npavGDAzkOlQ0QTlEyaocedGvtFKIzxx5uR70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754501716; c=relaxed/simple; bh=Z1gEMJiFIFjpRGok6tz/RfwwoNl0Rv2K7M7v3c9mDIw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jRO4XdQn3XMwYMhHDqZJlBcq68licWOTiYY3qE+IKgbKt/hmJyyyk7W2Ce/FDCx59hHqObhdin6D24slh9Cc8DRGSJAllNxDRaRUlLqoawAeGVYyCdvuTqhxcKRwFUzygNb15S9paVBw1x6FUd2y+MUuxqkOC2Dt1+MmaCWSLhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz; spf=pass smtp.mailfrom=dujemihanovic.xyz; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b=tt9i4Luy; arc=none smtp.client-ip=37.205.8.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dujemihanovic.xyz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dujemihanovic.xyz header.i=@dujemihanovic.xyz header.b="tt9i4Luy" DKIM-Signature: a=rsa-sha256; bh=fV6lVtW13D0yu6iCI/jPFRPbDpKGqEPIm6A+8YzQujM=; c=relaxed/relaxed; d=dujemihanovic.xyz; h=Subject:Subject:Sender:To:To:Cc:Cc:From:From:Date:Date:MIME-Version:MIME-Version:Content-Type:Content-Type:Content-Transfer-Encoding:Content-Transfer-Encoding:Reply-To:In-Reply-To:In-Reply-To:Message-Id:Message-Id:References:References:Autocrypt:Openpgp; i=@dujemihanovic.xyz; s=default; t=1754501630; v=1; x=1754933630; b=tt9i4LuylpZBhSuTuK9fRqLtp9gqEe9lN2eWeJbj22p4QHsOUDtod8ktIIlSwrngs5kXjlE9 nhSxBJVppkGnhT4bojW9PQIujy0a8Iu35WjrmueQ6ofQvfD1fnEHkUnsj0QhJ+6EcE0/gJGh1lN ebmxopqB4UOqe0Xlu95uHfXkDZqrOG1Ng/EsyHVaqAwF/WpDKYwqHIeey0xWOkLZX7tYFsP3sMY tKobRVGF4LRNZKMCWVwNjTl2PNwJCqwefOf66XIfI5nqYe386q62NauVhAbwD6bUdao2krTrqxv Xxk7w2PjWzQlrIam3J2OzcBJfjU6l7D7QSfP/tqskpchg== Received: by mx.olsak.net (envelope-sender ) with ESMTPS id ee7cda2d; Wed, 06 Aug 2025 19:33:50 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Wed, 06 Aug 2025 19:33:20 +0200 Subject: [PATCH RFC 1/5] dt-bindings: clock: marvell,pxa1908: Add simple-mfd, syscon compatible to apmu Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-pxa1908-genpd-v1-1-16409309fc72@dujemihanovic.xyz> References: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> In-Reply-To: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2431; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=Z1gEMJiFIFjpRGok6tz/RfwwoNl0Rv2K7M7v3c9mDIw=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBmTJ/5Z0mnWXV+/UbX1oWRn2Pp4jWtV4ZapKw8vnbqc3 fnxTE31jlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZhI4VKG/z4zlEJKtGumOxVI hNg6yD227M76wvc6UTnRUD9xQtv3DoZ/dgEqycen7nV9sNT/wTU5KyWHb98M6758mGz5WlTjQYw EAwA= X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Add required syscon and simple-mfd compatibles to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. The simple-mfd compatible allows devices whose registers are completely contained in the APMU range (such as the power domain controller and potentially more) to be children of the clock controller node. Also add an optional power-controller child node to the APMU controller to accommodate the new power domain driver. Signed-off-by: Duje Mihanovi=C4=87 --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 36 ++++++++++++++++++= ---- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 4e78933232b6b925811425f853bedf6e9f01a27d..5e924ebd97e6457191ac021adda= fd22caba48964 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -19,11 +19,15 @@ description: | =20 properties: compatible: - enum: - - marvell,pxa1908-apbc - - marvell,pxa1908-apbcp - - marvell,pxa1908-mpmu - - marvell,pxa1908-apmu + oneOf: + - enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - items: + - const: marvell,pxa1908-apmu + - const: simple-mfd + - const: syscon =20 reg: maxItems: 1 @@ -31,18 +35,38 @@ properties: '#clock-cells': const: 1 =20 + power-controller: + description: | + Optional power domain controller node. + type: object + additionalProperties: true + properties: + compatible: + const: marvell,pxa1908-power-controller + required: - compatible - reg - '#clock-cells' =20 +allOf: + - if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + then: + properties: + power-controller: false + additionalProperties: false =20 examples: # APMU block: - | clock-controller@d4282800 { - compatible =3D "marvell,pxa1908-apmu"; + compatible =3D "marvell,pxa1908-apmu", "simple-mfd", "syscon"; reg =3D <0xd4282800 0x400>; #clock-cells =3D <1>; }; --=20 2.50.1 From nobody Sun Oct 5 09:10:56 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18C391FDD; Wed, 6 Aug 2025 17:33:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.205.8.231 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754501717; cv=none; b=dcebrmBNh4MUyWqM6kqJNy+P4csT+cR4ABu3zehKEDNP88tjFdLGBlP+ZxgSl+GfNh5ECBTxq1HkIUZkEeU77lrwWSlWn/g2oH6ff9wXLo413AhDBmtelJX7PJ2CgSLjv9yZj+1/BoQyIKNJG2RF3zIjZjoiG2wOcX2jCqCcS2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754501717; c=relaxed/simple; bh=NaSKHDpe1UTKIpyJg9w1/zlPE5d3b9jJCH+yLalacOw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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i=@dujemihanovic.xyz; s=default; t=1754501630; v=1; x=1754933630; b=GovyU9nqwNWQBo54lcF4rXe42IT96iZOZf3OMfVm8XBnZ5b5t7k3K/ugVQu7ez43PkFGf28i sNhgiWyqyWbpdXiZOmFzskNuHQGS0OZXCDuwTmAeqRm8T/qaTBnmkAuvBLEiHkCheI5+BXnzfqh GOu7Z6LWUKwg+jsTGzUXu55S5+KLKiYh/RPn0+aUocEOBHQBxIEZSWfV4074xZwvCdRyZ75SW+N qE/Tbxz0XH2XGyEbBgeSZXzS5eF6Zr0nqhMy0hqGTr42j4bhThBxYQK4Yj1B8O0pKxWbNx+J8yj QbW74tRYO2Zi/aswsUhCtqChQRMNJ/RXK3DTJEOzbR4Tg== Received: by mx.olsak.net (envelope-sender ) with ESMTPS id 0bfd0103; Wed, 06 Aug 2025 19:33:50 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Wed, 06 Aug 2025 19:33:21 +0200 Subject: [PATCH RFC 2/5] dt-bindings: power: Add Marvell PXA1908 domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-pxa1908-genpd-v1-2-16409309fc72@dujemihanovic.xyz> References: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> In-Reply-To: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4274; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=NaSKHDpe1UTKIpyJg9w1/zlPE5d3b9jJCH+yLalacOw=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBmTJ/6xZ2Z7XR5sfy77GoOPz/LLwrsUi0okGFf3Zsm2b +M13/Cio5SFQYyLQVZMkSX3v+M13s8iW7dnLzOAmcPKBDKEgYtTACbiv4SR4YO0T2mo+imhjB6F A9tajZZ3BE3qmsRbtlCIs3Drhjlqxgz/Q7fr7eabINq9V1FATthoi1HA3NSw31w7HQ9WSM18fHM RAwA= X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Add device tree bindings for Marvell PXA1908's power domains. Signed-off-by: Duje Mihanovi=C4=87 --- .../power/marvell,pxa1908-power-controller.yaml | 105 +++++++++++++++++= ++++ include/dt-bindings/power/marvell,pxa1908-power.h | 17 ++++ 2 files changed, 122 insertions(+) diff --git a/Documentation/devicetree/bindings/power/marvell,pxa1908-power-= controller.yaml b/Documentation/devicetree/bindings/power/marvell,pxa1908-p= ower-controller.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1cf3a45d56cbb7b75f7204d6560= 16a9a569da186 --- /dev/null +++ b/Documentation/devicetree/bindings/power/marvell,pxa1908-power-control= ler.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/marvell,pxa1908-power-controller.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Power Domain Controller + +maintainers: + - Duje Mihanovi=C4=87 + +description: | + The Marvell PXA1908 SoC includes multiple power domains which can be pow= ered + on/off to save power when different IP cores are not in use. + +properties: + $nodename: + pattern: '^power-controller$' + + compatible: + const: marvell,pxa1908-power-controller + + '#power-domain-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + + description: | + Represents a power domain within the power controller node as docume= nted + in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + reg: + description: | + Power domain index. Valid values are defined in: + "include/dt-bindings/power/marvell,pxa1908-power.h" + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during do= main + power up. + + '#power-domain-cells': + const: 0 + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + clock-controller@d4282800 { + compatible =3D "marvell,pxa1908-apmu", "simple-mfd", "syscon"; + reg =3D <0xd4282800 0x400>; + #clock-cells =3D <1>; + + power-controller { + compatible =3D "marvell,pxa1908-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@PXA1908_POWER_DOMAIN_VPU { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_GPU { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_GPU2D { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_DSI { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_ISP { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; + }; diff --git a/include/dt-bindings/power/marvell,pxa1908-power.h b/include/dt= -bindings/power/marvell,pxa1908-power.h new file mode 100644 index 0000000000000000000000000000000000000000..19b088351af138823505a774ff2= 7203429fe2d97 --- /dev/null +++ b/include/dt-bindings/power/marvell,pxa1908-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Marvell PXA1908 power domains + * + * Copyright 2025, Duje Mihanovi=C4=87 + */ + +#ifndef __DTS_MARVELL_PXA1908_POWER_H +#define __DTS_MARVELL_PXA1908_POWER_H + +#define PXA1908_POWER_DOMAIN_VPU 0 +#define PXA1908_POWER_DOMAIN_GPU 1 +#define PXA1908_POWER_DOMAIN_GPU2D 2 +#define PXA1908_POWER_DOMAIN_DSI 3 +#define PXA1908_POWER_DOMAIN_ISP 4 + +#endif --=20 2.50.1 From nobody Sun Oct 5 09:10:56 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D26CF1E5B72; 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Wed, 06 Aug 2025 19:33:51 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Wed, 06 Aug 2025 19:33:22 +0200 Subject: [PATCH RFC 3/5] pmdomain: marvell: Add PXA1908 power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-pxa1908-genpd-v1-3-16409309fc72@dujemihanovic.xyz> References: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> In-Reply-To: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12221; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=E+XE8dpUP0CEk/XQFr1q2ddKC232C+8ijVTUXYignNE=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBmTJ/6R2nxls2dWR/axXqmP+VEMIp88pFVtnC7++MI1S yLrxE7njlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZhI9wOG/64HV9xeZFCh1i/n rbtDwvzc+hlr3yZqrG63Wp9wJux57n1Ghl3hu7fMWZ3Y7b9VeCnj25mc83JFNVeuXiyuGO1kafT 0AycA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Marvell's PXA1908 SoC has a few power domains for its VPU, GPU, image processor and DSI PHY. Add a driver to control these. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/marvell/Kconfig | 16 + drivers/pmdomain/marvell/Makefile | 3 + .../pmdomain/marvell/pxa1908-power-controller.c | 347 +++++++++++++++++= ++++ 5 files changed, 368 insertions(+) diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 91f04ace35d4b024fafdf6af4e26a179640eb82f..23076ae90e6641dea8e5dbc851d= 041cd7929cee6 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -7,6 +7,7 @@ source "drivers/pmdomain/apple/Kconfig" source "drivers/pmdomain/arm/Kconfig" source "drivers/pmdomain/bcm/Kconfig" source "drivers/pmdomain/imx/Kconfig" +source "drivers/pmdomain/marvell/Kconfig" source "drivers/pmdomain/mediatek/Kconfig" source "drivers/pmdomain/qcom/Kconfig" source "drivers/pmdomain/renesas/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index 7030f44a49df9e91b1c9d1b6d12690a6248671fb..ebc802f13eb953db750f5a9507c= aa64c637a957a 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -5,6 +5,7 @@ obj-y +=3D apple/ obj-y +=3D arm/ obj-y +=3D bcm/ obj-y +=3D imx/ +obj-y +=3D marvell/ obj-y +=3D mediatek/ obj-y +=3D qcom/ obj-y +=3D renesas/ diff --git a/drivers/pmdomain/marvell/Kconfig b/drivers/pmdomain/marvell/Kc= onfig new file mode 100644 index 0000000000000000000000000000000000000000..be2036726cc563ba2a3d1a82ca2= 4763e2148fec2 --- /dev/null +++ b/drivers/pmdomain/marvell/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menu "Marvell PM Domains" + depends on ARCH_MMP || COMPILE_TEST + +config PXA1908_PM_DOMAINS + tristate "Marvell PXA1908 power domains" + depends on OF + depends on PM + default ARCH_MMP && ARM64 + select REGMAP + select PM_GENERIC_DOMAINS + help + Say Y here to enable support for Marvell PXA1908's power domains. + +endmenu diff --git a/drivers/pmdomain/marvell/Makefile b/drivers/pmdomain/marvell/M= akefile new file mode 100644 index 0000000000000000000000000000000000000000..6163bcbcb00ca7256e4c893117b= 7443b6fb195e7 --- /dev/null +++ b/drivers/pmdomain/marvell/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_PXA1908_PM_DOMAINS) +=3D pxa1908-power-controller.o diff --git a/drivers/pmdomain/marvell/pxa1908-power-controller.c b/drivers/= pmdomain/marvell/pxa1908-power-controller.c new file mode 100644 index 0000000000000000000000000000000000000000..a8940e6dc2eaad2b14e9e6d8aa8= 75c11e114b9dd --- /dev/null +++ b/drivers/pmdomain/marvell/pxa1908-power-controller.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2025 Duje Mihanovi=C4=87 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* VPU, GPU, ISP */ +#define APMU_PWR_CTRL_REG 0xd8 +#define APMU_PWR_BLK_TMR_REG 0xdc +#define APMU_PWR_STATUS_REG 0xf0 + +/* DSI */ +#define APMU_DEBUG 0x88 +#define DSI_PHY_DVM_MASK BIT(31) + +#define POWER_ON_LATENCY_US 300 +#define POWER_OFF_LATENCY_US 20 + +struct pxa1908_pd_ctrl { + struct genpd_onecell_data onecell_data; + struct regmap *base; + struct generic_pm_domain *domains[]; +}; + +struct pxa1908_pd_data { + u32 reg_clk_res_ctrl; + u32 hw_mode; + u32 pwr_state; + bool keep_on; + int id; +}; + +struct pxa1908_pd { + const struct pxa1908_pd_data data; + struct generic_pm_domain genpd; + struct clk_bulk_data *clks; + struct device *dev; + bool initialized; + int num_clks; +}; + +static bool pxa1908_pd_is_on(struct pxa1908_pd *pd) +{ + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(pd->dev); + + return regmap_test_bits(ctrl->base, APMU_PWR_STATUS_REG, pd->data.pwr_sta= te); +} + +static int pxa1908_pd_power_on(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(pd->dev); + const struct pxa1908_pd_data *data =3D &pd->data; + unsigned int status; + int ret =3D 0; + + if (pd->clks) + ret =3D clk_bulk_prepare_enable(pd->num_clks, pd->clks); + + regmap_set_bits(ctrl->base, data->reg_clk_res_ctrl, data->hw_mode); + if (data->id !=3D PXA1908_POWER_DOMAIN_ISP) + regmap_write(ctrl->base, APMU_PWR_BLK_TMR_REG, 0x20001fff); + regmap_set_bits(ctrl->base, APMU_PWR_CTRL_REG, data->pwr_state); + + usleep_range(POWER_ON_LATENCY_US, POWER_ON_LATENCY_US * 2); + + ret =3D regmap_read_poll_timeout(ctrl->base, APMU_PWR_STATUS_REG, status, + status & data->pwr_state, 6, 25 * USEC_PER_MSEC); + if (ret =3D=3D -ETIMEDOUT) + dev_err(pd->dev, "timed out powering on domain '%s'\n", pd->genpd.name); + + if (pd->clks) + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); + + return ret; +} + +static int pxa1908_pd_power_off(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(pd->dev); + const struct pxa1908_pd_data *data =3D &pd->data; + unsigned int status; + int ret; + + regmap_clear_bits(ctrl->base, APMU_PWR_CTRL_REG, data->pwr_state); + + usleep_range(POWER_OFF_LATENCY_US, POWER_OFF_LATENCY_US * 2); + + ret =3D regmap_read_poll_timeout(ctrl->base, APMU_PWR_STATUS_REG, status, + !(status & data->pwr_state), 6, 25 * USEC_PER_MSEC); + if (ret =3D=3D -ETIMEDOUT) { + dev_err(pd->dev, "timed out powering off domain '%s'\n", pd->genpd.name); + return ret; + } + + regmap_clear_bits(ctrl->base, data->reg_clk_res_ctrl, data->hw_mode); + + return 0; +} + +static int pxa1908_dsi_power_on(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(pd->dev); + + if (pd->clks) { + int ret =3D clk_bulk_prepare_enable(pd->num_clks, pd->clks); + + if (ret) { + dev_err(pd->dev, "failed to enable clocks for domain '%s': %d\n", + pd->genpd.name, ret); + return ret; + } + } + + regmap_set_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK); + + return 0; +} + +static int pxa1908_dsi_power_off(struct generic_pm_domain *genpd) +{ + struct pxa1908_pd *pd =3D container_of(genpd, struct pxa1908_pd, genpd); + struct pxa1908_pd_ctrl *ctrl =3D dev_get_drvdata(pd->dev); + + regmap_clear_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK); + + if (pd->clks) + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); + + return 0; +} + +#define DOMAIN(_id, _name, ctrl, mode, state) \ + [_id] =3D { \ + .data =3D { \ + .reg_clk_res_ctrl =3D ctrl, \ + .hw_mode =3D BIT(mode), \ + .pwr_state =3D BIT(state), \ + .id =3D _id, \ + }, \ + .genpd =3D { \ + .name =3D _name, \ + .power_on =3D pxa1908_pd_power_on, \ + .power_off =3D pxa1908_pd_power_off, \ + }, \ + } + +static struct pxa1908_pd domains[] =3D { + DOMAIN(PXA1908_POWER_DOMAIN_VPU, "vpu", 0xa4, 19, 2), + DOMAIN(PXA1908_POWER_DOMAIN_GPU, "gpu", 0xcc, 11, 0), + DOMAIN(PXA1908_POWER_DOMAIN_GPU2D, "gpu2d", 0xf4, 11, 6), + DOMAIN(PXA1908_POWER_DOMAIN_ISP, "isp", 0x38, 15, 4), + [PXA1908_POWER_DOMAIN_DSI] =3D { + .genpd =3D { + .name =3D "dsi", + .power_on =3D pxa1908_dsi_power_on, + .power_off =3D pxa1908_dsi_power_off, + /* + * TODO: There is no DSI driver written yet and until then we probably + * don't want to power off the DSI PHY ever. + */ + .flags =3D GENPD_FLAG_ALWAYS_ON, + }, + .data =3D { + /* See above. */ + .keep_on =3D true, + }, + }, +}; + +static void pxa1908_pd_cleanup(struct pxa1908_pd_ctrl *ctrl) +{ + struct pxa1908_pd *pd; + int ret; + + for (int i =3D ARRAY_SIZE(domains) - 1; i >=3D 0; i--) { + pd =3D &domains[i]; + + if (!pd->initialized) + continue; + + ret =3D pm_genpd_remove(&pd->genpd); + if (ret) + dev_err(pd->dev, "failed to remove domain '%s': %d\n", + pd->genpd.name, ret); + if (pxa1908_pd_is_on(pd) && !pd->data.keep_on) + pxa1908_pd_power_off(&pd->genpd); + + clk_bulk_put_all(pd->num_clks, pd->clks); + } +} + +static int +pxa1908_pd_init(struct pxa1908_pd_ctrl *ctrl, struct device_node *node, st= ruct device *dev) +{ + struct pxa1908_pd *pd; + int clk_idx =3D 0, ret; + u32 id; + + ret =3D of_property_read_u32(node, "reg", &id); + if (ret) { + dev_err(dev, "failed to get domain id from reg: %d\n", ret); + return ret; + } + + if (id >=3D ARRAY_SIZE(domains)) { + dev_err(dev, "invalid domain id %d\n", id); + return ret; + } + + pd =3D &domains[id]; + pd->dev =3D dev; + pd->num_clks =3D of_clk_get_parent_count(node); + ctrl->domains[id] =3D &pd->genpd; + + if (pd->num_clks > 0) { + pd->clks =3D devm_kcalloc(dev, pd->num_clks, sizeof(*pd->clks), GFP_KERN= EL); + if (!pd->clks) + return -ENOMEM; + } + + for (int i =3D 0; i < pd->num_clks; i++) { + struct clk *clk =3D of_clk_get(node, i); + + if (IS_ERR(clk)) { + ret =3D PTR_ERR(clk); + dev_err(dev, "failed to get clk for domain '%s': %d\n", + pd->genpd.name, ret); + goto err; + } + + pd->clks[clk_idx++].clk =3D clk; + } + + /* Make sure the state of the hardware is synced with the domain table ab= ove. */ + if (pd->data.keep_on) { + ret =3D pd->genpd.power_on(&pd->genpd); + if (ret) { + dev_err(dev, "failed to power on domain '%s': %d\n", pd->genpd.name, re= t); + goto err; + } + } else { + if (pxa1908_pd_is_on(pd)) { + dev_warn(dev, + "domain '%s' is on despite being default off; powering off\n", + pd->genpd.name); + + ret =3D pxa1908_pd_power_off(&pd->genpd); + if (ret) { + dev_err(dev, "failed to power off domain '%s': %d\n", + pd->genpd.name, ret); + goto err; + } + } + } + + ret =3D pm_genpd_init(&pd->genpd, NULL, !pd->data.keep_on); + if (ret) { + dev_err(dev, "domain '%s' failed to initialize: %d\n", pd->genpd.name, r= et); + goto err; + } + + pd->initialized =3D true; + + return 0; + +err: + clk_bulk_put_all(pd->num_clks, pd->clks); + return ret; +} + +static int pxa1908_pd_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pxa1908_pd_ctrl *ctrl; + struct device_node *node; + int ret; + + ctrl =3D devm_kzalloc(dev, struct_size(ctrl, domains, ARRAY_SIZE(domains)= ), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->base =3D syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(ctrl->base)) { + dev_err(dev, "no regmap available\n"); + return PTR_ERR(ctrl->base); + } + + platform_set_drvdata(pdev, ctrl); + + ctrl->onecell_data.domains =3D ctrl->domains; + ctrl->onecell_data.num_domains =3D ARRAY_SIZE(domains); + + for_each_available_child_of_node(dev->of_node, node) { + ret =3D pxa1908_pd_init(ctrl, node, dev); + if (ret) + goto err; + } + + return of_genpd_add_provider_onecell(dev->of_node, &ctrl->onecell_data); + +err: + pxa1908_pd_cleanup(ctrl); + return ret; +} + +static void pxa1908_pd_remove(struct platform_device *pdev) +{ + pxa1908_pd_cleanup(platform_get_drvdata(pdev)); +} + +static const struct of_device_id pxa1908_pd_match[] =3D { + { + .compatible =3D "marvell,pxa1908-power-controller", + }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_pd_match); + +static struct platform_driver pxa1908_pd_driver =3D { + .probe =3D pxa1908_pd_probe, + .remove =3D pxa1908_pd_remove, + .driver =3D { + .name =3D "pxa1908-power-controller", + .of_match_table =3D pxa1908_pd_match, + }, +}; +module_platform_driver(pxa1908_pd_driver); + +MODULE_AUTHOR("Duje Mihanovi=C4=87 "); +MODULE_DESCRIPTION("Marvell PXA1908 power domain driver"); +MODULE_LICENSE("GPL"); --=20 2.50.1 From nobody Sun Oct 5 09:10:56 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8376F289373; Wed, 6 Aug 2025 17:33:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.205.8.231 ARC-Seal: i=1; a=rsa-sha256; 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Wed, 06 Aug 2025 19:33:52 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Wed, 06 Aug 2025 19:33:23 +0200 Subject: [PATCH RFC 4/5] MAINTAINERS: PXA1908: Add power domain controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-pxa1908-genpd-v1-4-16409309fc72@dujemihanovic.xyz> References: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> In-Reply-To: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1156; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=eJGICosdXjxas1ToQdEVslbW48DwDha7KI4VsUvnZU4=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBmTJ/45pGTdFuJ03XYXV7mHxocLPjnGy+d/Xfbimntcr VZG5V3zjlIWBjEuBlkxRZbc/47XeD+LbN2evcwAZg4rE8gQBi5OAZjIyR6G/0F9f7a0fqxOU2J7 w7F0Kfss1nO/6lQf9AlMrc5eYJ9WLMvI8EbgdZifmF/uyzNXhC89bbdYeKJXpTZA8e3RB/8if2Q GsQMA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Add the new PXA1908 power domain driver under the PXA1908 entry. Also add the clock schema (unintentionally omitted previously) and a link to the PXA1908 mainlining chatroom. Signed-off-by: Duje Mihanovi=C4=87 --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fda151dbf229e48d791e082b1f6be2e43fdb8d1c..905f3027d00e0cd5edf59fdc7dc= f6aa69ec608d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2869,9 +2869,14 @@ ARM/Marvell PXA1908 SOC support M: Duje Mihanovi=C4=87 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +C: irc://irc.oftc.net/pxa1908-mainline +F: Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +F: Documentation/devicetree/bindings/power/marvell,pxa1908-power-controlle= r.yaml F: arch/arm64/boot/dts/marvell/mmp/ F: drivers/clk/mmp/clk-pxa1908*.c +F: drivers/pmdomain/marvell/ F: include/dt-bindings/clock/marvell,pxa1908.h +F: include/dt-bindings/power/marvell,pxa1908-power.h =20 ARM/Mediatek RTC DRIVER M: Eddie Huang --=20 2.50.1 From nobody Sun Oct 5 09:10:56 2025 Received: from mx.olsak.net (mx.olsak.net [37.205.8.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B41928A41C; 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Wed, 06 Aug 2025 19:33:53 +0200 From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Wed, 06 Aug 2025 19:33:24 +0200 Subject: [PATCH RFC 5/5] arm64: dts: marvell: pxa1908: Add power controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250806-pxa1908-genpd-v1-5-16409309fc72@dujemihanovic.xyz> References: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> In-Reply-To: <20250806-pxa1908-genpd-v1-0-16409309fc72@dujemihanovic.xyz> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson Cc: David Wronek , Karel Balej , phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Duje_Mihanovi=C4=87?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3014; i=duje@dujemihanovic.xyz; s=20240706; h=from:subject:message-id; bh=r71dXU2Xc5Ubgu7RiIpKZnrZBJi4GnFBtADrF7xkhxA=; b=owGbwMvMwCW21nBykGv/WmbG02pJDBmTJ/6pnXBOdlbNHyWGuEoz91lLbK4zHM7cOL1uSf4nG fkOG5u1HaUsDGJcDLJiiiy5/x2v8X4W2bo9e5kBzBxWJpAhDFycAjCR6WyMDHdZLaVifnivnSG1 Y4NwJoudZe2Sx4dN18zQ5mu7Nm2KlAEjw8vnsS4aSRuYcpM+bAmpf/j/ufXxZCOdj9IK+R92sZW 3swMA X-Developer-Key: i=duje@dujemihanovic.xyz; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 Add a node for the newly implemented power domain controller. Also add the first two power domain consumers: IOMMU (fixes probing) and framebuffer. Signed-off-by: Duje Mihanovi=C4=87 --- .../marvell/mmp/pxa1908-samsung-coreprimevelte.dts | 1 + arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi | 36 ++++++++++++++++++= +++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte= .dts b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index 47a4f01a7077bfafe2cc50d0e59c37685ec9c2e9..2f175ae48c6a2371c407b3a6ffd= 3cdd577f44e56 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -23,6 +23,7 @@ chosen { fb0: framebuffer@17177000 { compatible =3D "simple-framebuffer"; reg =3D <0 0x17177000 0 (480 * 800 * 4)>; + power-domains =3D <&pd PXA1908_POWER_DOMAIN_DSI>; width =3D <480>; height =3D <800>; stride =3D <(480 * 4)>; diff --git a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi b/arch/arm64/boot= /dts/marvell/mmp/pxa1908.dtsi index cf2b9109688ce560eec8a1397251ead68d78a239..630e99f2c309dca0872d824a098= ac93b6e55c3a4 100644 --- a/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi +++ b/arch/arm64/boot/dts/marvell/mmp/pxa1908.dtsi @@ -3,6 +3,7 @@ =20 #include #include +#include =20 / { model =3D "Marvell Armada PXA1908"; @@ -79,6 +80,7 @@ smmu: iommu@c0010000 { #iommu-cells =3D <1>; interrupts =3D , ; + power-domains =3D <&pd PXA1908_POWER_DOMAIN_VPU>; status =3D "disabled"; }; =20 @@ -291,9 +293,41 @@ sdh2: mmc@81000 { }; =20 apmu: clock-controller@82800 { - compatible =3D "marvell,pxa1908-apmu"; + compatible =3D "marvell,pxa1908-apmu", "simple-mfd", "syscon"; reg =3D <0x82800 0x400>; #clock-cells =3D <1>; + + pd: power-controller { + compatible =3D "marvell,pxa1908-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + power-domain@PXA1908_POWER_DOMAIN_VPU { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_GPU { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_GPU2D { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_DSI { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@PXA1908_POWER_DOMAIN_ISP { + reg =3D ; + #power-domain-cells =3D <0>; + }; + }; }; }; }; --=20 2.50.1