From nobody Sun Oct 5 09:10:54 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18BF2524F; Tue, 5 Aug 2025 23:49:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754437801; cv=none; b=kSDavQ9MZF8ZHuimz910FUvFUOsfLsLU8E//azF9WENkXLFMnXPCicZRnZ4ixaMZXtX9knSCHxXvBPOxW/aDzjJhVUecAzfeszSSUPIqenW1tF3b5vVppeDCRxcnLxSmuOPp+HSRkAZ75yssZMG0MwM4v0DN6sklB+d/JoeXTj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754437801; c=relaxed/simple; bh=p2p4vKS5wYDCxNQLe3U+0FgrcL9pSAk87OCo+vsR5pM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j3qH1c4kaMdeuTnvHdZnjdvkkOlQbCTby5UvkgURD3jKHJIb+FYlpmXOxpR0sjO5VdQMtEu6rAtL3xPih9Zl3lFmIzwKJuKuMVc3zX/BC97C2GWA/TbmqzZgJlku2Vj/0yCvXJzHivWaaSgx2arUYLT+W8XcfLrqyRyMVwM0pK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bIsXxALN; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bIsXxALN" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 575NnpVa387998; Tue, 5 Aug 2025 18:49:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1754437791; bh=OWll8aXw8aHwO/nZCoAePnctU5zQKd6s1MSx1yOQJ/c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bIsXxALNZCxgM9MZpL8IVa3U7/riBpqlbzXjh+MAmq05d3w1mVfrqxgkhISs2Jbpr 3EuRvOOaRRhgFNMuSPQOFKdhxxXi8keEzUivJFii73yYtpQ0s/twmw1VkR4biyZto3 FIrFjpiHRWI+RcVs5FjDmHqJ8NtC/AuUjBwcsqyM= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 575NnpOp3149163 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 5 Aug 2025 18:49:51 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 5 Aug 2025 18:49:50 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 5 Aug 2025 18:49:50 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 575Nno6n2624898; Tue, 5 Aug 2025 18:49:50 -0500 From: Judith Mendez To: Judith Mendez , Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Ulf Hansson CC: Vignesh Raghavendra , Santosh Shilimkar , , , , Subject: [PATCH 1/4] dt-bindings: hwinfo: Add second register range for GP_SW Date: Tue, 5 Aug 2025 18:49:47 -0500 Message-ID: <20250805234950.3781367-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805234950.3781367-1-jm@ti.com> References: <20250805234950.3781367-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This adds a second register range in ti,k3-socinfo. This register range can also be used to detect silicon revisions. AM62px SR1.0, SR1.1, and SR1.2 can only be distinguished with GP_SW registers, so increase maximum items to 2 for reg property and update the example. Signed-off-by: Judith Mendez --- .../devicetree/bindings/hwinfo/ti,k3-socinfo.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/= Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml index dada28b47ea0..3b656fc0cb5a 100644 --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml @@ -24,7 +24,8 @@ properties: - const: ti,am654-chipid =20 reg: - maxItems: 1 + maxItems: 2 + minItems: 1 =20 required: - compatible @@ -34,7 +35,9 @@ additionalProperties: false =20 examples: - | - chipid@43000014 { + chipid@14 { compatible =3D "ti,am654-chipid"; - reg =3D <0x43000014 0x4>; + reg =3D <0x43000014 0x4>, + <0x43000230 0x10>; + bootph-all; }; --=20 2.49.0 From nobody Sun Oct 5 09:10:54 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE27A2BDC28; Tue, 5 Aug 2025 23:50:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754437814; cv=none; b=av8ox0pLxcXcAsG301faUWo6BPH9VNshujeGppshgT5l+svtz+TQbayngeV8mLwBI0M+v6opH6sNi8///5BQKnyRxgFXIkdBl6V1sToOg/4o4QcFb0MOPy7UzGd/evfx8WI/Lw/TQpZzDwOme8VCqx32XuiYylF3C04UVrrxCAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754437814; c=relaxed/simple; bh=y98rTCimIcBocg28bf5ZEqKcHSDMG73+7zkKaAH92OA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pkvL892Z152/75TSMerWCMht0zICKh+hWFYE8cYIkK1HZP3hoiPIMZ8NcB2pBd2ikMqfXuThcuBFfZSPUcRlzttg18qPRP3usOam6yIFvoIwr/u76cf5HtZbXtVvKkRnFCf6DxA9BM4SiYUyA6+cEC7xvRA7/FMMiCgBDR6Ph5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=AXk1ifyi; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="AXk1ifyi" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 575NnpSv4145370; Tue, 5 Aug 2025 18:49:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1754437791; bh=UvHxejtAmgIijopXkaZv3LCB715mK7PNsMCmeGs/1aQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AXk1ifyiWw/PWZOtRCvyC/xEbzQ8A3XnNuPXKZiktd9q/W33Ru/MUzXJmPwl6oxK5 ryhZhdtJvR+hYk7VDldLvlXTPr3CbnxHi77e3riLcDx3fT4GWuxgD6LQ3BLxbfKIPM +FHUzBbecX5SBZiHRfyiqzDjVWEjRp3EBd7vuCSE= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 575Nnpgp3796005 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Tue, 5 Aug 2025 18:49:51 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Tue, 5 Aug 2025 18:49:50 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Tue, 5 Aug 2025 18:49:50 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 575Nno6o2624898; Tue, 5 Aug 2025 18:49:50 -0500 From: Judith Mendez To: Judith Mendez , Nishanth Menon , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Ulf Hansson CC: Vignesh Raghavendra , Santosh Shilimkar , , , , Subject: [PATCH 2/4] soc: ti: k3-socinfo: Add support for AM62P variants Date: Tue, 5 Aug 2025 18:49:48 -0500 Message-ID: <20250805234950.3781367-3-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805234950.3781367-1-jm@ti.com> References: <20250805234950.3781367-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This adds a support for detecting AM62P SR1.0, SR1.1, SR1.2. On AM62P, silicon revision is discovered with GP_SW1 instead of JTAGID register, so introduce GP_SW register range to determine SoC revision. Signed-off-by: Judith Mendez --- drivers/soc/ti/k3-socinfo.c | 82 +++++++++++++++++++++++++++++++++---- 1 file changed, 74 insertions(+), 8 deletions(-) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index d716be113c84..9daeced656d6 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -15,6 +15,7 @@ #include =20 #define CTRLMMR_WKUP_JTAGID_REG 0 +#define CTRLMMR_WKUP_GP_SW1_REG 4 /* * Bits: * 31-28 VARIANT Device variant @@ -62,10 +63,63 @@ static const struct k3_soc_id { { JTAG_ID_PARTNO_AM62LX, "AM62LX" }, }; =20 +static const struct regmap_config k3_chipinfo_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + static const char * const j721e_rev_string_map[] =3D { "1.0", "1.1", "2.0", }; =20 +static const char * const am62p_gpsw_rev_string_map[] =3D { + "1.0", "1.1", "1.2", +}; + +static int +k3_chipinfo_get_variant_alternate(struct platform_device *pdev, unsigned i= nt partno, u32 *variant) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + u32 offset; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D regmap_init_mmio(dev, base, &k3_chipinfo_regmap_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + switch (partno) { + case JTAG_ID_PARTNO_AM62PX: + offset =3D CTRLMMR_WKUP_GP_SW1_REG; + break; + default: + offset =3D CTRLMMR_WKUP_GP_SW1_REG; + } + + ret =3D regmap_read(regmap, offset, variant); + + if (ret < 0) + return ret; + + return 0; +} + +static bool k3_chipinfo_variant_in_gp_sw(unsigned int partno) +{ + switch (partno) { + case JTAG_ID_PARTNO_AM62PX: + return true; + default: + return false; + } +} + static int k3_chipinfo_partno_to_names(unsigned int partno, struct soc_device_attribute *soc_dev_attr) @@ -83,8 +137,10 @@ k3_chipinfo_partno_to_names(unsigned int partno, =20 static int k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant, - struct soc_device_attribute *soc_dev_attr) + struct soc_device_attribute *soc_dev_attr, u32 gp_sw1) { + u32 gpsw_variant =3D gp_sw1 % 16; + switch (partno) { case JTAG_ID_PARTNO_J721E: if (variant >=3D ARRAY_SIZE(j721e_rev_string_map)) @@ -92,6 +148,13 @@ k3_chipinfo_variant_to_sr(unsigned int partno, unsigned= int variant, soc_dev_attr->revision =3D kasprintf(GFP_KERNEL, "SR%s", j721e_rev_string_map[variant]); break; + case JTAG_ID_PARTNO_AM62PX: + /* Always parse AM62P variant from GP_SW1 */ + if (gpsw_variant >=3D ARRAY_SIZE(am62p_gpsw_rev_string_map)) + goto err_unknown_variant; + soc_dev_attr->revision =3D kasprintf(GFP_KERNEL, "SR%s", + am62p_gpsw_rev_string_map[gpsw_variant]); + break; default: variant++; soc_dev_attr->revision =3D kasprintf(GFP_KERNEL, "SR%x.0", @@ -107,12 +170,6 @@ k3_chipinfo_variant_to_sr(unsigned int partno, unsigne= d int variant, return -ENODEV; } =20 -static const struct regmap_config k3_chipinfo_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, -}; - static int k3_chipinfo_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -121,6 +178,7 @@ static int k3_chipinfo_probe(struct platform_device *pd= ev) struct soc_device *soc_dev; struct regmap *regmap; void __iomem *base; + u32 gp_sw1_val =3D 0; u32 partno_id; u32 variant; u32 jtag_id; @@ -163,7 +221,15 @@ static int k3_chipinfo_probe(struct platform_device *p= dev) goto err; } =20 - ret =3D k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr); + if (k3_chipinfo_variant_in_gp_sw(partno_id)) { + ret =3D k3_chipinfo_get_variant_alternate(pdev, partno_id, &gp_sw1_val); + if (ret < 0) { + dev_err(dev, "Failed to read GP_SW1: %d\n", ret); + goto err; + } + } + + ret =3D k3_chipinfo_variant_to_sr(partno_id, variant, soc_dev_attr, gp_sw= 1_val); if (ret) { dev_err(dev, "Unknown SoC SR[0x%08X]: %d\n", jtag_id, ret); goto err; --=20 2.49.0 From nobody Sun Oct 5 09:10:54 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9946B291C1B; Tue, 5 Aug 2025 23:50:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" This adds SDHCI_AM654_QUIRK_DISABLE_HS400 quirk which shall be used to disable HS400 support. AM62P SR1.0 and SR1.1 do not support HS400 due to errata i2458 [0] so disable HS400 for these SoC revisions. [0] https://www.ti.com/lit/er/sprz574a/sprz574a.pdf Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index e4fc345be7e5..b7d2adff3277 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -156,6 +156,7 @@ struct sdhci_am654_data { =20 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) #define SDHCI_AM654_QUIRK_SUPPRESS_V1P8_ENA BIT(1) +#define SDHCI_AM654_QUIRK_DISABLE_HS400 BIT(2) }; =20 struct window { @@ -820,6 +821,9 @@ static int sdhci_am654_init(struct sdhci_host *host) if (ret) goto err_cleanup_host; =20 + if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_DISABLE_HS400) + host->mmc->caps2 &=3D ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); + ret =3D __sdhci_add_host(host); if (ret) goto err_cleanup_host; @@ -883,6 +887,12 @@ static int sdhci_am654_get_of_property(struct platform= _device *pdev, return 0; } =20 +static const struct soc_device_attribute sdhci_am654_descope_hs400[] =3D { + { .family =3D "AM62PX", .revision =3D "SR1.0" }, + { .family =3D "AM62PX", .revision =3D "SR1.1" }, + { /* sentinel */ } +}; + static const struct of_device_id sdhci_am654_of_match[] =3D { { .compatible =3D "ti,am654-sdhci-5.1", @@ -970,6 +980,12 @@ static int sdhci_am654_probe(struct platform_device *p= dev) if (ret) return dev_err_probe(dev, ret, "parsing dt failed\n"); =20 + soc =3D soc_device_match(sdhci_am654_descope_hs400); + if (soc) { + dev_err(dev, "Disable descoped HS400 mode for this silicon revision\n"); + sdhci_am654->quirks |=3D SDHCI_AM654_QUIRK_DISABLE_HS400; + } + host->mmc_host_ops.start_signal_voltage_switch =3D sdhci_am654_start_sign= al_voltage_switch; host->mmc_host_ops.execute_tuning =3D sdhci_am654_execute_tuning; =20 --=20 2.49.0 From nobody Sun Oct 5 09:10:54 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B76E291C1B; Tue, 5 Aug 2025 23:50:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" This adds GP_SW register range to k3-am62p-j722s-common-wakeup which will be used to determine SoC revision. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arc= h/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6757b37a9de3..48778c49d8fc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -18,7 +18,8 @@ wkup_conf: bus@43000000 { =20 chipid: chipid@14 { compatible =3D "ti,am654-chipid"; - reg =3D <0x14 0x4>; + reg =3D <0x14 0x4>, + <0x230 0x10>; bootph-all; }; =20 --=20 2.49.0